/*
 FreeRTOS V6.0.4 - Copyright (C) 2010 Real Time Engineers Ltd.

 ***************************************************************************
 *                                                                         *
 * If you are:                                                             *
 *                                                                         *
 *    + New to FreeRTOS,                                                   *
 *    + Wanting to learn FreeRTOS or multitasking in general quickly       *
 *    + Looking for basic training,                                        *
 *    + Wanting to improve your FreeRTOS skills and productivity           *
 *                                                                         *
 * then take a look at the FreeRTOS eBook                                  *
 *                                                                         *
 *        "Using the FreeRTOS Real Time Kernel - a Practical Guide"        *
 *                  http://www.FreeRTOS.org/Documentation                  *
 *                                                                         *
 * A pdf reference manual is also available.  Both are usually delivered   *
 * to your inbox within 20 minutes to two hours when purchased between 8am *
 * and 8pm GMT (although please allow up to 24 hours in case of            *
 * exceptional circumstances).  Thank you for your support!                *
 *                                                                         *
 ***************************************************************************

 This file is part of the FreeRTOS distribution.

 FreeRTOS is free software; you can redistribute it and/or modify it under
 the terms of the GNU General Public License (version 2) as published by the
 Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
 ***NOTE*** The exception to the GPL is included to allow you to distribute
 a combined work that includes FreeRTOS without being obliged to provide the
 source code for proprietary components outside of the FreeRTOS kernel.
 FreeRTOS is distributed in the hope that it will be useful, but WITHOUT
 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 more details. You should have received a copy of the GNU General Public
 License and the FreeRTOS license exception along with FreeRTOS; if not it
 can be viewed here: http://www.freertos.org/a00114.html and also obtained
 by writing to Richard Barry, contact details for whom are available on the
 FreeRTOS WEB site.

 1 tab == 4 spaces!

 http://www.FreeRTOS.org - Documentation, latest information, license and
 contact details.

 http://www.SafeRTOS.com - A version that is certified for use in safety
 critical systems.

 http://www.OpenRTOS.com - Commercial support, development, porting,
 licensing and training services.
 */

/*
 * Creates all the demo application tasks, then starts the scheduler.  The WEB
 * documentation provides more details of the standard demo application tasks.
 * In addition to the standard demo tasks, the following tasks and tests are
 * defined and/or created within this file:
 *
 * "uIP" task -  This is the task that handles the uIP stack.  All TCP/IP
 * processing is performed in this task.  It manages the WEB server functionality.
 *
 * "Check" task -  This only executes every five seconds but has a high priority
 * to ensure it gets processor time.  Its main function is to check that all the
 * standard demo tasks are still operational.  An error found in any task will be
 * latched in the ulErrorCode variable for display through the WEB server (the
 * error code is displayed at the foot of the table that contains information on
 * the state of each task).
 *
 * "Reg test" tasks - These fill the registers with known values, then check
 * that each register still contains its expected value.  Each task uses
 * different values.  The tasks run with very low priority so get preempted very
 * frequently.  A register containing an unexpected value is indicative of an
 * error in the context switching mechanism.
 *
 */

/* Standard includes. */
#include <stdio.h>
//#include <stdarg.h>

/* Scheduler includes. */
#include "FreeRTOS.h"
#include "task.h"
#include "queue.h"
#include "semphr.h"

/* Demo app includes. */
#include "BlockQ.h"
#include "death.h"
#include "blocktim.h"
#include "flash.h"
#include "partest.h"
#include "semtest.h"
#include "PollQ.h"
#include "GenQTest.h"
#include "QPeek.h"
#include "recmutex.h"
#include "IntQueue.h"
#include "comtest2.h"
#include "uart0.h"
#include "uart1.h"
#include "uart2.h"
#include "console_reader.h"
#include "webcam.h"
#include "riadenie.h"
#include "rfid_reader.h"
#include "flashUtilities.h"
#include "LCD.h"
#include "klavesnica.h"

//#include "printf-stdarg.h"

#define MCF_UART_UCR_TXC(x) (((x)&0x03)<<2)

#define putchar(c) outbyte(c)
static void outbyte(char ch) {
	(void) uart1_SendChar(ch);
}
/*-----------------------------------------------------------*/

/* The time between cycles of the 'check' functionality - as described at the
 top of this file. */
#define mainCHECK_TASK_PERIOD					( ( portTickType ) 5000 / portTICK_RATE_MS )

/* Task priorities. */
#define mainQUEUE_POLL_PRIORITY				( tskIDLE_PRIORITY + 2 )
#define mainCHECK_TASK_PRIORITY				( tskIDLE_PRIORITY + 3 )
#define mainSEM_TEST_PRIORITY				( tskIDLE_PRIORITY + 1 )
#define mainBLOCK_Q_PRIORITY				( tskIDLE_PRIORITY + 2 )
#define mainGEN_QUEUE_TASK_PRIORITY			( tskIDLE_PRIORITY )

/* The WEB server task uses more stack than most other tasks because of its
 reliance on using sprintf(). */
#define mainBASIC_WEB_STACK_SIZE			( configMINIMAL_STACK_SIZE * 2 )

/*
 * Configure the hardware for the demo.
 */
static void prvSetupHardware(void);

/*
 * Implements the 'check' task functionality as described at the top of this
 * file.
 */
static void prvCheckTask(void *pvParameters);

/*
 * The task that implements the WEB server.
 */
extern void vuIP_Task(void *pvParameters);

/*
 * Implement the 'Reg test' functionality as described at the top of this file.
 */
static void vRegTest1Task(void *pvParameters);
static void vRegTest2Task(void *pvParameters);

/*-----------------------------------------------------------*/

/* Counters used to detect errors within the reg test tasks. */
static volatile unsigned portLONG ulRegTest1Counter = 0x11111111,
		ulRegTest2Counter = 0x22222222;

/* Any errors that the check task finds in any tasks are latched into 
 ulErrorCode, and then displayed via the WEB server. */
static unsigned portLONG ulErrorCode = 0UL;

/* Additional register read/write macros (missing in headers) */
#define MCF_CIM_CCON                   (*(vuint16*)(void*)(&__IPSBAR[0x00110004]))

/* Bit definitions and macros for MCF_CIM_CCON */
#define MCF_CIM_CCON_SZEN              (0x00000040)
#define MCF_CIM_CCON_PSTEN             (0x00000020)
#define MCF_CIM_CCON_BME               (0x00000008)
#define MCF_CIM_CCON_BMT(x)            (((x)&0x00000007)<<0)

/*-----------------------------------------------------------*/
static void init_uarts(void);
static void init_pin_assignments(void);
static void init_interrupt_controller(void);
static void init_eport(void);

portTickType xTimeStart = 0, xTimePrev = 0;
portTickType IdleTime = 0;
uint8 vykon = 200;
uint8 maxVykon = 0;


//extern int printf(const char *format, ...);

int main(void) {

	/****START OF BLOCK: uvodna konfiguracia periferii*****************************************/
	/* inicializcia HW*/
	prvSetupHardware();
	uart0_Init(); /* UART0 inicializacia*/
	uart1_Init();
	uart2_Init();
	//init_uarts(); /* Inicializacia UARTov*/
	init_pin_assignments(); /* Inicializacia Pinov*/
	init_interrupt_controller(); /* Inicializacia kontrolera preruseni*/
	LCD_Init();
	init_eport(); //Inicializacia IRQ4 -> klavesnica
	//----END OF BLOCK: uvodna konfiguracia periferii------------------------------------------

	CFMinit(); //Inicializacia Flash modulu


	komOutSocketQueue = xQueueCreate(numQueue, sizeQueue); // Vytvorenie queue pre posielanie out prikazov cez socket
	komInSocketQueue = xQueueCreate(numQueue, sizeQueue); // Vytvorenie queue pre priate prikazi cez socket

	casovacQueue = xQueueCreate(casovacNumQueue, casovacSizeQueue); // Vytvorenie queue pre timer

	klavesnicaGetKeyMutex = xQueueCreateMutex(); //Vytvorenie mutexu pre obsluhu klavesnice
	xSemaphoreTake(klavesnicaGetKeyMutex,10);

	/* Create the WEB server task. */
	xTaskCreate( vuIP_Task, ( signed portCHAR * ) "uIP", mainBASIC_WEB_STACK_SIZE+500, NULL, tskIDLE_PRIORITY + 2, NULL );

	/* Start the standard demo tasks. */
	vStartLEDFlashTasks(tskIDLE_PRIORITY);
	vStartControlTask(tskIDLE_PRIORITY + 1);
	vStartRfidTask(tskIDLE_PRIORITY + 1);

	//vStartBlockingQueueTasks(mainBLOCK_Q_PRIORITY);
	//vCreateBlockTimeTasks();
	//vStartSemaphoreTasks(mainSEM_TEST_PRIORITY);
	//vStartPolledQueueTasks(mainQUEUE_POLL_PRIORITY);
	//vStartGenericQueueTasks(mainGEN_QUEUE_TASK_PRIORITY);
	//vStartQueuePeekTasks();
	//vStartRecursiveMutexTasks();
	vStartConsole_reader(tskIDLE_PRIORITY + 1, 250);
	CamPictureMutex = xQueueCreateMutex(); //Vytvorenie Mutexu ->Citanie obrazku z kamery

	xTaskCreate( picture_taker, ( signed portCHAR * ) "PicTake", 200, NULL, tskIDLE_PRIORITY + 2, NULL );

	/* Start the reg test tasks - defined in this file. */
	//xTaskCreate( vRegTest1Task, ( signed portCHAR * ) "Reg1", configMINIMAL_STACK_SIZE, ( void * ) &ulRegTest1Counter, tskIDLE_PRIORITY, NULL );
	//xTaskCreate( vRegTest2Task, ( signed portCHAR * ) "Reg2", configMINIMAL_STACK_SIZE, ( void * ) &ulRegTest2Counter, tskIDLE_PRIORITY, NULL );

	/* Create the check task. */
	//xTaskCreate( prvCheckTask, ( signed portCHAR * ) "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );


	/* Start the scheduler. */
	vTaskStartScheduler();

	/* Will only get here if there was insufficient heap to create the idle
	 task. */
	for (;;)
		asm("nop")
		;
}

/*********************************************************************
 * init_eport - Edge Port Module (EPORT)                              *
 **********************************************************************/
static void init_eport(void) {
	/* Pins 1,7 configured as GPIO inputs
	 Pin 4 configured as rising edge triggered input
	 */
	MCF_EPORT_EPDDR(0) = 0;
	MCF_EPORT_EPDDR(1) = 0;
	MCF_EPORT_EPPAR(0) = MCF_EPORT_EPPAR_EPPA4(0x1);
	MCF_EPORT_EPPAR(1) = 0;
	MCF_EPORT_EPIER(0) = MCF_EPORT_EPIER_EPIE4;
	MCF_EPORT_EPIER(1) = 0;
}

/********************************************************************************************
 * Function: init_uarts
 * Arguments: void
 * Return:  void
 * Comment: Inicializacia UARTov
 *******************************************************************************************/

static void init_uarts(void) {
	/* Configure UART 0 (first UART channel)
	 Baud Rate = 38400
	 8 data bits, 1 stop bit, No parity
	 /CTS input has no effect on the transmitter
	 /RTS output is not affected by receiver or transmitter
	 //	 */
	//
	//	/* UART 0: Reset transmitter, receiver and mode register pointer */
	//	MCF_UART0_UCR = MCF_UART_UCR_MISC(0x3);
	//	MCF_UART0_UCR = MCF_UART_UCR_MISC(0x2);
	//	MCF_UART0_UCR = MCF_UART_UCR_MISC(0x1);
	//
	//	/* UART 0 Mode Registers */
	//	MCF_UART0_UMR1 = MCF_UART_UMR_PM(0x2) | MCF_UART_UMR_BC(0x3);
	//	MCF_UART0_UMR1 = MCF_UART_UMR_SB(0x7);
	//
	//	/* UART 0 Clocking */
	//	MCF_UART0_UCSR = MCF_UART_UCSR_RCS(0xd) | MCF_UART_UCSR_TCS(0xd);
	//	MCF_UART0_UBG1 = 0;
	//	MCF_UART0_UBG2 = 0x30;
	//
	//	/* UART 0 Interrupt mask */
	//	MCF_UART0_UIMR = MCF_UART_UIMR_FFULL_RXRDY | MCF_UART_UIMR_TXRDY;
	//
	//	/* UART 0 Miscellaneous */
	//	MCF_UART0_UACR = 0;

	/* UART 0: Enable receiver and transmitter */
	//MCF_UART1_UCR = MCF_UART_UCR_TXC(0x1);
	/* UART 0: Reset transmitter, receiver and mode register pointer */
	MCF_UART1_UCR = MCF_UART_UCR_MISC(0x3);
	MCF_UART1_UCR = MCF_UART_UCR_MISC(0x2);
	MCF_UART1_UCR = MCF_UART_UCR_MISC(0x1);

	/* UART 0 Mode Registers */
	MCF_UART1_UMR1 = MCF_UART_UMR_PM(0x2) | MCF_UART_UMR_BC(0x3);
	MCF_UART1_UMR1 = MCF_UART_UMR_SB(0x7);

	/* UART 0 Clocking */
	MCF_UART1_UCSR = MCF_UART_UCSR_RCS(0xd) | MCF_UART_UCSR_TCS(0xd);
	MCF_UART1_UBG1 = 0;
	MCF_UART1_UBG2 = 0x30;

	/* UART 0 Interrupt mask */
	MCF_UART1_UIMR = MCF_UART_UIMR_FFULL_RXRDY | MCF_UART_UIMR_TXRDY;

	/* UART 0 Miscellaneous */
	MCF_UART1_UACR = 0;

	/* UART 0: Enable receiver and transmitter */
	MCF_UART1_UCR = MCF_UART_UCR_TXC(0x1);

}

/*--END OF FUNCTION: init_uarts---------------------------------------------------*/

/********************************************************************************************
 * Function: init_interrupt_controller
 * Arguments: void
 * Return:  void
 * Comment: Inicializacia interrupt kontrolera
 *******************************************************************************************/

static void init_interrupt_controller(void) {
	/* Configured interrupt sources in order of priority...
	 Level 7:  External interrupt /IRQ7, (initially masked)
	 Level 6:  External interrupt /IRQ6, (initially masked)
	 Level 5:  External interrupt /IRQ5, (initially masked)
	 Level 4:  UART1 interrupt
	 External interrupt /IRQ4, (initially masked)
	 Level 3:  External interrupt /IRQ3, (initially masked)
	 Level 2:  External interrupt /IRQ2, (initially masked)
	 Level 1:  External interrupt /IRQ1, (initially masked)
	 */
	MCF_INTC0_ICR01 = 0;
	MCF_INTC0_ICR02 = 0;
	MCF_INTC0_ICR03 = 0;
	MCF_INTC0_ICR04 = 0;
	MCF_INTC0_ICR05 = 0;
	MCF_INTC0_ICR06 = 0;
	MCF_INTC0_ICR07 = 0;
	MCF_INTC0_ICR08 = 0;
	MCF_INTC0_ICR09 = 0;
	MCF_INTC0_ICR10 = 0;
	MCF_INTC0_ICR11 = 0;
	MCF_INTC0_ICR12 = 0;
	MCF_INTC0_ICR13 = MCF_INTC_ICR_IL(0x4) | MCF_INTC_ICR_IP(0x4);
	MCF_INTC0_ICR14 = MCF_INTC_ICR_IL(0x4) | MCF_INTC_ICR_IP(0x2);
	MCF_INTC0_ICR15 = MCF_INTC_ICR_IL(0x4) | MCF_INTC_ICR_IP(0x3);
	MCF_INTC0_ICR17 = 0;
	MCF_INTC0_ICR18 = 0;
	MCF_INTC0_ICR19 = 0;
	MCF_INTC0_ICR20 = 0;
	MCF_INTC0_ICR21 = 0;
	MCF_INTC0_ICR22 = 0;
	MCF_INTC0_ICR23 = 0;
	MCF_INTC0_ICR24 = 0;
	MCF_INTC0_ICR25 = 0;
	MCF_INTC0_ICR26 = 0;
	MCF_INTC0_ICR27 = 0;
	MCF_INTC0_ICR28 = 0;
	MCF_INTC0_ICR29 = 0;
	MCF_INTC0_ICR30 = 0;
	MCF_INTC0_ICR31 = 0;
	MCF_INTC0_ICR32 = 0;
	MCF_INTC0_ICR33 = 0;
	MCF_INTC0_ICR34 = 0;
	MCF_INTC0_ICR35 = 0;
	MCF_INTC0_ICR36 = 0;
	MCF_INTC0_ICR41 = 0;
	MCF_INTC0_ICR42 = 0;
	MCF_INTC0_ICR43 = 0;
	MCF_INTC0_ICR44 = 0;
	MCF_INTC0_ICR45 = 0;
	MCF_INTC0_ICR46 = 0;
	MCF_INTC0_ICR47 = 0;
	MCF_INTC0_ICR48 = 0;
	MCF_INTC0_ICR49 = 0;
	MCF_INTC0_ICR50 = 0;
	MCF_INTC0_ICR51 = 0;
	MCF_INTC0_ICR52 = 0;
	MCF_INTC0_ICR55 = 0;
	MCF_INTC0_ICR56 = 0;
	MCF_INTC0_ICR59 = 0;
	MCF_INTC0_ICR60 = 0;
	MCF_INTC0_ICR61 = 0;
	MCF_INTC0_ICR62 = 0;
	MCF_INTC0_ICR63 = 0;
	MCF_INTC1_ICR32 = 0;
	MCF_INTC1_ICR33 = 0;
	MCF_INTC1_ICR34 = 0;
	MCF_INTC1_ICR35 = 0;
	MCF_INTC1_ICR36 = 0;
	MCF_INTC1_ICR37 = 0;
	MCF_INTC1_ICR38 = 0;
	MCF_INTC1_ICR39 = 0;
	MCF_INTC0_IMRH = 0xffffffff;
	MCF_INTC0_IMRL = MCF_INTC_IMRL_INT_MASK31 | MCF_INTC_IMRL_INT_MASK30
			| MCF_INTC_IMRL_INT_MASK29 | MCF_INTC_IMRL_INT_MASK28
			| MCF_INTC_IMRL_INT_MASK27 | MCF_INTC_IMRL_INT_MASK26
			| MCF_INTC_IMRL_INT_MASK25 | MCF_INTC_IMRL_INT_MASK24
			| MCF_INTC_IMRL_INT_MASK23 | MCF_INTC_IMRL_INT_MASK22
			| MCF_INTC_IMRL_INT_MASK21 | MCF_INTC_IMRL_INT_MASK20
			| MCF_INTC_IMRL_INT_MASK19 | MCF_INTC_IMRL_INT_MASK18
			| MCF_INTC_IMRL_INT_MASK17 | MCF_INTC_IMRL_INT_MASK16
			| MCF_INTC_IMRL_INT_MASK12 | MCF_INTC_IMRL_INT_MASK11
			| MCF_INTC_IMRL_INT_MASK10 | MCF_INTC_IMRL_INT_MASK9
			| MCF_INTC_IMRL_INT_MASK8 | MCF_INTC_IMRL_INT_MASK7
			| MCF_INTC_IMRL_INT_MASK6 | MCF_INTC_IMRL_INT_MASK5
			| MCF_INTC_IMRL_INT_MASK3 | MCF_INTC_IMRL_INT_MASK2
			| MCF_INTC_IMRL_INT_MASK1;
	MCF_INTC1_IMRH = 0xffffffff;
	MCF_INTC1_IMRL = 0xfffffffe;
}

/*--END OF FUNCTION: init_interrupt_controller---------------------------------------------------*/

/*-----------------------------------------------------------*/

unsigned portLONG ulGetErrorCode(void) {
	/* Returns the error code for display via the WEB server. */
	return ulErrorCode;
}
/*-----------------------------------------------------------*/

void prvSetupHardware(void) {
	__attribute__ ((section(".cfmconfig")))
	static const unsigned long _cfm[6] = { 0, /* KEY_UPPER 0x00000400 */
	0, /* KEY_LOWER 0x00000404 */
	0, /* CFMPROT 0x00000408 */
	0, /* CFMSACC 0x0000040C */
	0, /* CFMDACC 0x00000410 */
	0, /* CFMSEC 0x00000414 */
	};

	/* Just to stop compiler warnings. */
	(void) _cfm;

	/* Ensure the watchdog is disabled. */
	MCF_SCM_CWCR = 0;

	/* Initialize IPSBAR (0x40000000). */
	asm volatile(
			"move.l  #0x40000000,%d0	\n"
			"andi.l  #0xC0000000,%d0	\n"
			"add.l   #0x1,%d0			\n"
			"move.l  %d0,0x40000000		"
	);

	/* Initialize FLASHBAR (0x00) */
	asm volatile(
			"move.l  #0x00,%d0			\n"
			"andi.l  #0xFFF80000,%d0	\n"
			"add.l   #0x41,%d0			\n"
			"movec   %d0,%FLASHBAR		"
	);

	portDISABLE_INTERRUPTS();

	/* RAMBAR. */
	MCF_SCM_RAMBAR = MCF_SCM_RAMBAR_BA( RAMBAR_ADDRESS ) | MCF_SCM_RAMBAR_BDE;

	/* Multiply 25MHz crystal by 12 to get 60MHz clock. */
	MCF_CLOCK_SYNCR = MCF_CLOCK_SYNCR_MFD(4) | MCF_CLOCK_SYNCR_CLKSRC
			| MCF_CLOCK_SYNCR_PLLMODE | MCF_CLOCK_SYNCR_PLLEN;
	while (!(MCF_CLOCK_SYNSR & MCF_CLOCK_SYNSR_LOCK)) {
	}

	/* Setup the port used to toggle LEDs. */
	vParTestInitialise();
}

/*-----------------------------------------------------------*/

void vApplicationIdleHook() {
	portTickType xTimeAkt, delta;

	xTimeAkt = xTaskGetTickCount();
	if (xTimePrev == 0)
		xTimePrev = xTimeAkt;
	if (xTimeStart == 0)
		xTimeStart = xTimeAkt;
	delta = xTimeAkt - xTimePrev;

	if (delta > 1) {
		//delta=xTimePrev-xTimeStartIdle;
		//IdleTime+=delta;
		xTimePrev = 0;
	} else {
		if (delta == 1) {
			xTimePrev = xTimeAkt;
			IdleTime++;
		}
	}
	if ((xTimeAkt - xTimeStart) > 5000) {
		vykon = 100 - ((float) IdleTime / (float) 50);
		if (maxVykon < vykon)
			maxVykon = vykon;
		IdleTime = 0;
		xTimeStart = 0;
	}

}

void vApplicationStackOverflowHook(xTaskHandle *pxTask,
		signed portCHAR *pcTaskName) {
	char buffer[400];
	/* This will get called if a stack overflow is detected during the context
	 switch.  Set configCHECK_FOR_STACK_OVERFLOWS to 2 to also check for stack
	 problems within nested interrupts, but only do this for debug purposes as
	 it will increase the context switch time. */

	(void) pxTask;
	(void) pcTaskName;
	/* Vypisanie erroru o preteceni stacku*/
	vTaskEndScheduler();
	critical_ERROR_WRITE_uart1("\n\r ERROR: Application Stack Over flow:\n\r");

	pcTaskName[configMAX_TASK_NAME_LEN] = '\0';
	critical_ERROR_WRITE_uart1(pcTaskName);

	vTaskList(buffer);
	critical_ERROR_WRITE_uart1(buffer);

	for (;;)
		asm("nop");
	;
}
/*-----------------------------------------------------------*/

static void vRegTest1Task(void *pvParameters) {
	/* Sanity check - did we receive the parameter expected? */
	if (pvParameters != &ulRegTest1Counter) {
		/* Change here so the check task can detect that an error occurred. */
		for (;;)
			;
	}

	/* Set all the registers to known values, then check that each retains its
	 expected value - as described at the top of this file.  If an error is
	 found then the loop counter will no longer be incremented allowing the check
	 task to recognise the error. */
	asm volatile ( "reg_test_1_start:						\n\t"
			"	moveq		#1, %d0					\n\t"
			"	moveq		#2, %d1					\n\t"
			"	moveq		#3, %d2					\n\t"
			"	moveq		#4, %d3					\n\t"
			"	moveq		#5, %d4					\n\t"
			"	moveq		#6, %d5					\n\t"
			"	moveq		#7, %d6					\n\t"
			"	moveq		#8, %d7					\n\t"
			"	move		#9, %a0					\n\t"
			"	move		#10, %a1				\n\t"
			"	move		#11, %a2				\n\t"
			"	move		#12, %a3				\n\t"
			"	move		#13, %a4				\n\t"
			"	move		#14, %a5				\n\t"
			"	move		#15, %a6				\n\t"
			"										\n\t"
			"	cmpi.l		#1, %d0					\n\t"
			"	bne			reg_test_1_error		\n\t"
			"	cmpi.l		#2, %d1					\n\t"
			"	bne			reg_test_1_error		\n\t"
			"	cmpi.l		#3, %d2					\n\t"
			"	bne			reg_test_1_error		\n\t"
			"	cmpi.l		#4, %d3					\n\t"
			"	bne			reg_test_1_error		\n\t"
			"	cmpi.l		#5, %d4					\n\t"
			"	bne			reg_test_1_error		\n\t"
			"	cmpi.l		#6, %d5					\n\t"
			"	bne			reg_test_1_error		\n\t"
			"	cmpi.l		#7, %d6					\n\t"
			"	bne			reg_test_1_error		\n\t"
			"	cmpi.l		#8, %d7					\n\t"
			"	bne			reg_test_1_error		\n\t"
			"	move		%a0, %d0				\n\t"
			"	cmpi.l		#9, %d0					\n\t"
			"	bne			reg_test_1_error		\n\t"
			"	move		%a1, %d0				\n\t"
			"	cmpi.l		#10, %d0				\n\t"
			"	bne			reg_test_1_error		\n\t"
			"	move		%a2, %d0				\n\t"
			"	cmpi.l		#11, %d0				\n\t"
			"	bne			reg_test_1_error		\n\t"
			"	move		%a3, %d0				\n\t"
			"	cmpi.l		#12, %d0				\n\t"
			"	bne			reg_test_1_error		\n\t"
			"	move		%a4, %d0				\n\t"
			"	cmpi.l		#13, %d0				\n\t"
			"	bne			reg_test_1_error		\n\t"
			"	move		%a5, %d0				\n\t"
			"	cmpi.l		#14, %d0				\n\t"
			"	bne			reg_test_1_error		\n\t"
			"	move		%a6, %d0				\n\t"
			"	cmpi.l		#15, %d0				\n\t"
			"	bne			reg_test_1_error		\n\t"
			"	movel		ulRegTest1Counter, %d0	\n\t"
			"	addql		#1, %d0					\n\t"
			"	movel		%d0, ulRegTest1Counter	\n\t"
			"	bra			reg_test_1_start		\n\t"
			"reg_test_1_error:						\n\t"
			"	bra			reg_test_1_error		\n\t"
	);
}
/*-----------------------------------------------------------*/

static void vRegTest2Task(void *pvParameters) {
	/* Sanity check - did we receive the parameter expected? */
	if (pvParameters != &ulRegTest2Counter) {
		/* Change here so the check task can detect that an error occurred. */
		for (;;)
			;
	}

	/* Set all the registers to known values, then check that each retains its
	 expected value - as described at the top of this file.  If an error is
	 found then the loop counter will no longer be incremented allowing the check
	 task to recognise the error. */
	asm volatile ( "reg_test_2_start:						\n\t"
			"	moveq		#10, %d0				\n\t"
			"	moveq		#20, %d1				\n\t"
			"	moveq		#30, %d2				\n\t"
			"	moveq		#40, %d3				\n\t"
			"	moveq		#50, %d4				\n\t"
			"	moveq		#60, %d5				\n\t"
			"	moveq		#70, %d6				\n\t"
			"	moveq		#80, %d7				\n\t"
			"	move		#90, %a0				\n\t"
			"	move		#100, %a1				\n\t"
			"	move		#110, %a2				\n\t"
			"	move		#120, %a3				\n\t"
			"	move		#130, %a4				\n\t"
			"	move		#140, %a5				\n\t"
			"	move		#150, %a6				\n\t"
			"										\n\t"
			"	cmpi.l		#10, %d0				\n\t"
			"	bne			reg_test_2_error		\n\t"
			"	cmpi.l		#20, %d1				\n\t"
			"	bne			reg_test_2_error		\n\t"
			"	cmpi.l		#30, %d2				\n\t"
			"	bne			reg_test_2_error		\n\t"
			"	cmpi.l		#40, %d3				\n\t"
			"	bne			reg_test_2_error		\n\t"
			"	cmpi.l		#50, %d4				\n\t"
			"	bne			reg_test_2_error		\n\t"
			"	cmpi.l		#60, %d5				\n\t"
			"	bne			reg_test_2_error		\n\t"
			"	cmpi.l		#70, %d6				\n\t"
			"	bne			reg_test_2_error		\n\t"
			"	cmpi.l		#80, %d7				\n\t"
			"	bne			reg_test_2_error		\n\t"
			"	move		%a0, %d0				\n\t"
			"	cmpi.l		#90, %d0				\n\t"
			"	bne			reg_test_2_error		\n\t"
			"	move		%a1, %d0				\n\t"
			"	cmpi.l		#100, %d0				\n\t"
			"	bne			reg_test_2_error		\n\t"
			"	move		%a2, %d0				\n\t"
			"	cmpi.l		#110, %d0				\n\t"
			"	bne			reg_test_2_error		\n\t"
			"	move		%a3, %d0				\n\t"
			"	cmpi.l		#120, %d0				\n\t"
			"	bne			reg_test_2_error		\n\t"
			"	move		%a4, %d0				\n\t"
			"	cmpi.l		#130, %d0				\n\t"
			"	bne			reg_test_2_error		\n\t"
			"	move		%a5, %d0				\n\t"
			"	cmpi.l		#140, %d0				\n\t"
			"	bne			reg_test_2_error		\n\t"
			"	move		%a6, %d0				\n\t"
			"	cmpi.l		#150, %d0				\n\t"
			"	bne			reg_test_2_error		\n\t"
			"	movel		ulRegTest1Counter, %d0	\n\t"
			"	addql		#1, %d0					\n\t"
			"	movel		%d0, ulRegTest2Counter	\n\t"
			"	bra			reg_test_2_start		\n\t"
			"reg_test_2_error:						\n\t"
			"	bra			reg_test_2_error		\n\t"
	);
}
/*-----------------------------------------------------------*/
/********************************************************************************************
 * Function: init_pin_assignments
 * Arguments: void
 * Return:  void
 * Comment: Pin Assignment and General Purpose I/O
 *******************************************************************************************/
static void init_pin_assignments(void) {
	/* Pin assignments for port UA
	 Pin UA3 : GPIO input
	 Pin UA2 : GPIO input
	 Pin UA1 : UART 0 receive data, URXD0
	 Pin UA0 : UART 0 transmit data, UTXD0
	 */
	MCF_GPIO_DDRUA = 0;
	MCF_GPIO_PUAPAR = MCF_GPIO_PUAPAR_PUAPAR1(0x1)
			| MCF_GPIO_PUAPAR_PUAPAR0(0x1);

	/* Pin assignments for port UB
	 Pin UB3 : GPIO input
	 Pin UB2 : GPIO input
	 Pin UB1 : UART 1 receive data, URXD1
	 Pin UB0 : UART 1 transmit data, UTXD1
	 */
	MCF_GPIO_DDRUB = 0;
	MCF_GPIO_PUBPAR = MCF_GPIO_PUBPAR_PUBPAR1(0x1)
			| MCF_GPIO_PUBPAR_PUBPAR0(0x1);

	/* Pin assignments for port AS
	 Pin AS3 : GPIO input
	 Pin AS2 : GPIO input
	 Pin AS1 : UART 2 receive data, URXD2
	 Pin AS0 : UART 2 transmit data, UTXD2
	 */
	MCF_GPIO_DDRAS = 0;
	MCF_GPIO_PASPAR = MCF_GPIO_PASPAR_PASPAR1(0x3)
			| MCF_GPIO_PASPAR_PASPAR0(0x3);

	/* Pin assignments for port TC
	 Pin TC3 : GPIO input
	 Pin TC2 : GPIO input
	 Pin TC1 : GPIO output, initially logic '0'
	 Pin TC0 : GPIO output, initially logic '0'
	 */
	MCF_GPIO_PORTTC = 0;
	MCF_GPIO_DDRTC = MCF_GPIO_DDRTC_DDRTC1 | MCF_GPIO_DDRTC_DDRTC0;
	MCF_GPIO_PTCPAR = 0;

	/* Pin assignments for port TA
	 Pin TA3 : GPIO input
	 Pin TA2 : GPIO input
	 Pin TA1 : GPIO input
	 Pin TA0 : GPIO output, initially logic '0' LEDKA
	 */
	MCF_GPIO_PORTTA = 0;
	MCF_GPIO_DDRTA = MCF_GPIO_DDRTA_DDRTA0;
	MCF_GPIO_PTAPAR = 0;

	/* Configure Wired-OR register */
	//  MCF_GPIO_PWOR = 0;

	/* Pin assignments for port AN
	 Pin AN7 : GPIO output, initially logic '0'
	 Pin AN6 : GPIO output, initially logic '0'
	 Pin AN5 : GPIO output, initially logic '0'
	 Pin AN4 : GPIO output, initially logic '1'
	 Pin AN3 : GPIO output, initially logic '0'
	 Pin AN2 : GPIO output, initially logic '0'
	 Pin AN1 : GPIO output, initially logic '0'
	 Pin AN0 : GPIO output, initially logic '0'
	 */
	MCF_GPIO_PORTAN = MCF_GPIO_PORTAN_PORTAN4;
	MCF_GPIO_DDRAN = MCF_GPIO_DDRAN_DDRAN7 | MCF_GPIO_DDRAN_DDRAN6
			| MCF_GPIO_DDRAN_DDRAN5 | MCF_GPIO_DDRAN_DDRAN4
			| MCF_GPIO_DDRAN_DDRAN3 | MCF_GPIO_DDRAN_DDRAN2
			| MCF_GPIO_DDRAN_DDRAN1 | MCF_GPIO_DDRAN_DDRAN0;
	MCF_GPIO_PANPAR = 0;

}

/*--END OF FUNCTION: init_pin_assignments---------------------------------------------------*/

