/** ###################################################################
**     THIS COMPONENT MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT.
**     Filename  : MCF52233.h
**
**     Copyright : 1997 - 2010 Freescale Semiconductor, Inc. All Rights Reserved.
**
**     http      : www.freescale.com
**     mail      : support@freescale.com
** ###################################################################*/

#ifndef __MCF52233_PE_H
#define __MCF52233_PE_H

#ifndef PE_MCUINIT
  #include "PE_Types.h"
#else
  typedef unsigned char           uint8;   /*  8 bits */
  typedef unsigned short int      uint16;  /* 16 bits */
  typedef unsigned long int       uint32;  /* 32 bits */

  typedef signed char             int8;    /*  8 bits */
  typedef signed short int        int16;   /* 16 bits */
  typedef signed long int         int32;   /* 32 bits */

  typedef volatile uint8          vuint8;  /*  8 bits */
  typedef volatile uint16         vuint16; /* 16 bits */
  typedef volatile uint32         vuint32; /* 32 bits */
#endif


/***
 * MCF52233 Derivative Memory map definitions from linker command files:
 * __IPSBAR, __RAMBAR, __RAMBAR_SIZE, __FLASHBAR, __FLASHBAR_SIZE linker
 * symbols must be defined in the linker command file.
 */
/*
extern __declspec(system)  uint8 __IPSBAR[];
extern __declspec(system)  uint8 __RAMBAR[];
extern __declspec(system)  uint8 __RAMBAR_SIZE[];
extern __declspec(system)  uint8 __FLASHBAR[];
extern __declspec(system)  uint8 __FLASHBAR_SIZE[];
*/

#define IPSBAR_ADDRESS   (uint32)__IPSBAR
#define RAMBAR_ADDRESS   (uint32)__RAMBAR
#define RAMBAR_SIZE      (uint32)__RAMBAR_SIZE
#define FLASHBAR_ADDRESS (uint32)__FLASHBAR
#define FLASHBAR_SIZE    (uint32)__FLASHBAR_SIZE


/******************************************
*** Peripheral PowerManagement
*******************************************/

/*** LPICR - Low-Power Interrupt Control Register.; 0x00000012 ***/
#define LPICR                         (*((volatile uint8 *)(&__IPSBAR[0x00000012UL])))
#define LPICR_XLPM_IPL0_BITMASK       (0x10U)
#define LPICR_XLPM_IPL1_BITMASK       (0x20U)
#define LPICR_XLPM_IPL2_BITMASK       (0x40U)
#define LPICR_ENBSTOP_BITMASK         (0x80U)
#define LPICR_XLPM_IPL_GRPMASK        (0x70U)
#define LPICR_XLPM_IPL_GRPPOS         (0x4U)

/*** PowerManagement_LPCR - Low-Power Control Register.; 0x00110007 ***/
#define PowerManagement_LPCR          (*((volatile uint8 *)(&__IPSBAR[0x00110007UL])))
#define PowerManagement_LPCR_LVDSE_BITMASK (0x2U)
#define PowerManagement_LPCR_STPMD0_BITMASK (0x8U)
#define PowerManagement_LPCR_STPMD1_BITMASK (0x10U)
#define PowerManagement_LPCR_LPMD0_BITMASK (0x40U)
#define PowerManagement_LPCR_LPMD1_BITMASK (0x80U)
#define PowerManagement_LPCR_STPMD_GRPMASK (0x18U)
#define PowerManagement_LPCR_STPMD_GRPPOS (0x3U)
#define PowerManagement_LPCR_LPMD_GRPMASK (0xC0U)
#define PowerManagement_LPCR_LPMD_GRPPOS (0x6U)


/******************************************
*** Peripheral SCM
*******************************************/

/*** SCM_RAMBAR - Memory Base Address Register.; 0x00000008 ***/
#define SCM_RAMBAR                    (*((volatile uint32 *)(&__IPSBAR[0x00000008UL])))
#define SCM_RAMBAR_BDE_BITMASK        (0x200U)
#define SCM_RAMBAR_BA16_BITMASK       (0x10000U)
#define SCM_RAMBAR_BA17_BITMASK       (0x20000U)
#define SCM_RAMBAR_BA18_BITMASK       (0x40000U)
#define SCM_RAMBAR_BA19_BITMASK       (0x80000U)
#define SCM_RAMBAR_BA20_BITMASK       (0x100000U)
#define SCM_RAMBAR_BA21_BITMASK       (0x200000U)
#define SCM_RAMBAR_BA22_BITMASK       (0x400000U)
#define SCM_RAMBAR_BA23_BITMASK       (0x800000U)
#define SCM_RAMBAR_BA24_BITMASK       (0x1000000U)
#define SCM_RAMBAR_BA25_BITMASK       (0x2000000U)
#define SCM_RAMBAR_BA26_BITMASK       (0x4000000U)
#define SCM_RAMBAR_BA27_BITMASK       (0x8000000U)
#define SCM_RAMBAR_BA28_BITMASK       (0x10000000U)
#define SCM_RAMBAR_BA29_BITMASK       (0x20000000U)
#define SCM_RAMBAR_BA30_BITMASK       (0x40000000U)
#define SCM_RAMBAR_BA31_BITMASK       (0x80000000U)
#define SCM_RAMBAR_BA_GRPMASK         (0xFFFF0000U)
#define SCM_RAMBAR_BA_GRPPOS          (0x10U)

/*** PPMRH - Peripheral Power Management Register High.; 0x0000000C ***/
#define PPMRH                         (*((volatile uint32 *)(&__IPSBAR[0x0000000CUL])))
#define PPMRH_CDPORTS_BITMASK         (0x1U)
#define PPMRH_CDEPORT_BITMASK         (0x2U)
#define PPMRH_CDPIT0_BITMASK          (0x8U)
#define PPMRH_CDPIT1_BITMASK          (0x10U)
#define PPMRH_CDADC_BITMASK           (0x80U)
#define PPMRH_CDGPT_BITMASK           (0x100U)
#define PPMRH_CDPWM_BITMASK           (0x200U)
#define PPMRH_CDFCAN_BITMASK          (0x400U)
#define PPMRH_CDCFM_BITMASK           (0x800U)
#define PPMRH_CDEPHY_BITMASK          (0x1000U)
#define PPMRH_CDRNGA_BITMASK          (0x2000U)

/*** CRSR - Core Reset Status Register.; 0x00000010 ***/
#define CRSR                          (*((volatile uint8 *)(&__IPSBAR[0x00000010UL])))
#define CRSR_EXT_BITMASK              (0x80U)

/*** CWCR - Core Watchdog Control Register.; 0x00000011 ***/
#define CWCR                          (*((volatile uint8 *)(&__IPSBAR[0x00000011UL])))
#define CWCR_CWTIF_BITMASK            (0x1U)
#define CWCR_CWTAVAL_BITMASK          (0x2U)
#define CWCR_CWTA_BITMASK             (0x4U)
#define CWCR_CWT0_BITMASK             (0x8U)
#define CWCR_CWT1_BITMASK             (0x10U)
#define CWCR_CWT2_BITMASK             (0x20U)
#define CWCR_CWRI_BITMASK             (0x40U)
#define CWCR_CWE_BITMASK              (0x80U)
#define CWCR_CWT_GRPMASK              (0x38U)
#define CWCR_CWT_GRPPOS               (0x3U)

/*** CWSR - Core Watchdog Service Register.; 0x00000013 ***/
#define CWSR                          (*((volatile uint8 *)(&__IPSBAR[0x00000013UL])))
#define CWSR_CWSR0_BITMASK            (0x1U)
#define CWSR_CWSR1_BITMASK            (0x2U)
#define CWSR_CWSR2_BITMASK            (0x4U)
#define CWSR_CWSR3_BITMASK            (0x8U)
#define CWSR_CWSR4_BITMASK            (0x10U)
#define CWSR_CWSR5_BITMASK            (0x20U)
#define CWSR_CWSR6_BITMASK            (0x40U)
#define CWSR_CWSR7_BITMASK            (0x80U)
#define CWSR_CWSR_GRPMASK             (0xFFU)
#define CWSR_CWSR_GRPPOS              (0U)

/*** DMAREQC - DMA Request Control Register.; 0x00000014 ***/
#define DMAREQC                       (*((volatile uint32 *)(&__IPSBAR[0x00000014UL])))
#define DMAREQC_DMAC00_BITMASK        (0x1U)
#define DMAREQC_DMAC01_BITMASK        (0x2U)
#define DMAREQC_DMAC02_BITMASK        (0x4U)
#define DMAREQC_DMAC03_BITMASK        (0x8U)
#define DMAREQC_DMAC10_BITMASK        (0x10U)
#define DMAREQC_DMAC11_BITMASK        (0x20U)
#define DMAREQC_DMAC12_BITMASK        (0x40U)
#define DMAREQC_DMAC13_BITMASK        (0x80U)
#define DMAREQC_DMAC20_BITMASK        (0x100U)
#define DMAREQC_DMAC21_BITMASK        (0x200U)
#define DMAREQC_DMAC22_BITMASK        (0x400U)
#define DMAREQC_DMAC23_BITMASK        (0x800U)
#define DMAREQC_DMAC30_BITMASK        (0x1000U)
#define DMAREQC_DMAC31_BITMASK        (0x2000U)
#define DMAREQC_DMAC32_BITMASK        (0x4000U)
#define DMAREQC_DMAC33_BITMASK        (0x8000U)
#define DMAREQC_DMAC0_GRPMASK         (0xFU)
#define DMAREQC_DMAC0_GRPPOS          (0U)
#define DMAREQC_DMAC1_GRPMASK         (0xF0U)
#define DMAREQC_DMAC1_GRPPOS          (0x4U)
#define DMAREQC_DMAC2_GRPMASK         (0xF00U)
#define DMAREQC_DMAC2_GRPPOS          (0x8U)
#define DMAREQC_DMAC3_GRPMASK         (0xF000U)
#define DMAREQC_DMAC3_GRPPOS          (0xCU)

/*** PPMRL - Peripheral Power Management Register Low.; 0x00000018 ***/
#define PPMRL                         (*((volatile uint32 *)(&__IPSBAR[0x00000018UL])))
#define PPMRL_CDG_BITMASK             (0x2U)
#define PPMRL_CDDMA_BITMASK           (0x10U)
#define PPMRL_CDUART0_BITMASK         (0x20U)
#define PPMRL_CDUART1_BITMASK         (0x40U)
#define PPMRL_CDUART2_BITMASK         (0x80U)
#define PPMRL_CDI2C_BITMASK           (0x200U)
#define PPMRL_CDQSPI_BITMASK          (0x400U)
#define PPMRL_CDRTC_BITMASK           (0x1000U)
#define PPMRL_CDTMR0_BITMASK          (0x2000U)
#define PPMRL_CDTMR1_BITMASK          (0x4000U)
#define PPMRL_CDTMR2_BITMASK          (0x8000U)
#define PPMRL_CDTMR3_BITMASK          (0x10000U)
#define PPMRL_CDINTC0_BITMASK         (0x20000U)
#define PPMRL_CDINTC1_BITMASK         (0x40000U)
#define PPMRL_CDFEC0_BITMASK          (0x200000U)

/*** MPARK - Bus Master Park Register.; 0x0000001C ***/
#define MPARK                         (*((volatile uint32 *)(&__IPSBAR[0x0000001CUL])))
#define MPARK_LCKOUT_TIME0_BITMASK    (0x100U)
#define MPARK_LCKOUT_TIME1_BITMASK    (0x200U)
#define MPARK_LCKOUT_TIME2_BITMASK    (0x400U)
#define MPARK_LCKOUT_TIME3_BITMASK    (0x800U)
#define MPARK_PRKLAST_BITMASK         (0x1000U)
#define MPARK_TIMEOUT_BITMASK         (0x2000U)
#define MPARK_FIXED_BITMASK           (0x4000U)
#define MPARK_M1_PRTY0_BITMASK        (0x10000U)
#define MPARK_M1_PRTY1_BITMASK        (0x20000U)
#define MPARK_M0_PRTY0_BITMASK        (0x40000U)
#define MPARK_M0_PRTY1_BITMASK        (0x80000U)
#define MPARK_M2_PRTY0_BITMASK        (0x100000U)
#define MPARK_M2_PRTY1_BITMASK        (0x200000U)
#define MPARK_BCR24BIT_BITMASK        (0x1000000U)
#define MPARK_M2_P_EN_BITMASK         (0x2000000U)
#define MPARK_LCKOUT_TIME_GRPMASK     (0xF00U)
#define MPARK_LCKOUT_TIME_GRPPOS      (0x8U)
#define MPARK_M1_PRTY_GRPMASK         (0x30000U)
#define MPARK_M1_PRTY_GRPPOS          (0x10U)
#define MPARK_M0_PRTY_GRPMASK         (0xC0000U)
#define MPARK_M0_PRTY_GRPPOS          (0x12U)
#define MPARK_M2_PRTY_GRPMASK         (0x300000U)
#define MPARK_M2_PRTY_GRPPOS          (0x14U)

/*** MPR - Master Privilege Register.; 0x00000020 ***/
#define MPR                           (*((volatile uint8 *)(&__IPSBAR[0x00000020UL])))
#define MPR_MPR0_BITMASK              (0x1U)
#define MPR_MPR1_BITMASK              (0x2U)
#define MPR_MPR2_BITMASK              (0x4U)
#define MPR_MPR3_BITMASK              (0x8U)
#define MPR_MPR_GRPMASK               (0xFU)
#define MPR_MPR_GRPPOS                (0U)

/*** PPMRS - Peripheral Power Management Set Register.; 0x00000021 ***/
#define PPMRS                         (*((volatile uint8 *)(&__IPSBAR[0x00000021UL])))
#define PPMRS_PPMRS0_BITMASK          (0x1U)
#define PPMRS_PPMRS1_BITMASK          (0x2U)
#define PPMRS_PPMRS2_BITMASK          (0x4U)
#define PPMRS_PPMRS3_BITMASK          (0x8U)
#define PPMRS_PPMRS4_BITMASK          (0x10U)
#define PPMRS_PPMRS5_BITMASK          (0x20U)
#define PPMRS_PPMRS6_BITMASK          (0x40U)
#define PPMRS_PPMRS_GRPMASK           (0x7FU)
#define PPMRS_PPMRS_GRPPOS            (0U)

/*** PPMRC - Peripheral Power Management Clear Register.; 0x00000022 ***/
#define PPMRC                         (*((volatile uint8 *)(&__IPSBAR[0x00000022UL])))
#define PPMRC_PPMRC0_BITMASK          (0x1U)
#define PPMRC_PPMRC1_BITMASK          (0x2U)
#define PPMRC_PPMRC2_BITMASK          (0x4U)
#define PPMRC_PPMRC3_BITMASK          (0x8U)
#define PPMRC_PPMRC4_BITMASK          (0x10U)
#define PPMRC_PPMRC5_BITMASK          (0x20U)
#define PPMRC_PPMRC6_BITMASK          (0x40U)
#define PPMRC_PPMRC_GRPMASK           (0x7FU)
#define PPMRC_PPMRC_GRPPOS            (0U)

/*** IPSBMT - IPS Bus Timeout Monitor Register.; 0x00000023 ***/
#define IPSBMT                        (*((volatile uint8 *)(&__IPSBAR[0x00000023UL])))
#define IPSBMT_BMT0_BITMASK           (0x1U)
#define IPSBMT_BMT1_BITMASK           (0x2U)
#define IPSBMT_BMT2_BITMASK           (0x4U)
#define IPSBMT_BME_BITMASK            (0x8U)
#define IPSBMT_BMT_GRPMASK            (0x7U)
#define IPSBMT_BMT_GRPPOS             (0U)

/*** PACR0 - Peripheral Access Control Register 0.; 0x00000024 ***/
#define PACR0                         (*((volatile uint8 *)(&__IPSBAR[0x00000024UL])))
#define PACR0_ACCESS_CTRL00_BITMASK   (0x1U)
#define PACR0_ACCESS_CTRL01_BITMASK   (0x2U)
#define PACR0_ACCESS_CTRL02_BITMASK   (0x4U)
#define PACR0_LOCK0_BITMASK           (0x8U)
#define PACR0_ACCESS_CTRL10_BITMASK   (0x10U)
#define PACR0_ACCESS_CTRL11_BITMASK   (0x20U)
#define PACR0_ACCESS_CTRL12_BITMASK   (0x40U)
#define PACR0_LOCK1_BITMASK           (0x80U)
#define PACR0_ACCESS_CTRL0_GRPMASK    (0x7U)
#define PACR0_ACCESS_CTRL0_GRPPOS     (0U)
#define PACR0_ACCESS_CTRL1_GRPMASK    (0x70U)
#define PACR0_ACCESS_CTRL1_GRPPOS     (0x4U)

/*** PACR1 - Peripheral Access Control Register 1.; 0x00000025 ***/
#define PACR1                         (*((volatile uint8 *)(&__IPSBAR[0x00000025UL])))
#define PACR1_ACCESS_CTRL00_BITMASK   (0x1U)
#define PACR1_ACCESS_CTRL01_BITMASK   (0x2U)
#define PACR1_ACCESS_CTRL02_BITMASK   (0x4U)
#define PACR1_LOCK0_BITMASK           (0x8U)
#define PACR1_ACCESS_CTRL10_BITMASK   (0x10U)
#define PACR1_ACCESS_CTRL11_BITMASK   (0x20U)
#define PACR1_ACCESS_CTRL12_BITMASK   (0x40U)
#define PACR1_LOCK1_BITMASK           (0x80U)
#define PACR1_ACCESS_CTRL0_GRPMASK    (0x7U)
#define PACR1_ACCESS_CTRL0_GRPPOS     (0U)
#define PACR1_ACCESS_CTRL1_GRPMASK    (0x70U)
#define PACR1_ACCESS_CTRL1_GRPPOS     (0x4U)

/*** PACR2 - Peripheral Access Control Register 2.; 0x00000026 ***/
#define PACR2                         (*((volatile uint8 *)(&__IPSBAR[0x00000026UL])))
#define PACR2_ACCESS_CTRL00_BITMASK   (0x1U)
#define PACR2_ACCESS_CTRL01_BITMASK   (0x2U)
#define PACR2_ACCESS_CTRL02_BITMASK   (0x4U)
#define PACR2_LOCK0_BITMASK           (0x8U)
#define PACR2_ACCESS_CTRL10_BITMASK   (0x10U)
#define PACR2_ACCESS_CTRL11_BITMASK   (0x20U)
#define PACR2_ACCESS_CTRL12_BITMASK   (0x40U)
#define PACR2_LOCK1_BITMASK           (0x80U)
#define PACR2_ACCESS_CTRL0_GRPMASK    (0x7U)
#define PACR2_ACCESS_CTRL0_GRPPOS     (0U)
#define PACR2_ACCESS_CTRL1_GRPMASK    (0x70U)
#define PACR2_ACCESS_CTRL1_GRPPOS     (0x4U)

/*** PACR3 - Peripheral Access Control Register 3.; 0x00000027 ***/
#define PACR3                         (*((volatile uint8 *)(&__IPSBAR[0x00000027UL])))
#define PACR3_ACCESS_CTRL00_BITMASK   (0x1U)
#define PACR3_ACCESS_CTRL01_BITMASK   (0x2U)
#define PACR3_ACCESS_CTRL02_BITMASK   (0x4U)
#define PACR3_LOCK0_BITMASK           (0x8U)
#define PACR3_ACCESS_CTRL10_BITMASK   (0x10U)
#define PACR3_ACCESS_CTRL11_BITMASK   (0x20U)
#define PACR3_ACCESS_CTRL12_BITMASK   (0x40U)
#define PACR3_LOCK1_BITMASK           (0x80U)
#define PACR3_ACCESS_CTRL0_GRPMASK    (0x7U)
#define PACR3_ACCESS_CTRL0_GRPPOS     (0U)
#define PACR3_ACCESS_CTRL1_GRPMASK    (0x70U)
#define PACR3_ACCESS_CTRL1_GRPPOS     (0x4U)

/*** PACR4 - Peripheral Access Control Register 4.; 0x00000028 ***/
#define PACR4                         (*((volatile uint8 *)(&__IPSBAR[0x00000028UL])))
#define PACR4_ACCESS_CTRL00_BITMASK   (0x1U)
#define PACR4_ACCESS_CTRL01_BITMASK   (0x2U)
#define PACR4_ACCESS_CTRL02_BITMASK   (0x4U)
#define PACR4_LOCK0_BITMASK           (0x8U)
#define PACR4_ACCESS_CTRL10_BITMASK   (0x10U)
#define PACR4_ACCESS_CTRL11_BITMASK   (0x20U)
#define PACR4_ACCESS_CTRL12_BITMASK   (0x40U)
#define PACR4_LOCK1_BITMASK           (0x80U)
#define PACR4_ACCESS_CTRL0_GRPMASK    (0x7U)
#define PACR4_ACCESS_CTRL0_GRPPOS     (0U)
#define PACR4_ACCESS_CTRL1_GRPMASK    (0x70U)
#define PACR4_ACCESS_CTRL1_GRPPOS     (0x4U)

/*** PACR5 - Peripheral Access Control Register 5.; 0x00000029 ***/
#define PACR5                         (*((volatile uint8 *)(&__IPSBAR[0x00000029UL])))
#define PACR5_ACCESS_CTRL00_BITMASK   (0x1U)
#define PACR5_ACCESS_CTRL01_BITMASK   (0x2U)
#define PACR5_ACCESS_CTRL02_BITMASK   (0x4U)
#define PACR5_LOCK0_BITMASK           (0x8U)
#define PACR5_ACCESS_CTRL10_BITMASK   (0x10U)
#define PACR5_ACCESS_CTRL11_BITMASK   (0x20U)
#define PACR5_ACCESS_CTRL12_BITMASK   (0x40U)
#define PACR5_LOCK1_BITMASK           (0x80U)
#define PACR5_ACCESS_CTRL0_GRPMASK    (0x7U)
#define PACR5_ACCESS_CTRL0_GRPPOS     (0U)
#define PACR5_ACCESS_CTRL1_GRPMASK    (0x70U)
#define PACR5_ACCESS_CTRL1_GRPPOS     (0x4U)

/*** PACR6 - Peripheral Access Control Register 6.; 0x0000002A ***/
#define PACR6                         (*((volatile uint8 *)(&__IPSBAR[0x0000002AUL])))
#define PACR6_ACCESS_CTRL00_BITMASK   (0x1U)
#define PACR6_ACCESS_CTRL01_BITMASK   (0x2U)
#define PACR6_ACCESS_CTRL02_BITMASK   (0x4U)
#define PACR6_LOCK0_BITMASK           (0x8U)
#define PACR6_ACCESS_CTRL10_BITMASK   (0x10U)
#define PACR6_ACCESS_CTRL11_BITMASK   (0x20U)
#define PACR6_ACCESS_CTRL12_BITMASK   (0x40U)
#define PACR6_LOCK1_BITMASK           (0x80U)
#define PACR6_ACCESS_CTRL0_GRPMASK    (0x7U)
#define PACR6_ACCESS_CTRL0_GRPPOS     (0U)
#define PACR6_ACCESS_CTRL1_GRPMASK    (0x70U)
#define PACR6_ACCESS_CTRL1_GRPPOS     (0x4U)

/*** PACR7 - Peripheral Access Control Register 7.; 0x0000002B ***/
#define PACR7                         (*((volatile uint8 *)(&__IPSBAR[0x0000002BUL])))
#define PACR7_ACCESS_CTRL00_BITMASK   (0x1U)
#define PACR7_ACCESS_CTRL01_BITMASK   (0x2U)
#define PACR7_ACCESS_CTRL02_BITMASK   (0x4U)
#define PACR7_LOCK0_BITMASK           (0x8U)
#define PACR7_ACCESS_CTRL10_BITMASK   (0x10U)
#define PACR7_ACCESS_CTRL11_BITMASK   (0x20U)
#define PACR7_ACCESS_CTRL12_BITMASK   (0x40U)
#define PACR7_LOCK1_BITMASK           (0x80U)
#define PACR7_ACCESS_CTRL0_GRPMASK    (0x7U)
#define PACR7_ACCESS_CTRL0_GRPPOS     (0U)
#define PACR7_ACCESS_CTRL1_GRPMASK    (0x70U)
#define PACR7_ACCESS_CTRL1_GRPPOS     (0x4U)

/*** PACR8 - Peripheral Access Control Register 8.; 0x0000002C ***/
#define PACR8                         (*((volatile uint8 *)(&__IPSBAR[0x0000002CUL])))
#define PACR8_ACCESS_CTRL00_BITMASK   (0x1U)
#define PACR8_ACCESS_CTRL01_BITMASK   (0x2U)
#define PACR8_ACCESS_CTRL02_BITMASK   (0x4U)
#define PACR8_LOCK0_BITMASK           (0x8U)
#define PACR8_ACCESS_CTRL10_BITMASK   (0x10U)
#define PACR8_ACCESS_CTRL11_BITMASK   (0x20U)
#define PACR8_ACCESS_CTRL12_BITMASK   (0x40U)
#define PACR8_LOCK1_BITMASK           (0x80U)
#define PACR8_ACCESS_CTRL0_GRPMASK    (0x7U)
#define PACR8_ACCESS_CTRL0_GRPPOS     (0U)
#define PACR8_ACCESS_CTRL1_GRPMASK    (0x70U)
#define PACR8_ACCESS_CTRL1_GRPPOS     (0x4U)

/*** GPACR0 - Grouped Peripheral Access Control Register 0.; 0x00000030 ***/
#define GPACR0                        (*((volatile uint8 *)(&__IPSBAR[0x00000030UL])))
#define GPACR0_ACCESS_CTRL0_BITMASK   (0x1U)
#define GPACR0_ACCESS_CTRL1_BITMASK   (0x2U)
#define GPACR0_ACCESS_CTRL2_BITMASK   (0x4U)
#define GPACR0_ACCESS_CTRL3_BITMASK   (0x8U)
#define GPACR0_LOCK_BITMASK           (0x80U)
#define GPACR0_ACCESS_CTRL_GRPMASK    (0xFU)
#define GPACR0_ACCESS_CTRL_GRPPOS     (0U)

/*** GPACR1 - Grouped Peripheral Access Control Register 1.; 0x00000031 ***/
#define GPACR1                        (*((volatile uint8 *)(&__IPSBAR[0x00000031UL])))
#define GPACR1_ACCESS_CTRL0_BITMASK   (0x1U)
#define GPACR1_ACCESS_CTRL1_BITMASK   (0x2U)
#define GPACR1_ACCESS_CTRL2_BITMASK   (0x4U)
#define GPACR1_ACCESS_CTRL3_BITMASK   (0x8U)
#define GPACR1_LOCK_BITMASK           (0x80U)
#define GPACR1_ACCESS_CTRL_GRPMASK    (0xFU)
#define GPACR1_ACCESS_CTRL_GRPPOS     (0U)


/******************************************
*** Peripheral DMA0
*******************************************/

/*** SAR0 - Source Address Register 0.; 0x00000100 ***/
#define SAR0                          (*((volatile uint32 *)(&__IPSBAR[0x00000100UL])))
#define SAR0_SAR0_BITMASK             (0x1U)
#define SAR0_SAR1_BITMASK             (0x2U)
#define SAR0_SAR2_BITMASK             (0x4U)
#define SAR0_SAR3_BITMASK             (0x8U)
#define SAR0_SAR4_BITMASK             (0x10U)
#define SAR0_SAR5_BITMASK             (0x20U)
#define SAR0_SAR6_BITMASK             (0x40U)
#define SAR0_SAR7_BITMASK             (0x80U)
#define SAR0_SAR8_BITMASK             (0x100U)
#define SAR0_SAR9_BITMASK             (0x200U)
#define SAR0_SAR10_BITMASK            (0x400U)
#define SAR0_SAR11_BITMASK            (0x800U)
#define SAR0_SAR12_BITMASK            (0x1000U)
#define SAR0_SAR13_BITMASK            (0x2000U)
#define SAR0_SAR14_BITMASK            (0x4000U)
#define SAR0_SAR15_BITMASK            (0x8000U)
#define SAR0_SAR16_BITMASK            (0x10000U)
#define SAR0_SAR17_BITMASK            (0x20000U)
#define SAR0_SAR18_BITMASK            (0x40000U)
#define SAR0_SAR19_BITMASK            (0x80000U)
#define SAR0_SAR20_BITMASK            (0x100000U)
#define SAR0_SAR21_BITMASK            (0x200000U)
#define SAR0_SAR22_BITMASK            (0x400000U)
#define SAR0_SAR23_BITMASK            (0x800000U)
#define SAR0_SAR24_BITMASK            (0x1000000U)
#define SAR0_SAR25_BITMASK            (0x2000000U)
#define SAR0_SAR26_BITMASK            (0x4000000U)
#define SAR0_SAR27_BITMASK            (0x8000000U)
#define SAR0_SAR28_BITMASK            (0x10000000U)
#define SAR0_SAR29_BITMASK            (0x20000000U)
#define SAR0_SAR30_BITMASK            (0x40000000U)
#define SAR0_SAR31_BITMASK            (0x80000000U)
#define SAR0_SAR_GRPMASK              (0xFFFFFFFFU)
#define SAR0_SAR_GRPPOS               (0U)

/*** DAR0 - Destination Address Register 0.; 0x00000104 ***/
#define DAR0                          (*((volatile uint32 *)(&__IPSBAR[0x00000104UL])))
#define DAR0_DAR0_BITMASK             (0x1U)
#define DAR0_DAR1_BITMASK             (0x2U)
#define DAR0_DAR2_BITMASK             (0x4U)
#define DAR0_DAR3_BITMASK             (0x8U)
#define DAR0_DAR4_BITMASK             (0x10U)
#define DAR0_DAR5_BITMASK             (0x20U)
#define DAR0_DAR6_BITMASK             (0x40U)
#define DAR0_DAR7_BITMASK             (0x80U)
#define DAR0_DAR8_BITMASK             (0x100U)
#define DAR0_DAR9_BITMASK             (0x200U)
#define DAR0_DAR10_BITMASK            (0x400U)
#define DAR0_DAR11_BITMASK            (0x800U)
#define DAR0_DAR12_BITMASK            (0x1000U)
#define DAR0_DAR13_BITMASK            (0x2000U)
#define DAR0_DAR14_BITMASK            (0x4000U)
#define DAR0_DAR15_BITMASK            (0x8000U)
#define DAR0_DAR16_BITMASK            (0x10000U)
#define DAR0_DAR17_BITMASK            (0x20000U)
#define DAR0_DAR18_BITMASK            (0x40000U)
#define DAR0_DAR19_BITMASK            (0x80000U)
#define DAR0_DAR20_BITMASK            (0x100000U)
#define DAR0_DAR21_BITMASK            (0x200000U)
#define DAR0_DAR22_BITMASK            (0x400000U)
#define DAR0_DAR23_BITMASK            (0x800000U)
#define DAR0_DAR24_BITMASK            (0x1000000U)
#define DAR0_DAR25_BITMASK            (0x2000000U)
#define DAR0_DAR26_BITMASK            (0x4000000U)
#define DAR0_DAR27_BITMASK            (0x8000000U)
#define DAR0_DAR28_BITMASK            (0x10000000U)
#define DAR0_DAR29_BITMASK            (0x20000000U)
#define DAR0_DAR30_BITMASK            (0x40000000U)
#define DAR0_DAR31_BITMASK            (0x80000000U)
#define DAR0_DAR_GRPMASK              (0xFFFFFFFFU)
#define DAR0_DAR_GRPPOS               (0U)

/*** DSR0 - DMA Status Register 0.; 0x00000108 ***/
#define DSR0                          (*((volatile uint8 *)(&__IPSBAR[0x00000108UL])))
#define DSR0_DONE_BITMASK             (0x1U)
#define DSR0_BSY_BITMASK              (0x2U)
#define DSR0_REQ_BITMASK              (0x4U)
#define DSR0_BED_BITMASK              (0x10U)
#define DSR0_BES_BITMASK              (0x20U)
#define DSR0_CE_BITMASK               (0x40U)

/*** BCR0 - Byte Count Register 0.; 0x00000108 ***/
#define BCR0                          (*((volatile uint32 *)(&__IPSBAR[0x00000108UL])))
#define BCR0_BCR0_BITMASK             (0x1U)
#define BCR0_BCR1_BITMASK             (0x2U)
#define BCR0_BCR2_BITMASK             (0x4U)
#define BCR0_BCR3_BITMASK             (0x8U)
#define BCR0_BCR4_BITMASK             (0x10U)
#define BCR0_BCR5_BITMASK             (0x20U)
#define BCR0_BCR6_BITMASK             (0x40U)
#define BCR0_BCR7_BITMASK             (0x80U)
#define BCR0_BCR8_BITMASK             (0x100U)
#define BCR0_BCR9_BITMASK             (0x200U)
#define BCR0_BCR10_BITMASK            (0x400U)
#define BCR0_BCR11_BITMASK            (0x800U)
#define BCR0_BCR12_BITMASK            (0x1000U)
#define BCR0_BCR13_BITMASK            (0x2000U)
#define BCR0_BCR14_BITMASK            (0x4000U)
#define BCR0_BCR15_BITMASK            (0x8000U)
#define BCR0_BCR16_BITMASK            (0x10000U)
#define BCR0_BCR17_BITMASK            (0x20000U)
#define BCR0_BCR18_BITMASK            (0x40000U)
#define BCR0_BCR19_BITMASK            (0x80000U)
#define BCR0_BCR20_BITMASK            (0x100000U)
#define BCR0_BCR21_BITMASK            (0x200000U)
#define BCR0_BCR22_BITMASK            (0x400000U)
#define BCR0_BCR23_BITMASK            (0x800000U)
#define BCR0_DSR0_BITMASK             (0x1000000U)
#define BCR0_DSR1_BITMASK             (0x2000000U)
#define BCR0_DSR2_BITMASK             (0x4000000U)
#define BCR0_DSR3_BITMASK             (0x8000000U)
#define BCR0_DSR4_BITMASK             (0x10000000U)
#define BCR0_DSR5_BITMASK             (0x20000000U)
#define BCR0_DSR6_BITMASK             (0x40000000U)
#define BCR0_DSR7_BITMASK             (0x80000000U)
#define BCR0_BCR_GRPMASK              (0xFFFFFFU)
#define BCR0_BCR_GRPPOS               (0U)
#define BCR0_DSR_GRPMASK              (0xFF000000U)
#define BCR0_DSR_GRPPOS               (0x18U)

/*** DCR0 - DMA Control Register 0.; 0x0000010C ***/
#define DCR0                          (*((volatile uint32 *)(&__IPSBAR[0x0000010CUL])))
#define DCR0_LCH20_BITMASK            (0x1U)
#define DCR0_LCH21_BITMASK            (0x2U)
#define DCR0_LCH10_BITMASK            (0x4U)
#define DCR0_LCH11_BITMASK            (0x8U)
#define DCR0_LINKCC0_BITMASK          (0x10U)
#define DCR0_LINKCC1_BITMASK          (0x20U)
#define DCR0_D_REQ_BITMASK            (0x80U)
#define DCR0_DMOD0_BITMASK            (0x100U)
#define DCR0_DMOD1_BITMASK            (0x200U)
#define DCR0_DMOD2_BITMASK            (0x400U)
#define DCR0_DMOD3_BITMASK            (0x800U)
#define DCR0_SMOD0_BITMASK            (0x1000U)
#define DCR0_SMOD1_BITMASK            (0x2000U)
#define DCR0_SMOD2_BITMASK            (0x4000U)
#define DCR0_SMOD3_BITMASK            (0x8000U)
#define DCR0_START_BITMASK            (0x10000U)
#define DCR0_DSIZE0_BITMASK           (0x20000U)
#define DCR0_DSIZE1_BITMASK           (0x40000U)
#define DCR0_DINC_BITMASK             (0x80000U)
#define DCR0_SSIZE0_BITMASK           (0x100000U)
#define DCR0_SSIZE1_BITMASK           (0x200000U)
#define DCR0_SINC_BITMASK             (0x400000U)
#define DCR0_BWC0_BITMASK             (0x2000000U)
#define DCR0_BWC1_BITMASK             (0x4000000U)
#define DCR0_BWC2_BITMASK             (0x8000000U)
#define DCR0_AA_BITMASK               (0x10000000U)
#define DCR0_CS_BITMASK               (0x20000000U)
#define DCR0_EEXT_BITMASK             (0x40000000U)
#define DCR0_INT_BITMASK              (0x80000000U)
#define DCR0_LCH2_GRPMASK             (0x3U)
#define DCR0_LCH2_GRPPOS              (0U)
#define DCR0_LCH1_GRPMASK             (0xCU)
#define DCR0_LCH1_GRPPOS              (0x2U)
#define DCR0_LINKCC_GRPMASK           (0x30U)
#define DCR0_LINKCC_GRPPOS            (0x4U)
#define DCR0_DMOD_GRPMASK             (0xF00U)
#define DCR0_DMOD_GRPPOS              (0x8U)
#define DCR0_SMOD_GRPMASK             (0xF000U)
#define DCR0_SMOD_GRPPOS              (0xCU)
#define DCR0_DSIZE_GRPMASK            (0x60000U)
#define DCR0_DSIZE_GRPPOS             (0x11U)
#define DCR0_SSIZE_GRPMASK            (0x300000U)
#define DCR0_SSIZE_GRPPOS             (0x14U)
#define DCR0_BWC_GRPMASK              (0xE000000U)
#define DCR0_BWC_GRPPOS               (0x19U)


/******************************************
*** Peripheral DMA1
*******************************************/

/*** SAR1 - Source Address Register 1.; 0x00000110 ***/
#define SAR1                          (*((volatile uint32 *)(&__IPSBAR[0x00000110UL])))
#define SAR1_SAR0_BITMASK             (0x1U)
#define SAR1_SAR1_BITMASK             (0x2U)
#define SAR1_SAR2_BITMASK             (0x4U)
#define SAR1_SAR3_BITMASK             (0x8U)
#define SAR1_SAR4_BITMASK             (0x10U)
#define SAR1_SAR5_BITMASK             (0x20U)
#define SAR1_SAR6_BITMASK             (0x40U)
#define SAR1_SAR7_BITMASK             (0x80U)
#define SAR1_SAR8_BITMASK             (0x100U)
#define SAR1_SAR9_BITMASK             (0x200U)
#define SAR1_SAR10_BITMASK            (0x400U)
#define SAR1_SAR11_BITMASK            (0x800U)
#define SAR1_SAR12_BITMASK            (0x1000U)
#define SAR1_SAR13_BITMASK            (0x2000U)
#define SAR1_SAR14_BITMASK            (0x4000U)
#define SAR1_SAR15_BITMASK            (0x8000U)
#define SAR1_SAR16_BITMASK            (0x10000U)
#define SAR1_SAR17_BITMASK            (0x20000U)
#define SAR1_SAR18_BITMASK            (0x40000U)
#define SAR1_SAR19_BITMASK            (0x80000U)
#define SAR1_SAR20_BITMASK            (0x100000U)
#define SAR1_SAR21_BITMASK            (0x200000U)
#define SAR1_SAR22_BITMASK            (0x400000U)
#define SAR1_SAR23_BITMASK            (0x800000U)
#define SAR1_SAR24_BITMASK            (0x1000000U)
#define SAR1_SAR25_BITMASK            (0x2000000U)
#define SAR1_SAR26_BITMASK            (0x4000000U)
#define SAR1_SAR27_BITMASK            (0x8000000U)
#define SAR1_SAR28_BITMASK            (0x10000000U)
#define SAR1_SAR29_BITMASK            (0x20000000U)
#define SAR1_SAR30_BITMASK            (0x40000000U)
#define SAR1_SAR31_BITMASK            (0x80000000U)
#define SAR1_SAR_GRPMASK              (0xFFFFFFFFU)
#define SAR1_SAR_GRPPOS               (0U)

/*** DAR1 - Destination Address Register 1.; 0x00000114 ***/
#define DAR1                          (*((volatile uint32 *)(&__IPSBAR[0x00000114UL])))
#define DAR1_DAR0_BITMASK             (0x1U)
#define DAR1_DAR1_BITMASK             (0x2U)
#define DAR1_DAR2_BITMASK             (0x4U)
#define DAR1_DAR3_BITMASK             (0x8U)
#define DAR1_DAR4_BITMASK             (0x10U)
#define DAR1_DAR5_BITMASK             (0x20U)
#define DAR1_DAR6_BITMASK             (0x40U)
#define DAR1_DAR7_BITMASK             (0x80U)
#define DAR1_DAR8_BITMASK             (0x100U)
#define DAR1_DAR9_BITMASK             (0x200U)
#define DAR1_DAR10_BITMASK            (0x400U)
#define DAR1_DAR11_BITMASK            (0x800U)
#define DAR1_DAR12_BITMASK            (0x1000U)
#define DAR1_DAR13_BITMASK            (0x2000U)
#define DAR1_DAR14_BITMASK            (0x4000U)
#define DAR1_DAR15_BITMASK            (0x8000U)
#define DAR1_DAR16_BITMASK            (0x10000U)
#define DAR1_DAR17_BITMASK            (0x20000U)
#define DAR1_DAR18_BITMASK            (0x40000U)
#define DAR1_DAR19_BITMASK            (0x80000U)
#define DAR1_DAR20_BITMASK            (0x100000U)
#define DAR1_DAR21_BITMASK            (0x200000U)
#define DAR1_DAR22_BITMASK            (0x400000U)
#define DAR1_DAR23_BITMASK            (0x800000U)
#define DAR1_DAR24_BITMASK            (0x1000000U)
#define DAR1_DAR25_BITMASK            (0x2000000U)
#define DAR1_DAR26_BITMASK            (0x4000000U)
#define DAR1_DAR27_BITMASK            (0x8000000U)
#define DAR1_DAR28_BITMASK            (0x10000000U)
#define DAR1_DAR29_BITMASK            (0x20000000U)
#define DAR1_DAR30_BITMASK            (0x40000000U)
#define DAR1_DAR31_BITMASK            (0x80000000U)
#define DAR1_DAR_GRPMASK              (0xFFFFFFFFU)
#define DAR1_DAR_GRPPOS               (0U)

/*** DSR1 - DMA Status Register 1.; 0x00000118 ***/
#define DSR1                          (*((volatile uint8 *)(&__IPSBAR[0x00000118UL])))
#define DSR1_DONE_BITMASK             (0x1U)
#define DSR1_BSY_BITMASK              (0x2U)
#define DSR1_REQ_BITMASK              (0x4U)
#define DSR1_BED_BITMASK              (0x10U)
#define DSR1_BES_BITMASK              (0x20U)
#define DSR1_CE_BITMASK               (0x40U)

/*** BCR1 - Byte Count Register 1.; 0x00000118 ***/
#define BCR1                          (*((volatile uint32 *)(&__IPSBAR[0x00000118UL])))
#define BCR1_BCR0_BITMASK             (0x1U)
#define BCR1_BCR1_BITMASK             (0x2U)
#define BCR1_BCR2_BITMASK             (0x4U)
#define BCR1_BCR3_BITMASK             (0x8U)
#define BCR1_BCR4_BITMASK             (0x10U)
#define BCR1_BCR5_BITMASK             (0x20U)
#define BCR1_BCR6_BITMASK             (0x40U)
#define BCR1_BCR7_BITMASK             (0x80U)
#define BCR1_BCR8_BITMASK             (0x100U)
#define BCR1_BCR9_BITMASK             (0x200U)
#define BCR1_BCR10_BITMASK            (0x400U)
#define BCR1_BCR11_BITMASK            (0x800U)
#define BCR1_BCR12_BITMASK            (0x1000U)
#define BCR1_BCR13_BITMASK            (0x2000U)
#define BCR1_BCR14_BITMASK            (0x4000U)
#define BCR1_BCR15_BITMASK            (0x8000U)
#define BCR1_BCR16_BITMASK            (0x10000U)
#define BCR1_BCR17_BITMASK            (0x20000U)
#define BCR1_BCR18_BITMASK            (0x40000U)
#define BCR1_BCR19_BITMASK            (0x80000U)
#define BCR1_BCR20_BITMASK            (0x100000U)
#define BCR1_BCR21_BITMASK            (0x200000U)
#define BCR1_BCR22_BITMASK            (0x400000U)
#define BCR1_BCR23_BITMASK            (0x800000U)
#define BCR1_DSR0_BITMASK             (0x1000000U)
#define BCR1_DSR1_BITMASK             (0x2000000U)
#define BCR1_DSR2_BITMASK             (0x4000000U)
#define BCR1_DSR3_BITMASK             (0x8000000U)
#define BCR1_DSR4_BITMASK             (0x10000000U)
#define BCR1_DSR5_BITMASK             (0x20000000U)
#define BCR1_DSR6_BITMASK             (0x40000000U)
#define BCR1_DSR7_BITMASK             (0x80000000U)
#define BCR1_BCR_GRPMASK              (0xFFFFFFU)
#define BCR1_BCR_GRPPOS               (0U)
#define BCR1_DSR_GRPMASK              (0xFF000000U)
#define BCR1_DSR_GRPPOS               (0x18U)

/*** DCR1 - DMA Control Register 1.; 0x0000011C ***/
#define DCR1                          (*((volatile uint32 *)(&__IPSBAR[0x0000011CUL])))
#define DCR1_LCH20_BITMASK            (0x1U)
#define DCR1_LCH21_BITMASK            (0x2U)
#define DCR1_LCH10_BITMASK            (0x4U)
#define DCR1_LCH11_BITMASK            (0x8U)
#define DCR1_LINKCC0_BITMASK          (0x10U)
#define DCR1_LINKCC1_BITMASK          (0x20U)
#define DCR1_D_REQ_BITMASK            (0x80U)
#define DCR1_DMOD0_BITMASK            (0x100U)
#define DCR1_DMOD1_BITMASK            (0x200U)
#define DCR1_DMOD2_BITMASK            (0x400U)
#define DCR1_DMOD3_BITMASK            (0x800U)
#define DCR1_SMOD0_BITMASK            (0x1000U)
#define DCR1_SMOD1_BITMASK            (0x2000U)
#define DCR1_SMOD2_BITMASK            (0x4000U)
#define DCR1_SMOD3_BITMASK            (0x8000U)
#define DCR1_START_BITMASK            (0x10000U)
#define DCR1_DSIZE0_BITMASK           (0x20000U)
#define DCR1_DSIZE1_BITMASK           (0x40000U)
#define DCR1_DINC_BITMASK             (0x80000U)
#define DCR1_SSIZE0_BITMASK           (0x100000U)
#define DCR1_SSIZE1_BITMASK           (0x200000U)
#define DCR1_SINC_BITMASK             (0x400000U)
#define DCR1_BWC0_BITMASK             (0x2000000U)
#define DCR1_BWC1_BITMASK             (0x4000000U)
#define DCR1_BWC2_BITMASK             (0x8000000U)
#define DCR1_AA_BITMASK               (0x10000000U)
#define DCR1_CS_BITMASK               (0x20000000U)
#define DCR1_EEXT_BITMASK             (0x40000000U)
#define DCR1_INT_BITMASK              (0x80000000U)
#define DCR1_LCH2_GRPMASK             (0x3U)
#define DCR1_LCH2_GRPPOS              (0U)
#define DCR1_LCH1_GRPMASK             (0xCU)
#define DCR1_LCH1_GRPPOS              (0x2U)
#define DCR1_LINKCC_GRPMASK           (0x30U)
#define DCR1_LINKCC_GRPPOS            (0x4U)
#define DCR1_DMOD_GRPMASK             (0xF00U)
#define DCR1_DMOD_GRPPOS              (0x8U)
#define DCR1_SMOD_GRPMASK             (0xF000U)
#define DCR1_SMOD_GRPPOS              (0xCU)
#define DCR1_DSIZE_GRPMASK            (0x60000U)
#define DCR1_DSIZE_GRPPOS             (0x11U)
#define DCR1_SSIZE_GRPMASK            (0x300000U)
#define DCR1_SSIZE_GRPPOS             (0x14U)
#define DCR1_BWC_GRPMASK              (0xE000000U)
#define DCR1_BWC_GRPPOS               (0x19U)


/******************************************
*** Peripheral DMA2
*******************************************/

/*** SAR2 - Source Address Register 2.; 0x00000120 ***/
#define SAR2                          (*((volatile uint32 *)(&__IPSBAR[0x00000120UL])))
#define SAR2_SAR0_BITMASK             (0x1U)
#define SAR2_SAR1_BITMASK             (0x2U)
#define SAR2_SAR2_BITMASK             (0x4U)
#define SAR2_SAR3_BITMASK             (0x8U)
#define SAR2_SAR4_BITMASK             (0x10U)
#define SAR2_SAR5_BITMASK             (0x20U)
#define SAR2_SAR6_BITMASK             (0x40U)
#define SAR2_SAR7_BITMASK             (0x80U)
#define SAR2_SAR8_BITMASK             (0x100U)
#define SAR2_SAR9_BITMASK             (0x200U)
#define SAR2_SAR10_BITMASK            (0x400U)
#define SAR2_SAR11_BITMASK            (0x800U)
#define SAR2_SAR12_BITMASK            (0x1000U)
#define SAR2_SAR13_BITMASK            (0x2000U)
#define SAR2_SAR14_BITMASK            (0x4000U)
#define SAR2_SAR15_BITMASK            (0x8000U)
#define SAR2_SAR16_BITMASK            (0x10000U)
#define SAR2_SAR17_BITMASK            (0x20000U)
#define SAR2_SAR18_BITMASK            (0x40000U)
#define SAR2_SAR19_BITMASK            (0x80000U)
#define SAR2_SAR20_BITMASK            (0x100000U)
#define SAR2_SAR21_BITMASK            (0x200000U)
#define SAR2_SAR22_BITMASK            (0x400000U)
#define SAR2_SAR23_BITMASK            (0x800000U)
#define SAR2_SAR24_BITMASK            (0x1000000U)
#define SAR2_SAR25_BITMASK            (0x2000000U)
#define SAR2_SAR26_BITMASK            (0x4000000U)
#define SAR2_SAR27_BITMASK            (0x8000000U)
#define SAR2_SAR28_BITMASK            (0x10000000U)
#define SAR2_SAR29_BITMASK            (0x20000000U)
#define SAR2_SAR30_BITMASK            (0x40000000U)
#define SAR2_SAR31_BITMASK            (0x80000000U)
#define SAR2_SAR_GRPMASK              (0xFFFFFFFFU)
#define SAR2_SAR_GRPPOS               (0U)

/*** DAR2 - Destination Address Register 2.; 0x00000124 ***/
#define DAR2                          (*((volatile uint32 *)(&__IPSBAR[0x00000124UL])))
#define DAR2_DAR0_BITMASK             (0x1U)
#define DAR2_DAR1_BITMASK             (0x2U)
#define DAR2_DAR2_BITMASK             (0x4U)
#define DAR2_DAR3_BITMASK             (0x8U)
#define DAR2_DAR4_BITMASK             (0x10U)
#define DAR2_DAR5_BITMASK             (0x20U)
#define DAR2_DAR6_BITMASK             (0x40U)
#define DAR2_DAR7_BITMASK             (0x80U)
#define DAR2_DAR8_BITMASK             (0x100U)
#define DAR2_DAR9_BITMASK             (0x200U)
#define DAR2_DAR10_BITMASK            (0x400U)
#define DAR2_DAR11_BITMASK            (0x800U)
#define DAR2_DAR12_BITMASK            (0x1000U)
#define DAR2_DAR13_BITMASK            (0x2000U)
#define DAR2_DAR14_BITMASK            (0x4000U)
#define DAR2_DAR15_BITMASK            (0x8000U)
#define DAR2_DAR16_BITMASK            (0x10000U)
#define DAR2_DAR17_BITMASK            (0x20000U)
#define DAR2_DAR18_BITMASK            (0x40000U)
#define DAR2_DAR19_BITMASK            (0x80000U)
#define DAR2_DAR20_BITMASK            (0x100000U)
#define DAR2_DAR21_BITMASK            (0x200000U)
#define DAR2_DAR22_BITMASK            (0x400000U)
#define DAR2_DAR23_BITMASK            (0x800000U)
#define DAR2_DAR24_BITMASK            (0x1000000U)
#define DAR2_DAR25_BITMASK            (0x2000000U)
#define DAR2_DAR26_BITMASK            (0x4000000U)
#define DAR2_DAR27_BITMASK            (0x8000000U)
#define DAR2_DAR28_BITMASK            (0x10000000U)
#define DAR2_DAR29_BITMASK            (0x20000000U)
#define DAR2_DAR30_BITMASK            (0x40000000U)
#define DAR2_DAR31_BITMASK            (0x80000000U)
#define DAR2_DAR_GRPMASK              (0xFFFFFFFFU)
#define DAR2_DAR_GRPPOS               (0U)

/*** DSR2 - DMA Status Register 2.; 0x00000128 ***/
#define DSR2                          (*((volatile uint8 *)(&__IPSBAR[0x00000128UL])))
#define DSR2_DONE_BITMASK             (0x1U)
#define DSR2_BSY_BITMASK              (0x2U)
#define DSR2_REQ_BITMASK              (0x4U)
#define DSR2_BED_BITMASK              (0x10U)
#define DSR2_BES_BITMASK              (0x20U)
#define DSR2_CE_BITMASK               (0x40U)

/*** BCR2 - Byte Count Register 2.; 0x00000128 ***/
#define BCR2                          (*((volatile uint32 *)(&__IPSBAR[0x00000128UL])))
#define BCR2_BCR0_BITMASK             (0x1U)
#define BCR2_BCR1_BITMASK             (0x2U)
#define BCR2_BCR2_BITMASK             (0x4U)
#define BCR2_BCR3_BITMASK             (0x8U)
#define BCR2_BCR4_BITMASK             (0x10U)
#define BCR2_BCR5_BITMASK             (0x20U)
#define BCR2_BCR6_BITMASK             (0x40U)
#define BCR2_BCR7_BITMASK             (0x80U)
#define BCR2_BCR8_BITMASK             (0x100U)
#define BCR2_BCR9_BITMASK             (0x200U)
#define BCR2_BCR10_BITMASK            (0x400U)
#define BCR2_BCR11_BITMASK            (0x800U)
#define BCR2_BCR12_BITMASK            (0x1000U)
#define BCR2_BCR13_BITMASK            (0x2000U)
#define BCR2_BCR14_BITMASK            (0x4000U)
#define BCR2_BCR15_BITMASK            (0x8000U)
#define BCR2_BCR16_BITMASK            (0x10000U)
#define BCR2_BCR17_BITMASK            (0x20000U)
#define BCR2_BCR18_BITMASK            (0x40000U)
#define BCR2_BCR19_BITMASK            (0x80000U)
#define BCR2_BCR20_BITMASK            (0x100000U)
#define BCR2_BCR21_BITMASK            (0x200000U)
#define BCR2_BCR22_BITMASK            (0x400000U)
#define BCR2_BCR23_BITMASK            (0x800000U)
#define BCR2_DSR0_BITMASK             (0x1000000U)
#define BCR2_DSR1_BITMASK             (0x2000000U)
#define BCR2_DSR2_BITMASK             (0x4000000U)
#define BCR2_DSR3_BITMASK             (0x8000000U)
#define BCR2_DSR4_BITMASK             (0x10000000U)
#define BCR2_DSR5_BITMASK             (0x20000000U)
#define BCR2_DSR6_BITMASK             (0x40000000U)
#define BCR2_DSR7_BITMASK             (0x80000000U)
#define BCR2_BCR_GRPMASK              (0xFFFFFFU)
#define BCR2_BCR_GRPPOS               (0U)
#define BCR2_DSR_GRPMASK              (0xFF000000U)
#define BCR2_DSR_GRPPOS               (0x18U)

/*** DCR2 - DMA Control Register 2.; 0x0000012C ***/
#define DCR2                          (*((volatile uint32 *)(&__IPSBAR[0x0000012CUL])))
#define DCR2_LCH20_BITMASK            (0x1U)
#define DCR2_LCH21_BITMASK            (0x2U)
#define DCR2_LCH10_BITMASK            (0x4U)
#define DCR2_LCH11_BITMASK            (0x8U)
#define DCR2_LINKCC0_BITMASK          (0x10U)
#define DCR2_LINKCC1_BITMASK          (0x20U)
#define DCR2_D_REQ_BITMASK            (0x80U)
#define DCR2_DMOD0_BITMASK            (0x100U)
#define DCR2_DMOD1_BITMASK            (0x200U)
#define DCR2_DMOD2_BITMASK            (0x400U)
#define DCR2_DMOD3_BITMASK            (0x800U)
#define DCR2_SMOD0_BITMASK            (0x1000U)
#define DCR2_SMOD1_BITMASK            (0x2000U)
#define DCR2_SMOD2_BITMASK            (0x4000U)
#define DCR2_SMOD3_BITMASK            (0x8000U)
#define DCR2_START_BITMASK            (0x10000U)
#define DCR2_DSIZE0_BITMASK           (0x20000U)
#define DCR2_DSIZE1_BITMASK           (0x40000U)
#define DCR2_DINC_BITMASK             (0x80000U)
#define DCR2_SSIZE0_BITMASK           (0x100000U)
#define DCR2_SSIZE1_BITMASK           (0x200000U)
#define DCR2_SINC_BITMASK             (0x400000U)
#define DCR2_BWC0_BITMASK             (0x2000000U)
#define DCR2_BWC1_BITMASK             (0x4000000U)
#define DCR2_BWC2_BITMASK             (0x8000000U)
#define DCR2_AA_BITMASK               (0x10000000U)
#define DCR2_CS_BITMASK               (0x20000000U)
#define DCR2_EEXT_BITMASK             (0x40000000U)
#define DCR2_INT_BITMASK              (0x80000000U)
#define DCR2_LCH2_GRPMASK             (0x3U)
#define DCR2_LCH2_GRPPOS              (0U)
#define DCR2_LCH1_GRPMASK             (0xCU)
#define DCR2_LCH1_GRPPOS              (0x2U)
#define DCR2_LINKCC_GRPMASK           (0x30U)
#define DCR2_LINKCC_GRPPOS            (0x4U)
#define DCR2_DMOD_GRPMASK             (0xF00U)
#define DCR2_DMOD_GRPPOS              (0x8U)
#define DCR2_SMOD_GRPMASK             (0xF000U)
#define DCR2_SMOD_GRPPOS              (0xCU)
#define DCR2_DSIZE_GRPMASK            (0x60000U)
#define DCR2_DSIZE_GRPPOS             (0x11U)
#define DCR2_SSIZE_GRPMASK            (0x300000U)
#define DCR2_SSIZE_GRPPOS             (0x14U)
#define DCR2_BWC_GRPMASK              (0xE000000U)
#define DCR2_BWC_GRPPOS               (0x19U)


/******************************************
*** Peripheral DMA3
*******************************************/

/*** SAR3 - Source Address Register 3.; 0x00000130 ***/
#define SAR3                          (*((volatile uint32 *)(&__IPSBAR[0x00000130UL])))
#define SAR3_SAR0_BITMASK             (0x1U)
#define SAR3_SAR1_BITMASK             (0x2U)
#define SAR3_SAR2_BITMASK             (0x4U)
#define SAR3_SAR3_BITMASK             (0x8U)
#define SAR3_SAR4_BITMASK             (0x10U)
#define SAR3_SAR5_BITMASK             (0x20U)
#define SAR3_SAR6_BITMASK             (0x40U)
#define SAR3_SAR7_BITMASK             (0x80U)
#define SAR3_SAR8_BITMASK             (0x100U)
#define SAR3_SAR9_BITMASK             (0x200U)
#define SAR3_SAR10_BITMASK            (0x400U)
#define SAR3_SAR11_BITMASK            (0x800U)
#define SAR3_SAR12_BITMASK            (0x1000U)
#define SAR3_SAR13_BITMASK            (0x2000U)
#define SAR3_SAR14_BITMASK            (0x4000U)
#define SAR3_SAR15_BITMASK            (0x8000U)
#define SAR3_SAR16_BITMASK            (0x10000U)
#define SAR3_SAR17_BITMASK            (0x20000U)
#define SAR3_SAR18_BITMASK            (0x40000U)
#define SAR3_SAR19_BITMASK            (0x80000U)
#define SAR3_SAR20_BITMASK            (0x100000U)
#define SAR3_SAR21_BITMASK            (0x200000U)
#define SAR3_SAR22_BITMASK            (0x400000U)
#define SAR3_SAR23_BITMASK            (0x800000U)
#define SAR3_SAR24_BITMASK            (0x1000000U)
#define SAR3_SAR25_BITMASK            (0x2000000U)
#define SAR3_SAR26_BITMASK            (0x4000000U)
#define SAR3_SAR27_BITMASK            (0x8000000U)
#define SAR3_SAR28_BITMASK            (0x10000000U)
#define SAR3_SAR29_BITMASK            (0x20000000U)
#define SAR3_SAR30_BITMASK            (0x40000000U)
#define SAR3_SAR31_BITMASK            (0x80000000U)
#define SAR3_SAR_GRPMASK              (0xFFFFFFFFU)
#define SAR3_SAR_GRPPOS               (0U)

/*** DAR3 - Destination Address Register 3.; 0x00000134 ***/
#define DAR3                          (*((volatile uint32 *)(&__IPSBAR[0x00000134UL])))
#define DAR3_DAR0_BITMASK             (0x1U)
#define DAR3_DAR1_BITMASK             (0x2U)
#define DAR3_DAR2_BITMASK             (0x4U)
#define DAR3_DAR3_BITMASK             (0x8U)
#define DAR3_DAR4_BITMASK             (0x10U)
#define DAR3_DAR5_BITMASK             (0x20U)
#define DAR3_DAR6_BITMASK             (0x40U)
#define DAR3_DAR7_BITMASK             (0x80U)
#define DAR3_DAR8_BITMASK             (0x100U)
#define DAR3_DAR9_BITMASK             (0x200U)
#define DAR3_DAR10_BITMASK            (0x400U)
#define DAR3_DAR11_BITMASK            (0x800U)
#define DAR3_DAR12_BITMASK            (0x1000U)
#define DAR3_DAR13_BITMASK            (0x2000U)
#define DAR3_DAR14_BITMASK            (0x4000U)
#define DAR3_DAR15_BITMASK            (0x8000U)
#define DAR3_DAR16_BITMASK            (0x10000U)
#define DAR3_DAR17_BITMASK            (0x20000U)
#define DAR3_DAR18_BITMASK            (0x40000U)
#define DAR3_DAR19_BITMASK            (0x80000U)
#define DAR3_DAR20_BITMASK            (0x100000U)
#define DAR3_DAR21_BITMASK            (0x200000U)
#define DAR3_DAR22_BITMASK            (0x400000U)
#define DAR3_DAR23_BITMASK            (0x800000U)
#define DAR3_DAR24_BITMASK            (0x1000000U)
#define DAR3_DAR25_BITMASK            (0x2000000U)
#define DAR3_DAR26_BITMASK            (0x4000000U)
#define DAR3_DAR27_BITMASK            (0x8000000U)
#define DAR3_DAR28_BITMASK            (0x10000000U)
#define DAR3_DAR29_BITMASK            (0x20000000U)
#define DAR3_DAR30_BITMASK            (0x40000000U)
#define DAR3_DAR31_BITMASK            (0x80000000U)
#define DAR3_DAR_GRPMASK              (0xFFFFFFFFU)
#define DAR3_DAR_GRPPOS               (0U)

/*** DSR3 - DMA Status Register 3.; 0x00000138 ***/
#define DSR3                          (*((volatile uint8 *)(&__IPSBAR[0x00000138UL])))
#define DSR3_DONE_BITMASK             (0x1U)
#define DSR3_BSY_BITMASK              (0x2U)
#define DSR3_REQ_BITMASK              (0x4U)
#define DSR3_BED_BITMASK              (0x10U)
#define DSR3_BES_BITMASK              (0x20U)
#define DSR3_CE_BITMASK               (0x40U)

/*** BCR3 - Byte Count Register 3.; 0x00000138 ***/
#define BCR3                          (*((volatile uint32 *)(&__IPSBAR[0x00000138UL])))
#define BCR3_BCR0_BITMASK             (0x1U)
#define BCR3_BCR1_BITMASK             (0x2U)
#define BCR3_BCR2_BITMASK             (0x4U)
#define BCR3_BCR3_BITMASK             (0x8U)
#define BCR3_BCR4_BITMASK             (0x10U)
#define BCR3_BCR5_BITMASK             (0x20U)
#define BCR3_BCR6_BITMASK             (0x40U)
#define BCR3_BCR7_BITMASK             (0x80U)
#define BCR3_BCR8_BITMASK             (0x100U)
#define BCR3_BCR9_BITMASK             (0x200U)
#define BCR3_BCR10_BITMASK            (0x400U)
#define BCR3_BCR11_BITMASK            (0x800U)
#define BCR3_BCR12_BITMASK            (0x1000U)
#define BCR3_BCR13_BITMASK            (0x2000U)
#define BCR3_BCR14_BITMASK            (0x4000U)
#define BCR3_BCR15_BITMASK            (0x8000U)
#define BCR3_BCR16_BITMASK            (0x10000U)
#define BCR3_BCR17_BITMASK            (0x20000U)
#define BCR3_BCR18_BITMASK            (0x40000U)
#define BCR3_BCR19_BITMASK            (0x80000U)
#define BCR3_BCR20_BITMASK            (0x100000U)
#define BCR3_BCR21_BITMASK            (0x200000U)
#define BCR3_BCR22_BITMASK            (0x400000U)
#define BCR3_BCR23_BITMASK            (0x800000U)
#define BCR3_DSR0_BITMASK             (0x1000000U)
#define BCR3_DSR1_BITMASK             (0x2000000U)
#define BCR3_DSR2_BITMASK             (0x4000000U)
#define BCR3_DSR3_BITMASK             (0x8000000U)
#define BCR3_DSR4_BITMASK             (0x10000000U)
#define BCR3_DSR5_BITMASK             (0x20000000U)
#define BCR3_DSR6_BITMASK             (0x40000000U)
#define BCR3_DSR7_BITMASK             (0x80000000U)
#define BCR3_BCR_GRPMASK              (0xFFFFFFU)
#define BCR3_BCR_GRPPOS               (0U)
#define BCR3_DSR_GRPMASK              (0xFF000000U)
#define BCR3_DSR_GRPPOS               (0x18U)

/*** DCR3 - DMA Control Register 3.; 0x0000013C ***/
#define DCR3                          (*((volatile uint32 *)(&__IPSBAR[0x0000013CUL])))
#define DCR3_LCH20_BITMASK            (0x1U)
#define DCR3_LCH21_BITMASK            (0x2U)
#define DCR3_LCH10_BITMASK            (0x4U)
#define DCR3_LCH11_BITMASK            (0x8U)
#define DCR3_LINKCC0_BITMASK          (0x10U)
#define DCR3_LINKCC1_BITMASK          (0x20U)
#define DCR3_D_REQ_BITMASK            (0x80U)
#define DCR3_DMOD0_BITMASK            (0x100U)
#define DCR3_DMOD1_BITMASK            (0x200U)
#define DCR3_DMOD2_BITMASK            (0x400U)
#define DCR3_DMOD3_BITMASK            (0x800U)
#define DCR3_SMOD0_BITMASK            (0x1000U)
#define DCR3_SMOD1_BITMASK            (0x2000U)
#define DCR3_SMOD2_BITMASK            (0x4000U)
#define DCR3_SMOD3_BITMASK            (0x8000U)
#define DCR3_START_BITMASK            (0x10000U)
#define DCR3_DSIZE0_BITMASK           (0x20000U)
#define DCR3_DSIZE1_BITMASK           (0x40000U)
#define DCR3_DINC_BITMASK             (0x80000U)
#define DCR3_SSIZE0_BITMASK           (0x100000U)
#define DCR3_SSIZE1_BITMASK           (0x200000U)
#define DCR3_SINC_BITMASK             (0x400000U)
#define DCR3_BWC0_BITMASK             (0x2000000U)
#define DCR3_BWC1_BITMASK             (0x4000000U)
#define DCR3_BWC2_BITMASK             (0x8000000U)
#define DCR3_AA_BITMASK               (0x10000000U)
#define DCR3_CS_BITMASK               (0x20000000U)
#define DCR3_EEXT_BITMASK             (0x40000000U)
#define DCR3_INT_BITMASK              (0x80000000U)
#define DCR3_LCH2_GRPMASK             (0x3U)
#define DCR3_LCH2_GRPPOS              (0U)
#define DCR3_LCH1_GRPMASK             (0xCU)
#define DCR3_LCH1_GRPPOS              (0x2U)
#define DCR3_LINKCC_GRPMASK           (0x30U)
#define DCR3_LINKCC_GRPPOS            (0x4U)
#define DCR3_DMOD_GRPMASK             (0xF00U)
#define DCR3_DMOD_GRPPOS              (0x8U)
#define DCR3_SMOD_GRPMASK             (0xF000U)
#define DCR3_SMOD_GRPPOS              (0xCU)
#define DCR3_DSIZE_GRPMASK            (0x60000U)
#define DCR3_DSIZE_GRPPOS             (0x11U)
#define DCR3_SSIZE_GRPMASK            (0x300000U)
#define DCR3_SSIZE_GRPPOS             (0x14U)
#define DCR3_BWC_GRPMASK              (0xE000000U)
#define DCR3_BWC_GRPPOS               (0x19U)


/******************************************
*** Peripheral UART0
*******************************************/

/*** UMR10 - UART Mode Register 1.; 0x00000200 ***/
#define UMR10                         (*((volatile uint8 *)(&__IPSBAR[0x00000200UL])))
#define UMR10_BC0_BITMASK             (0x1U)
#define UMR10_BC1_BITMASK             (0x2U)
#define UMR10_PT_BITMASK              (0x4U)
#define UMR10_PM0_BITMASK             (0x8U)
#define UMR10_PM1_BITMASK             (0x10U)
#define UMR10_ERR_BITMASK             (0x20U)
#define UMR10_RXIRQ_BITMASK           (0x40U)
#define UMR10_RXRTS_BITMASK           (0x80U)
#define UMR10_BC_GRPMASK              (0x3U)
#define UMR10_BC_GRPPOS               (0U)
#define UMR10_PM_GRPMASK              (0x18U)
#define UMR10_PM_GRPPOS               (0x3U)

/*** UMR20 - UART Mode Register 2.; 0x00000200 ***/
#define UMR20                         (*((volatile uint8 *)(&__IPSBAR[0x00000200UL])))
#define UMR20_SB0_BITMASK             (0x1U)
#define UMR20_SB1_BITMASK             (0x2U)
#define UMR20_SB2_BITMASK             (0x4U)
#define UMR20_SB3_BITMASK             (0x8U)
#define UMR20_TXCTS_BITMASK           (0x10U)
#define UMR20_TXRTS_BITMASK           (0x20U)
#define UMR20_CM0_BITMASK             (0x40U)
#define UMR20_CM1_BITMASK             (0x80U)
#define UMR20_SB_GRPMASK              (0xFU)
#define UMR20_SB_GRPPOS               (0U)
#define UMR20_CM_GRPMASK              (0xC0U)
#define UMR20_CM_GRPPOS               (0x6U)

/*** USR0 - UART Status Register.; 0x00000204 ***/
#define USR0                          (*((volatile uint8 *)(&__IPSBAR[0x00000204UL])))
#define USR0_RXRDY_BITMASK            (0x1U)
#define USR0_FFULL_BITMASK            (0x2U)
#define USR0_TXRDY_BITMASK            (0x4U)
#define USR0_TXEMP_BITMASK            (0x8U)
#define USR0_OE_BITMASK               (0x10U)
#define USR0_PE_BITMASK               (0x20U)
#define USR0_FE_BITMASK               (0x40U)
#define USR0_RB_BITMASK               (0x80U)

/*** UCSR0 - UART Clock Select Register.; 0x00000204 ***/
#define UCSR0                         (*((volatile uint8 *)(&__IPSBAR[0x00000204UL])))
#define UCSR0_TCS0_BITMASK            (0x1U)
#define UCSR0_TCS1_BITMASK            (0x2U)
#define UCSR0_TCS2_BITMASK            (0x4U)
#define UCSR0_TCS3_BITMASK            (0x8U)
#define UCSR0_RCS0_BITMASK            (0x10U)
#define UCSR0_RCS1_BITMASK            (0x20U)
#define UCSR0_RCS2_BITMASK            (0x40U)
#define UCSR0_RCS3_BITMASK            (0x80U)
#define UCSR0_TCS_GRPMASK             (0xFU)
#define UCSR0_TCS_GRPPOS              (0U)
#define UCSR0_RCS_GRPMASK             (0xF0U)
#define UCSR0_RCS_GRPPOS              (0x4U)

/*** UCR0 - UART Command Register.; 0x00000208 ***/
#define UCR0                          (*((volatile uint8 *)(&__IPSBAR[0x00000208UL])))
#define UCR0_RC0_BITMASK              (0x1U)
#define UCR0_RC1_BITMASK              (0x2U)
#define UCR0_TC0_BITMASK              (0x4U)
#define UCR0_TC1_BITMASK              (0x8U)
#define UCR0_MISC0_BITMASK            (0x10U)
#define UCR0_MISC1_BITMASK            (0x20U)
#define UCR0_MISC2_BITMASK            (0x40U)
#define UCR0_RC_GRPMASK               (0x3U)
#define UCR0_RC_GRPPOS                (0U)
#define UCR0_TC_GRPMASK               (0xCU)
#define UCR0_TC_GRPPOS                (0x2U)
#define UCR0_MISC_GRPMASK             (0x70U)
#define UCR0_MISC_GRPPOS              (0x4U)

/*** URB0 - UART Receive Buffer.; 0x0000020C ***/
#define URB0                          (*((volatile uint8 *)(&__IPSBAR[0x0000020CUL])))
#define URB0_RB0_BITMASK              (0x1U)
#define URB0_RB1_BITMASK              (0x2U)
#define URB0_RB2_BITMASK              (0x4U)
#define URB0_RB3_BITMASK              (0x8U)
#define URB0_RB4_BITMASK              (0x10U)
#define URB0_RB5_BITMASK              (0x20U)
#define URB0_RB6_BITMASK              (0x40U)
#define URB0_RB7_BITMASK              (0x80U)
#define URB0_RB_GRPMASK               (0xFFU)
#define URB0_RB_GRPPOS                (0U)

/*** UTB0 - UART Transmit Buffer.; 0x0000020C ***/
#define UTB0                          (*((volatile uint8 *)(&__IPSBAR[0x0000020CUL])))
#define UTB0_TB0_BITMASK              (0x1U)
#define UTB0_TB1_BITMASK              (0x2U)
#define UTB0_TB2_BITMASK              (0x4U)
#define UTB0_TB3_BITMASK              (0x8U)
#define UTB0_TB4_BITMASK              (0x10U)
#define UTB0_TB5_BITMASK              (0x20U)
#define UTB0_TB6_BITMASK              (0x40U)
#define UTB0_TB7_BITMASK              (0x80U)
#define UTB0_TB_GRPMASK               (0xFFU)
#define UTB0_TB_GRPPOS                (0U)

/*** UIPCR0 - UART Input Port Change Register.; 0x00000210 ***/
#define UIPCR0                        (*((volatile uint8 *)(&__IPSBAR[0x00000210UL])))
#define UIPCR0_CTS_BITMASK            (0x1U)
#define UIPCR0_COS_BITMASK            (0x10U)

/*** UACR0 - UART Auxiliary Control Register.; 0x00000210 ***/
#define UACR0                         (*((volatile uint8 *)(&__IPSBAR[0x00000210UL])))
#define UACR0_IEC_BITMASK             (0x1U)

/*** UIMR0 - UART Interrupt Mask Register.; 0x00000214 ***/
#define UIMR0                         (*((volatile uint8 *)(&__IPSBAR[0x00000214UL])))
#define UIMR0_TXRDY_BITMASK           (0x1U)
#define UIMR0_FFULL_RXRDY_BITMASK     (0x2U)
#define UIMR0_DB_BITMASK              (0x4U)
#define UIMR0_COS_BITMASK             (0x80U)

/*** UISR0 - UART Interrupt Status Register.; 0x00000214 ***/
#define UISR0                         (*((volatile uint8 *)(&__IPSBAR[0x00000214UL])))
#define UISR0_TXRDY_BITMASK           (0x1U)
#define UISR0_FFULL_RXRDY_BITMASK     (0x2U)
#define UISR0_DB_BITMASK              (0x4U)
#define UISR0_COS_BITMASK             (0x80U)

/*** UBG10 - UART Baud Rate Generator Register 1.; 0x00000218 ***/
#define UBG10                         (*((volatile uint8 *)(&__IPSBAR[0x00000218UL])))
#define UBG10_Divider_MSB0_BITMASK    (0x1U)
#define UBG10_Divider_MSB1_BITMASK    (0x2U)
#define UBG10_Divider_MSB2_BITMASK    (0x4U)
#define UBG10_Divider_MSB3_BITMASK    (0x8U)
#define UBG10_Divider_MSB4_BITMASK    (0x10U)
#define UBG10_Divider_MSB5_BITMASK    (0x20U)
#define UBG10_Divider_MSB6_BITMASK    (0x40U)
#define UBG10_Divider_MSB7_BITMASK    (0x80U)
#define UBG10_Divider_MSB_GRPMASK     (0xFFU)
#define UBG10_Divider_MSB_GRPPOS      (0U)

/*** UBG20 - UART Baud Rate Generator Register 2.; 0x0000021C ***/
#define UBG20                         (*((volatile uint8 *)(&__IPSBAR[0x0000021CUL])))
#define UBG20_Divider_LSB0_BITMASK    (0x1U)
#define UBG20_Divider_LSB1_BITMASK    (0x2U)
#define UBG20_Divider_LSB2_BITMASK    (0x4U)
#define UBG20_Divider_LSB3_BITMASK    (0x8U)
#define UBG20_Divider_LSB4_BITMASK    (0x10U)
#define UBG20_Divider_LSB5_BITMASK    (0x20U)
#define UBG20_Divider_LSB6_BITMASK    (0x40U)
#define UBG20_Divider_LSB7_BITMASK    (0x80U)
#define UBG20_Divider_LSB_GRPMASK     (0xFFU)
#define UBG20_Divider_LSB_GRPPOS      (0U)

/*** UIP0 - UART Input Port Register.; 0x00000234 ***/
#define UIP0                          (*((volatile uint8 *)(&__IPSBAR[0x00000234UL])))
#define UIP0_CTS_BITMASK              (0x1U)

/*** UOP10 - UART Output Port Command Register 1.; 0x00000238 ***/
#define UOP10                         (*((volatile uint8 *)(&__IPSBAR[0x00000238UL])))
#define UOP10_RTS_BITMASK             (0x1U)

/*** UOP00 - UART Output Port Command Register 0.; 0x0000023C ***/
#define UOP00                         (*((volatile uint8 *)(&__IPSBAR[0x0000023CUL])))
#define UOP00_RTS_BITMASK             (0x1U)


/******************************************
*** Peripheral UART1
*******************************************/

/*** UMR11 - UART Mode Register 1.; 0x00000240 ***/
#define UMR11                         (*((volatile uint8 *)(&__IPSBAR[0x00000240UL])))
#define UMR11_BC0_BITMASK             (0x1U)
#define UMR11_BC1_BITMASK             (0x2U)
#define UMR11_PT_BITMASK              (0x4U)
#define UMR11_PM0_BITMASK             (0x8U)
#define UMR11_PM1_BITMASK             (0x10U)
#define UMR11_ERR_BITMASK             (0x20U)
#define UMR11_RXIRQ_BITMASK           (0x40U)
#define UMR11_RXRTS_BITMASK           (0x80U)
#define UMR11_BC_GRPMASK              (0x3U)
#define UMR11_BC_GRPPOS               (0U)
#define UMR11_PM_GRPMASK              (0x18U)
#define UMR11_PM_GRPPOS               (0x3U)

/*** UMR21 - UART Mode Register 2.; 0x00000240 ***/
#define UMR21                         (*((volatile uint8 *)(&__IPSBAR[0x00000240UL])))
#define UMR21_SB0_BITMASK             (0x1U)
#define UMR21_SB1_BITMASK             (0x2U)
#define UMR21_SB2_BITMASK             (0x4U)
#define UMR21_SB3_BITMASK             (0x8U)
#define UMR21_TXCTS_BITMASK           (0x10U)
#define UMR21_TXRTS_BITMASK           (0x20U)
#define UMR21_CM0_BITMASK             (0x40U)
#define UMR21_CM1_BITMASK             (0x80U)
#define UMR21_SB_GRPMASK              (0xFU)
#define UMR21_SB_GRPPOS               (0U)
#define UMR21_CM_GRPMASK              (0xC0U)
#define UMR21_CM_GRPPOS               (0x6U)

/*** USR1 - UART Status Register.; 0x00000244 ***/
#define USR1                          (*((volatile uint8 *)(&__IPSBAR[0x00000244UL])))
#define USR1_RXRDY_BITMASK            (0x1U)
#define USR1_FFULL_BITMASK            (0x2U)
#define USR1_TXRDY_BITMASK            (0x4U)
#define USR1_TXEMP_BITMASK            (0x8U)
#define USR1_OE_BITMASK               (0x10U)
#define USR1_PE_BITMASK               (0x20U)
#define USR1_FE_BITMASK               (0x40U)
#define USR1_RB_BITMASK               (0x80U)

/*** UCSR1 - UART Clock Select Register.; 0x00000244 ***/
#define UCSR1                         (*((volatile uint8 *)(&__IPSBAR[0x00000244UL])))
#define UCSR1_TCS0_BITMASK            (0x1U)
#define UCSR1_TCS1_BITMASK            (0x2U)
#define UCSR1_TCS2_BITMASK            (0x4U)
#define UCSR1_TCS3_BITMASK            (0x8U)
#define UCSR1_RCS0_BITMASK            (0x10U)
#define UCSR1_RCS1_BITMASK            (0x20U)
#define UCSR1_RCS2_BITMASK            (0x40U)
#define UCSR1_RCS3_BITMASK            (0x80U)
#define UCSR1_TCS_GRPMASK             (0xFU)
#define UCSR1_TCS_GRPPOS              (0U)
#define UCSR1_RCS_GRPMASK             (0xF0U)
#define UCSR1_RCS_GRPPOS              (0x4U)

/*** UCR1 - UART Command Register.; 0x00000248 ***/
#define UCR1                          (*((volatile uint8 *)(&__IPSBAR[0x00000248UL])))
#define UCR1_RC0_BITMASK              (0x1U)
#define UCR1_RC1_BITMASK              (0x2U)
#define UCR1_TC0_BITMASK              (0x4U)
#define UCR1_TC1_BITMASK              (0x8U)
#define UCR1_MISC0_BITMASK            (0x10U)
#define UCR1_MISC1_BITMASK            (0x20U)
#define UCR1_MISC2_BITMASK            (0x40U)
#define UCR1_RC_GRPMASK               (0x3U)
#define UCR1_RC_GRPPOS                (0U)
#define UCR1_TC_GRPMASK               (0xCU)
#define UCR1_TC_GRPPOS                (0x2U)
#define UCR1_MISC_GRPMASK             (0x70U)
#define UCR1_MISC_GRPPOS              (0x4U)

/*** URB1 - UART Receive Buffer.; 0x0000024C ***/
#define URB1                          (*((volatile uint8 *)(&__IPSBAR[0x0000024CUL])))
#define URB1_RB0_BITMASK              (0x1U)
#define URB1_RB1_BITMASK              (0x2U)
#define URB1_RB2_BITMASK              (0x4U)
#define URB1_RB3_BITMASK              (0x8U)
#define URB1_RB4_BITMASK              (0x10U)
#define URB1_RB5_BITMASK              (0x20U)
#define URB1_RB6_BITMASK              (0x40U)
#define URB1_RB7_BITMASK              (0x80U)
#define URB1_RB_GRPMASK               (0xFFU)
#define URB1_RB_GRPPOS                (0U)

/*** UTB1 - UART Transmit Buffer.; 0x0000024C ***/
#define UTB1                          (*((volatile uint8 *)(&__IPSBAR[0x0000024CUL])))
#define UTB1_TB0_BITMASK              (0x1U)
#define UTB1_TB1_BITMASK              (0x2U)
#define UTB1_TB2_BITMASK              (0x4U)
#define UTB1_TB3_BITMASK              (0x8U)
#define UTB1_TB4_BITMASK              (0x10U)
#define UTB1_TB5_BITMASK              (0x20U)
#define UTB1_TB6_BITMASK              (0x40U)
#define UTB1_TB7_BITMASK              (0x80U)
#define UTB1_TB_GRPMASK               (0xFFU)
#define UTB1_TB_GRPPOS                (0U)

/*** UIPCR1 - UART Input Port Change Register.; 0x00000250 ***/
#define UIPCR1                        (*((volatile uint8 *)(&__IPSBAR[0x00000250UL])))
#define UIPCR1_CTS_BITMASK            (0x1U)
#define UIPCR1_COS_BITMASK            (0x10U)

/*** UACR1 - UART Auxiliary Control Register.; 0x00000250 ***/
#define UACR1                         (*((volatile uint8 *)(&__IPSBAR[0x00000250UL])))
#define UACR1_IEC_BITMASK             (0x1U)

/*** UIMR1 - UART Interrupt Mask Register.; 0x00000254 ***/
#define UIMR1                         (*((volatile uint8 *)(&__IPSBAR[0x00000254UL])))
#define UIMR1_TXRDY_BITMASK           (0x1U)
#define UIMR1_FFULL_RXRDY_BITMASK     (0x2U)
#define UIMR1_DB_BITMASK              (0x4U)
#define UIMR1_COS_BITMASK             (0x80U)

/*** UISR1 - UART Interrupt Status Register.; 0x00000254 ***/
#define UISR1                         (*((volatile uint8 *)(&__IPSBAR[0x00000254UL])))
#define UISR1_TXRDY_BITMASK           (0x1U)
#define UISR1_FFULL_RXRDY_BITMASK     (0x2U)
#define UISR1_DB_BITMASK              (0x4U)
#define UISR1_COS_BITMASK             (0x80U)

/*** UBG11 - UART Baud Rate Generator Register 1.; 0x00000258 ***/
#define UBG11                         (*((volatile uint8 *)(&__IPSBAR[0x00000258UL])))
#define UBG11_Divider_MSB0_BITMASK    (0x1U)
#define UBG11_Divider_MSB1_BITMASK    (0x2U)
#define UBG11_Divider_MSB2_BITMASK    (0x4U)
#define UBG11_Divider_MSB3_BITMASK    (0x8U)
#define UBG11_Divider_MSB4_BITMASK    (0x10U)
#define UBG11_Divider_MSB5_BITMASK    (0x20U)
#define UBG11_Divider_MSB6_BITMASK    (0x40U)
#define UBG11_Divider_MSB7_BITMASK    (0x80U)
#define UBG11_Divider_MSB_GRPMASK     (0xFFU)
#define UBG11_Divider_MSB_GRPPOS      (0U)

/*** UBG21 - UART Baud Rate Generator Register 2.; 0x0000025C ***/
#define UBG21                         (*((volatile uint8 *)(&__IPSBAR[0x0000025CUL])))
#define UBG21_Divider_LSB0_BITMASK    (0x1U)
#define UBG21_Divider_LSB1_BITMASK    (0x2U)
#define UBG21_Divider_LSB2_BITMASK    (0x4U)
#define UBG21_Divider_LSB3_BITMASK    (0x8U)
#define UBG21_Divider_LSB4_BITMASK    (0x10U)
#define UBG21_Divider_LSB5_BITMASK    (0x20U)
#define UBG21_Divider_LSB6_BITMASK    (0x40U)
#define UBG21_Divider_LSB7_BITMASK    (0x80U)
#define UBG21_Divider_LSB_GRPMASK     (0xFFU)
#define UBG21_Divider_LSB_GRPPOS      (0U)

/*** UIP1 - UART Input Port Register.; 0x00000274 ***/
#define UIP1                          (*((volatile uint8 *)(&__IPSBAR[0x00000274UL])))
#define UIP1_CTS_BITMASK              (0x1U)

/*** UOP11 - UART Output Port Command Register 1.; 0x00000278 ***/
#define UOP11                         (*((volatile uint8 *)(&__IPSBAR[0x00000278UL])))
#define UOP11_RTS_BITMASK             (0x1U)

/*** UOP01 - UART Output Port Command Register 0.; 0x0000027C ***/
#define UOP01                         (*((volatile uint8 *)(&__IPSBAR[0x0000027CUL])))
#define UOP01_RTS_BITMASK             (0x1U)


/******************************************
*** Peripheral UART2
*******************************************/

/*** UMR12 - UART Mode Register 1.; 0x00000280 ***/
#define UMR12                         (*((volatile uint8 *)(&__IPSBAR[0x00000280UL])))
#define UMR12_BC0_BITMASK             (0x1U)
#define UMR12_BC1_BITMASK             (0x2U)
#define UMR12_PT_BITMASK              (0x4U)
#define UMR12_PM0_BITMASK             (0x8U)
#define UMR12_PM1_BITMASK             (0x10U)
#define UMR12_ERR_BITMASK             (0x20U)
#define UMR12_RXIRQ_BITMASK           (0x40U)
#define UMR12_RXRTS_BITMASK           (0x80U)
#define UMR12_BC_GRPMASK              (0x3U)
#define UMR12_BC_GRPPOS               (0U)
#define UMR12_PM_GRPMASK              (0x18U)
#define UMR12_PM_GRPPOS               (0x3U)

/*** UMR22 - UART Mode Register 2.; 0x00000280 ***/
#define UMR22                         (*((volatile uint8 *)(&__IPSBAR[0x00000280UL])))
#define UMR22_SB0_BITMASK             (0x1U)
#define UMR22_SB1_BITMASK             (0x2U)
#define UMR22_SB2_BITMASK             (0x4U)
#define UMR22_SB3_BITMASK             (0x8U)
#define UMR22_TXCTS_BITMASK           (0x10U)
#define UMR22_TXRTS_BITMASK           (0x20U)
#define UMR22_CM0_BITMASK             (0x40U)
#define UMR22_CM1_BITMASK             (0x80U)
#define UMR22_SB_GRPMASK              (0xFU)
#define UMR22_SB_GRPPOS               (0U)
#define UMR22_CM_GRPMASK              (0xC0U)
#define UMR22_CM_GRPPOS               (0x6U)

/*** USR2 - UART Status Register.; 0x00000284 ***/
#define USR2                          (*((volatile uint8 *)(&__IPSBAR[0x00000284UL])))
#define USR2_RXRDY_BITMASK            (0x1U)
#define USR2_FFULL_BITMASK            (0x2U)
#define USR2_TXRDY_BITMASK            (0x4U)
#define USR2_TXEMP_BITMASK            (0x8U)
#define USR2_OE_BITMASK               (0x10U)
#define USR2_PE_BITMASK               (0x20U)
#define USR2_FE_BITMASK               (0x40U)
#define USR2_RB_BITMASK               (0x80U)

/*** UCSR2 - UART Clock Select Register.; 0x00000284 ***/
#define UCSR2                         (*((volatile uint8 *)(&__IPSBAR[0x00000284UL])))
#define UCSR2_TCS0_BITMASK            (0x1U)
#define UCSR2_TCS1_BITMASK            (0x2U)
#define UCSR2_TCS2_BITMASK            (0x4U)
#define UCSR2_TCS3_BITMASK            (0x8U)
#define UCSR2_RCS0_BITMASK            (0x10U)
#define UCSR2_RCS1_BITMASK            (0x20U)
#define UCSR2_RCS2_BITMASK            (0x40U)
#define UCSR2_RCS3_BITMASK            (0x80U)
#define UCSR2_TCS_GRPMASK             (0xFU)
#define UCSR2_TCS_GRPPOS              (0U)
#define UCSR2_RCS_GRPMASK             (0xF0U)
#define UCSR2_RCS_GRPPOS              (0x4U)

/*** UCR2 - UART Command Register.; 0x00000288 ***/
#define UCR2                          (*((volatile uint8 *)(&__IPSBAR[0x00000288UL])))
#define UCR2_RC0_BITMASK              (0x1U)
#define UCR2_RC1_BITMASK              (0x2U)
#define UCR2_TC0_BITMASK              (0x4U)
#define UCR2_TC1_BITMASK              (0x8U)
#define UCR2_MISC0_BITMASK            (0x10U)
#define UCR2_MISC1_BITMASK            (0x20U)
#define UCR2_MISC2_BITMASK            (0x40U)
#define UCR2_RC_GRPMASK               (0x3U)
#define UCR2_RC_GRPPOS                (0U)
#define UCR2_TC_GRPMASK               (0xCU)
#define UCR2_TC_GRPPOS                (0x2U)
#define UCR2_MISC_GRPMASK             (0x70U)
#define UCR2_MISC_GRPPOS              (0x4U)

/*** URB2 - UART Receive Buffer.; 0x0000028C ***/
#define URB2                          (*((volatile uint8 *)(&__IPSBAR[0x0000028CUL])))
#define URB2_RB0_BITMASK              (0x1U)
#define URB2_RB1_BITMASK              (0x2U)
#define URB2_RB2_BITMASK              (0x4U)
#define URB2_RB3_BITMASK              (0x8U)
#define URB2_RB4_BITMASK              (0x10U)
#define URB2_RB5_BITMASK              (0x20U)
#define URB2_RB6_BITMASK              (0x40U)
#define URB2_RB7_BITMASK              (0x80U)
#define URB2_RB_GRPMASK               (0xFFU)
#define URB2_RB_GRPPOS                (0U)

/*** UTB2 - UART Transmit Buffer.; 0x0000028C ***/
#define UTB2                          (*((volatile uint8 *)(&__IPSBAR[0x0000028CUL])))
#define UTB2_TB0_BITMASK              (0x1U)
#define UTB2_TB1_BITMASK              (0x2U)
#define UTB2_TB2_BITMASK              (0x4U)
#define UTB2_TB3_BITMASK              (0x8U)
#define UTB2_TB4_BITMASK              (0x10U)
#define UTB2_TB5_BITMASK              (0x20U)
#define UTB2_TB6_BITMASK              (0x40U)
#define UTB2_TB7_BITMASK              (0x80U)
#define UTB2_TB_GRPMASK               (0xFFU)
#define UTB2_TB_GRPPOS                (0U)

/*** UIPCR2 - UART Input Port Change Register.; 0x00000290 ***/
#define UIPCR2                        (*((volatile uint8 *)(&__IPSBAR[0x00000290UL])))
#define UIPCR2_CTS_BITMASK            (0x1U)
#define UIPCR2_COS_BITMASK            (0x10U)

/*** UACR2 - UART Auxiliary Control Register.; 0x00000290 ***/
#define UACR2                         (*((volatile uint8 *)(&__IPSBAR[0x00000290UL])))
#define UACR2_IEC_BITMASK             (0x1U)

/*** UIMR2 - UART Interrupt Mask Register.; 0x00000294 ***/
#define UIMR2                         (*((volatile uint8 *)(&__IPSBAR[0x00000294UL])))
#define UIMR2_TXRDY_BITMASK           (0x1U)
#define UIMR2_FFULL_RXRDY_BITMASK     (0x2U)
#define UIMR2_DB_BITMASK              (0x4U)
#define UIMR2_COS_BITMASK             (0x80U)

/*** UISR2 - UART Interrupt Status Register.; 0x00000294 ***/
#define UISR2                         (*((volatile uint8 *)(&__IPSBAR[0x00000294UL])))
#define UISR2_TXRDY_BITMASK           (0x1U)
#define UISR2_FFULL_RXRDY_BITMASK     (0x2U)
#define UISR2_DB_BITMASK              (0x4U)
#define UISR2_COS_BITMASK             (0x80U)

/*** UBG12 - UART Baud Rate Generator Register 1.; 0x00000298 ***/
#define UBG12                         (*((volatile uint8 *)(&__IPSBAR[0x00000298UL])))
#define UBG12_Divider_MSB0_BITMASK    (0x1U)
#define UBG12_Divider_MSB1_BITMASK    (0x2U)
#define UBG12_Divider_MSB2_BITMASK    (0x4U)
#define UBG12_Divider_MSB3_BITMASK    (0x8U)
#define UBG12_Divider_MSB4_BITMASK    (0x10U)
#define UBG12_Divider_MSB5_BITMASK    (0x20U)
#define UBG12_Divider_MSB6_BITMASK    (0x40U)
#define UBG12_Divider_MSB7_BITMASK    (0x80U)
#define UBG12_Divider_MSB_GRPMASK     (0xFFU)
#define UBG12_Divider_MSB_GRPPOS      (0U)

/*** UBG22 - UART Baud Rate Generator Register 2.; 0x0000029C ***/
#define UBG22                         (*((volatile uint8 *)(&__IPSBAR[0x0000029CUL])))
#define UBG22_Divider_LSB0_BITMASK    (0x1U)
#define UBG22_Divider_LSB1_BITMASK    (0x2U)
#define UBG22_Divider_LSB2_BITMASK    (0x4U)
#define UBG22_Divider_LSB3_BITMASK    (0x8U)
#define UBG22_Divider_LSB4_BITMASK    (0x10U)
#define UBG22_Divider_LSB5_BITMASK    (0x20U)
#define UBG22_Divider_LSB6_BITMASK    (0x40U)
#define UBG22_Divider_LSB7_BITMASK    (0x80U)
#define UBG22_Divider_LSB_GRPMASK     (0xFFU)
#define UBG22_Divider_LSB_GRPPOS      (0U)

/*** UIP2 - UART Input Port Register.; 0x000002B4 ***/
#define UIP2                          (*((volatile uint8 *)(&__IPSBAR[0x000002B4UL])))
#define UIP2_CTS_BITMASK              (0x1U)

/*** UOP12 - UART Output Port Command Register 1.; 0x000002B8 ***/
#define UOP12                         (*((volatile uint8 *)(&__IPSBAR[0x000002B8UL])))
#define UOP12_RTS_BITMASK             (0x1U)

/*** UOP02 - UART Output Port Command Register 0.; 0x000002BC ***/
#define UOP02                         (*((volatile uint8 *)(&__IPSBAR[0x000002BCUL])))
#define UOP02_RTS_BITMASK             (0x1U)


/******************************************
*** Peripheral I2C
*******************************************/

/*** I2ADR - I2C Address Register.; 0x00000300 ***/
#define I2ADR                         (*((volatile uint8 *)(&__IPSBAR[0x00000300UL])))
#define I2ADR_ADR1_BITMASK            (0x2U)
#define I2ADR_ADR2_BITMASK            (0x4U)
#define I2ADR_ADR3_BITMASK            (0x8U)
#define I2ADR_ADR4_BITMASK            (0x10U)
#define I2ADR_ADR5_BITMASK            (0x20U)
#define I2ADR_ADR6_BITMASK            (0x40U)
#define I2ADR_ADR7_BITMASK            (0x80U)
#define I2ADR_ADR_GRPMASK             (0xFEU)
#define I2ADR_ADR_GRPPOS              (0x1U)

/*** I2FDR - I2C Frequency Divider Register.; 0x00000304 ***/
#define I2FDR                         (*((volatile uint8 *)(&__IPSBAR[0x00000304UL])))
#define I2FDR_IC0_BITMASK             (0x1U)
#define I2FDR_IC1_BITMASK             (0x2U)
#define I2FDR_IC2_BITMASK             (0x4U)
#define I2FDR_IC3_BITMASK             (0x8U)
#define I2FDR_IC4_BITMASK             (0x10U)
#define I2FDR_IC5_BITMASK             (0x20U)
#define I2FDR_IC_GRPMASK              (0x3FU)
#define I2FDR_IC_GRPPOS               (0U)

/*** I2CR - I2C Control Register.; 0x00000308 ***/
#define I2CR                          (*((volatile uint8 *)(&__IPSBAR[0x00000308UL])))
#define I2CR_RSTA_BITMASK             (0x4U)
#define I2CR_TXAK_BITMASK             (0x8U)
#define I2CR_MTX_BITMASK              (0x10U)
#define I2CR_MSTA_BITMASK             (0x20U)
#define I2CR_IIEN_BITMASK             (0x40U)
#define I2CR_IEN_BITMASK              (0x80U)

/*** I2SR - I2C Status Register.; 0x0000030C ***/
#define I2SR                          (*((volatile uint8 *)(&__IPSBAR[0x0000030CUL])))
#define I2SR_RXAK_BITMASK             (0x1U)
#define I2SR_IIF_BITMASK              (0x2U)
#define I2SR_SRW_BITMASK              (0x4U)
#define I2SR_IAL_BITMASK              (0x10U)
#define I2SR_IBB_BITMASK              (0x20U)
#define I2SR_IAAS_BITMASK             (0x40U)
#define I2SR_ICF_BITMASK              (0x80U)

/*** I2DR - I2C Data I/O Register.; 0x00000310 ***/
#define I2DR                          (*((volatile uint8 *)(&__IPSBAR[0x00000310UL])))
#define I2DR_DATA0_BITMASK            (0x1U)
#define I2DR_DATA1_BITMASK            (0x2U)
#define I2DR_DATA2_BITMASK            (0x4U)
#define I2DR_DATA3_BITMASK            (0x8U)
#define I2DR_DATA4_BITMASK            (0x10U)
#define I2DR_DATA5_BITMASK            (0x20U)
#define I2DR_DATA6_BITMASK            (0x40U)
#define I2DR_DATA7_BITMASK            (0x80U)
#define I2DR_DATA_GRPMASK             (0xFFU)
#define I2DR_DATA_GRPPOS              (0U)


/******************************************
*** Peripheral QSPI
*******************************************/

/*** QMR - QSPI Mode Register.; 0x00000340 ***/
#define QMR                           (*((volatile uint16 *)(&__IPSBAR[0x00000340UL])))
#define QMR_BAUD0_BITMASK             (0x1U)
#define QMR_BAUD1_BITMASK             (0x2U)
#define QMR_BAUD2_BITMASK             (0x4U)
#define QMR_BAUD3_BITMASK             (0x8U)
#define QMR_BAUD4_BITMASK             (0x10U)
#define QMR_BAUD5_BITMASK             (0x20U)
#define QMR_BAUD6_BITMASK             (0x40U)
#define QMR_BAUD7_BITMASK             (0x80U)
#define QMR_CPHA_BITMASK              (0x100U)
#define QMR_CPOL_BITMASK              (0x200U)
#define QMR_BITS0_BITMASK             (0x400U)
#define QMR_BITS1_BITMASK             (0x800U)
#define QMR_BITS2_BITMASK             (0x1000U)
#define QMR_BITS3_BITMASK             (0x2000U)
#define QMR_DOHIE_BITMASK             (0x4000U)
#define QMR_MSTR_BITMASK              (0x8000U)
#define QMR_BAUD_GRPMASK              (0xFFU)
#define QMR_BAUD_GRPPOS               (0U)
#define QMR_BITS_GRPMASK              (0x3C00U)
#define QMR_BITS_GRPPOS               (0xAU)

/*** QDLYR - QSPI Delay Register.; 0x00000344 ***/
#define QDLYR                         (*((volatile uint16 *)(&__IPSBAR[0x00000344UL])))
#define QDLYR_DTL0_BITMASK            (0x1U)
#define QDLYR_DTL1_BITMASK            (0x2U)
#define QDLYR_DTL2_BITMASK            (0x4U)
#define QDLYR_DTL3_BITMASK            (0x8U)
#define QDLYR_DTL4_BITMASK            (0x10U)
#define QDLYR_DTL5_BITMASK            (0x20U)
#define QDLYR_DTL6_BITMASK            (0x40U)
#define QDLYR_DTL7_BITMASK            (0x80U)
#define QDLYR_QCD0_BITMASK            (0x100U)
#define QDLYR_QCD1_BITMASK            (0x200U)
#define QDLYR_QCD2_BITMASK            (0x400U)
#define QDLYR_QCD3_BITMASK            (0x800U)
#define QDLYR_QCD4_BITMASK            (0x1000U)
#define QDLYR_QCD5_BITMASK            (0x2000U)
#define QDLYR_QCD6_BITMASK            (0x4000U)
#define QDLYR_SPE_BITMASK             (0x8000U)
#define QDLYR_DTL_GRPMASK             (0xFFU)
#define QDLYR_DTL_GRPPOS              (0U)
#define QDLYR_QCD_GRPMASK             (0x7F00U)
#define QDLYR_QCD_GRPPOS              (0x8U)

/*** QWR - QSPI Wrap Register.; 0x00000348 ***/
#define QWR                           (*((volatile uint16 *)(&__IPSBAR[0x00000348UL])))
#define QWR_NEWQP0_BITMASK            (0x1U)
#define QWR_NEWQP1_BITMASK            (0x2U)
#define QWR_NEWQP2_BITMASK            (0x4U)
#define QWR_NEWQP3_BITMASK            (0x8U)
#define QWR_CPTQP0_BITMASK            (0x10U)
#define QWR_CPTQP1_BITMASK            (0x20U)
#define QWR_CPTQP2_BITMASK            (0x40U)
#define QWR_CPTQP3_BITMASK            (0x80U)
#define QWR_ENDQP0_BITMASK            (0x100U)
#define QWR_ENDQP1_BITMASK            (0x200U)
#define QWR_ENDQP2_BITMASK            (0x400U)
#define QWR_ENDQP3_BITMASK            (0x800U)
#define QWR_CSIV_BITMASK              (0x1000U)
#define QWR_WRTO_BITMASK              (0x2000U)
#define QWR_WREN_BITMASK              (0x4000U)
#define QWR_HALT_BITMASK              (0x8000U)
#define QWR_NEWQP_GRPMASK             (0xFU)
#define QWR_NEWQP_GRPPOS              (0U)
#define QWR_CPTQP_GRPMASK             (0xF0U)
#define QWR_CPTQP_GRPPOS              (0x4U)
#define QWR_ENDQP_GRPMASK             (0xF00U)
#define QWR_ENDQP_GRPPOS              (0x8U)

/*** QIR - QSPI Interrupt Register.; 0x0000034C ***/
#define QIR                           (*((volatile uint16 *)(&__IPSBAR[0x0000034CUL])))
#define QIR_SPIF_BITMASK              (0x1U)
#define QIR_ABRT_BITMASK              (0x4U)
#define QIR_WCEF_BITMASK              (0x8U)
#define QIR_SPIFE_BITMASK             (0x100U)
#define QIR_ABRTE_BITMASK             (0x400U)
#define QIR_WCEFE_BITMASK             (0x800U)
#define QIR_ABRTL_BITMASK             (0x1000U)
#define QIR_ABRTB_BITMASK             (0x4000U)
#define QIR_WCEFB_BITMASK             (0x8000U)

/*** QAR - QSPI Address Register.; 0x00000350 ***/
#define QAR                           (*((volatile uint16 *)(&__IPSBAR[0x00000350UL])))
#define QAR_ADDR0_BITMASK             (0x1U)
#define QAR_ADDR1_BITMASK             (0x2U)
#define QAR_ADDR2_BITMASK             (0x4U)
#define QAR_ADDR3_BITMASK             (0x8U)
#define QAR_ADDR4_BITMASK             (0x10U)
#define QAR_ADDR5_BITMASK             (0x20U)
#define QAR_ADDR_GRPMASK              (0x3FU)
#define QAR_ADDR_GRPPOS               (0U)

/*** QDR - QSPI Data Register.; 0x00000354 ***/
#define QDR                           (*((volatile uint16 *)(&__IPSBAR[0x00000354UL])))
#define QDR_DATA0_BITMASK             (0x1U)
#define QDR_DATA1_BITMASK             (0x2U)
#define QDR_DATA2_BITMASK             (0x4U)
#define QDR_DATA3_BITMASK             (0x8U)
#define QDR_DATA4_BITMASK             (0x10U)
#define QDR_DATA5_BITMASK             (0x20U)
#define QDR_DATA6_BITMASK             (0x40U)
#define QDR_DATA7_BITMASK             (0x80U)
#define QDR_DATA8_BITMASK             (0x100U)
#define QDR_DATA9_BITMASK             (0x200U)
#define QDR_DATA10_BITMASK            (0x400U)
#define QDR_DATA11_BITMASK            (0x800U)
#define QDR_DATA12_BITMASK            (0x1000U)
#define QDR_DATA13_BITMASK            (0x2000U)
#define QDR_DATA14_BITMASK            (0x4000U)
#define QDR_DATA15_BITMASK            (0x8000U)
#define QDR_DATA_GRPMASK              (0xFFFFU)
#define QDR_DATA_GRPPOS               (0U)


/******************************************
*** Peripheral RTC
*******************************************/

/*** HOURMIN - RTC Hours and Minutes Counter Register.; 0x000003C0 ***/
#define HOURMIN                       (*((volatile uint32 *)(&__IPSBAR[0x000003C0UL])))
#define HOURMIN_MINUTES0_BITMASK      (0x1U)
#define HOURMIN_MINUTES1_BITMASK      (0x2U)
#define HOURMIN_MINUTES2_BITMASK      (0x4U)
#define HOURMIN_MINUTES3_BITMASK      (0x8U)
#define HOURMIN_MINUTES4_BITMASK      (0x10U)
#define HOURMIN_MINUTES5_BITMASK      (0x20U)
#define HOURMIN_HOURS0_BITMASK        (0x100U)
#define HOURMIN_HOURS1_BITMASK        (0x200U)
#define HOURMIN_HOURS2_BITMASK        (0x400U)
#define HOURMIN_HOURS3_BITMASK        (0x800U)
#define HOURMIN_HOURS4_BITMASK        (0x1000U)
#define HOURMIN_MINUTES_GRPMASK       (0x3FU)
#define HOURMIN_MINUTES_GRPPOS        (0U)
#define HOURMIN_HOURS_GRPMASK         (0x1F00U)
#define HOURMIN_HOURS_GRPPOS          (0x8U)

/*** SECONDS - RTC Seconds Counter Register.; 0x000003C4 ***/
#define SECONDS                       (*((volatile uint32 *)(&__IPSBAR[0x000003C4UL])))
#define SECONDS_SECONDS0_BITMASK      (0x1U)
#define SECONDS_SECONDS1_BITMASK      (0x2U)
#define SECONDS_SECONDS2_BITMASK      (0x4U)
#define SECONDS_SECONDS3_BITMASK      (0x8U)
#define SECONDS_SECONDS4_BITMASK      (0x10U)
#define SECONDS_SECONDS5_BITMASK      (0x20U)
#define SECONDS_SECONDS_GRPMASK       (0x3FU)
#define SECONDS_SECONDS_GRPPOS        (0U)

/*** ALRM_HM - RTC Hours and Minutes Alarm Register.; 0x000003C8 ***/
#define ALRM_HM                       (*((volatile uint32 *)(&__IPSBAR[0x000003C8UL])))
#define ALRM_HM_MINUTES0_BITMASK      (0x1U)
#define ALRM_HM_MINUTES1_BITMASK      (0x2U)
#define ALRM_HM_MINUTES2_BITMASK      (0x4U)
#define ALRM_HM_MINUTES3_BITMASK      (0x8U)
#define ALRM_HM_MINUTES4_BITMASK      (0x10U)
#define ALRM_HM_MINUTES5_BITMASK      (0x20U)
#define ALRM_HM_HOURS0_BITMASK        (0x100U)
#define ALRM_HM_HOURS1_BITMASK        (0x200U)
#define ALRM_HM_HOURS2_BITMASK        (0x400U)
#define ALRM_HM_HOURS3_BITMASK        (0x800U)
#define ALRM_HM_HOURS4_BITMASK        (0x1000U)
#define ALRM_HM_MINUTES_GRPMASK       (0x3FU)
#define ALRM_HM_MINUTES_GRPPOS        (0U)
#define ALRM_HM_HOURS_GRPMASK         (0x1F00U)
#define ALRM_HM_HOURS_GRPPOS          (0x8U)

/*** ALRM_SEC - RTC Seconds Alarm Register.; 0x000003CC ***/
#define ALRM_SEC                      (*((volatile uint32 *)(&__IPSBAR[0x000003CCUL])))
#define ALRM_SEC_SECONDS0_BITMASK     (0x1U)
#define ALRM_SEC_SECONDS1_BITMASK     (0x2U)
#define ALRM_SEC_SECONDS2_BITMASK     (0x4U)
#define ALRM_SEC_SECONDS3_BITMASK     (0x8U)
#define ALRM_SEC_SECONDS4_BITMASK     (0x10U)
#define ALRM_SEC_SECONDS5_BITMASK     (0x20U)
#define ALRM_SEC_SECONDS_GRPMASK      (0x3FU)
#define ALRM_SEC_SECONDS_GRPPOS       (0U)

/*** RTCCTL - RTC Control Register.; 0x000003D0 ***/
#define RTCCTL                        (*((volatile uint32 *)(&__IPSBAR[0x000003D0UL])))
#define RTCCTL_SWR_BITMASK            (0x1U)
#define RTCCTL_EN_BITMASK             (0x80U)

/*** RTCISR - RTC Interrupt Status Register.; 0x000003D4 ***/
#define RTCISR                        (*((volatile uint32 *)(&__IPSBAR[0x000003D4UL])))
#define RTCISR_SW_BITMASK             (0x1U)
#define RTCISR_MIN_BITMASK            (0x2U)
#define RTCISR_ALM_BITMASK            (0x4U)
#define RTCISR_DAY_BITMASK            (0x8U)
#define RTCISR_1HZ_BITMASK            (0x10U)
#define RTCISR_HR_BITMASK             (0x20U)

/*** RTCIENR - RTC Interrupt Enable Register.; 0x000003D8 ***/
#define RTCIENR                       (*((volatile uint32 *)(&__IPSBAR[0x000003D8UL])))
#define RTCIENR_SW_BITMASK            (0x1U)
#define RTCIENR_MIN_BITMASK           (0x2U)
#define RTCIENR_ALM_BITMASK           (0x4U)
#define RTCIENR_DAY_BITMASK           (0x8U)
#define RTCIENR_1HZ_BITMASK           (0x10U)
#define RTCIENR_HR_BITMASK            (0x20U)

/*** STPWCH - RTC Stopwatch Minutes Register.; 0x000003DC ***/
#define STPWCH                        (*((volatile uint32 *)(&__IPSBAR[0x000003DCUL])))
#define STPWCH_CNT0_BITMASK           (0x1U)
#define STPWCH_CNT1_BITMASK           (0x2U)
#define STPWCH_CNT2_BITMASK           (0x4U)
#define STPWCH_CNT3_BITMASK           (0x8U)
#define STPWCH_CNT4_BITMASK           (0x10U)
#define STPWCH_CNT5_BITMASK           (0x20U)
#define STPWCH_CNT_GRPMASK            (0x3FU)
#define STPWCH_CNT_GRPPOS             (0U)

/*** DAYS - RTC Days Counter Register.; 0x000003E0 ***/
#define DAYS                          (*((volatile uint32 *)(&__IPSBAR[0x000003E0UL])))
#define DAYS_DAYS0_BITMASK            (0x1U)
#define DAYS_DAYS1_BITMASK            (0x2U)
#define DAYS_DAYS2_BITMASK            (0x4U)
#define DAYS_DAYS3_BITMASK            (0x8U)
#define DAYS_DAYS4_BITMASK            (0x10U)
#define DAYS_DAYS5_BITMASK            (0x20U)
#define DAYS_DAYS6_BITMASK            (0x40U)
#define DAYS_DAYS7_BITMASK            (0x80U)
#define DAYS_DAYS8_BITMASK            (0x100U)
#define DAYS_DAYS9_BITMASK            (0x200U)
#define DAYS_DAYS10_BITMASK           (0x400U)
#define DAYS_DAYS11_BITMASK           (0x800U)
#define DAYS_DAYS12_BITMASK           (0x1000U)
#define DAYS_DAYS13_BITMASK           (0x2000U)
#define DAYS_DAYS14_BITMASK           (0x4000U)
#define DAYS_DAYS15_BITMASK           (0x8000U)
#define DAYS_DAYS_GRPMASK             (0xFFFFU)
#define DAYS_DAYS_GRPPOS              (0U)

/*** ALRM_DAY - RTC Day Alarm Register.; 0x000003E4 ***/
#define ALRM_DAY                      (*((volatile uint32 *)(&__IPSBAR[0x000003E4UL])))
#define ALRM_DAY_DAYSAL0_BITMASK      (0x1U)
#define ALRM_DAY_DAYSAL1_BITMASK      (0x2U)
#define ALRM_DAY_DAYSAL2_BITMASK      (0x4U)
#define ALRM_DAY_DAYSAL3_BITMASK      (0x8U)
#define ALRM_DAY_DAYSAL4_BITMASK      (0x10U)
#define ALRM_DAY_DAYSAL5_BITMASK      (0x20U)
#define ALRM_DAY_DAYSAL6_BITMASK      (0x40U)
#define ALRM_DAY_DAYSAL7_BITMASK      (0x80U)
#define ALRM_DAY_DAYSAL8_BITMASK      (0x100U)
#define ALRM_DAY_DAYSAL9_BITMASK      (0x200U)
#define ALRM_DAY_DAYSAL10_BITMASK     (0x400U)
#define ALRM_DAY_DAYSAL11_BITMASK     (0x800U)
#define ALRM_DAY_DAYSAL12_BITMASK     (0x1000U)
#define ALRM_DAY_DAYSAL13_BITMASK     (0x2000U)
#define ALRM_DAY_DAYSAL14_BITMASK     (0x4000U)
#define ALRM_DAY_DAYSAL15_BITMASK     (0x8000U)
#define ALRM_DAY_DAYSAL_GRPMASK       (0xFFFFU)
#define ALRM_DAY_DAYSAL_GRPPOS        (0U)


/******************************************
*** Peripheral DTIM0
*******************************************/

/*** DTMR0 - DMA Timer 0 Mode Register.; 0x00000400 ***/
#define DTMR0                         (*((volatile uint16 *)(&__IPSBAR[0x00000400UL])))
#define DTMR0_RST_BITMASK             (0x1U)
#define DTMR0_CLK0_BITMASK            (0x2U)
#define DTMR0_CLK1_BITMASK            (0x4U)
#define DTMR0_FRR_BITMASK             (0x8U)
#define DTMR0_ORRI_BITMASK            (0x10U)
#define DTMR0_OM_BITMASK              (0x20U)
#define DTMR0_CE0_BITMASK             (0x40U)
#define DTMR0_CE1_BITMASK             (0x80U)
#define DTMR0_PS0_BITMASK             (0x100U)
#define DTMR0_PS1_BITMASK             (0x200U)
#define DTMR0_PS2_BITMASK             (0x400U)
#define DTMR0_PS3_BITMASK             (0x800U)
#define DTMR0_PS4_BITMASK             (0x1000U)
#define DTMR0_PS5_BITMASK             (0x2000U)
#define DTMR0_PS6_BITMASK             (0x4000U)
#define DTMR0_PS7_BITMASK             (0x8000U)
#define DTMR0_CLK_GRPMASK             (0x6U)
#define DTMR0_CLK_GRPPOS              (0x1U)
#define DTMR0_CE_GRPMASK              (0xC0U)
#define DTMR0_CE_GRPPOS               (0x6U)
#define DTMR0_PS_GRPMASK              (0xFF00U)
#define DTMR0_PS_GRPPOS               (0x8U)

/*** DTXMR0 - DMA Timer 0  Extended Mode Register.; 0x00000402 ***/
#define DTXMR0                        (*((volatile uint8 *)(&__IPSBAR[0x00000402UL])))
#define DTXMR0_MODE16_BITMASK         (0x1U)
#define DTXMR0_HALTED_BITMASK         (0x40U)
#define DTXMR0_DMAEN_BITMASK          (0x80U)

/*** DTER0 - DMA Timer 0 Event Register.; 0x00000403 ***/
#define DTER0                         (*((volatile uint8 *)(&__IPSBAR[0x00000403UL])))
#define DTER0_CAP_BITMASK             (0x1U)
#define DTER0_REF_BITMASK             (0x2U)

/*** DTRR0 - DMA Timer 0 Reference Register.; 0x00000404 ***/
#define DTRR0                         (*((volatile uint32 *)(&__IPSBAR[0x00000404UL])))
#define DTRR0_REF0_BITMASK            (0x1U)
#define DTRR0_REF1_BITMASK            (0x2U)
#define DTRR0_REF2_BITMASK            (0x4U)
#define DTRR0_REF3_BITMASK            (0x8U)
#define DTRR0_REF4_BITMASK            (0x10U)
#define DTRR0_REF5_BITMASK            (0x20U)
#define DTRR0_REF6_BITMASK            (0x40U)
#define DTRR0_REF7_BITMASK            (0x80U)
#define DTRR0_REF8_BITMASK            (0x100U)
#define DTRR0_REF9_BITMASK            (0x200U)
#define DTRR0_REF10_BITMASK           (0x400U)
#define DTRR0_REF11_BITMASK           (0x800U)
#define DTRR0_REF12_BITMASK           (0x1000U)
#define DTRR0_REF13_BITMASK           (0x2000U)
#define DTRR0_REF14_BITMASK           (0x4000U)
#define DTRR0_REF15_BITMASK           (0x8000U)
#define DTRR0_REF16_BITMASK           (0x10000U)
#define DTRR0_REF17_BITMASK           (0x20000U)
#define DTRR0_REF18_BITMASK           (0x40000U)
#define DTRR0_REF19_BITMASK           (0x80000U)
#define DTRR0_REF20_BITMASK           (0x100000U)
#define DTRR0_REF21_BITMASK           (0x200000U)
#define DTRR0_REF22_BITMASK           (0x400000U)
#define DTRR0_REF23_BITMASK           (0x800000U)
#define DTRR0_REF24_BITMASK           (0x1000000U)
#define DTRR0_REF25_BITMASK           (0x2000000U)
#define DTRR0_REF26_BITMASK           (0x4000000U)
#define DTRR0_REF27_BITMASK           (0x8000000U)
#define DTRR0_REF28_BITMASK           (0x10000000U)
#define DTRR0_REF29_BITMASK           (0x20000000U)
#define DTRR0_REF30_BITMASK           (0x40000000U)
#define DTRR0_REF31_BITMASK           (0x80000000U)
#define DTRR0_REF_GRPMASK             (0xFFFFFFFFU)
#define DTRR0_REF_GRPPOS              (0U)

/*** DTCR0 - DMA Timer 0 Capture Register.; 0x00000408 ***/
#define DTCR0                         (*((volatile uint32 *)(&__IPSBAR[0x00000408UL])))
#define DTCR0_CAP0_BITMASK            (0x1U)
#define DTCR0_CAP1_BITMASK            (0x2U)
#define DTCR0_CAP2_BITMASK            (0x4U)
#define DTCR0_CAP3_BITMASK            (0x8U)
#define DTCR0_CAP4_BITMASK            (0x10U)
#define DTCR0_CAP5_BITMASK            (0x20U)
#define DTCR0_CAP6_BITMASK            (0x40U)
#define DTCR0_CAP7_BITMASK            (0x80U)
#define DTCR0_CAP8_BITMASK            (0x100U)
#define DTCR0_CAP9_BITMASK            (0x200U)
#define DTCR0_CAP10_BITMASK           (0x400U)
#define DTCR0_CAP11_BITMASK           (0x800U)
#define DTCR0_CAP12_BITMASK           (0x1000U)
#define DTCR0_CAP13_BITMASK           (0x2000U)
#define DTCR0_CAP14_BITMASK           (0x4000U)
#define DTCR0_CAP15_BITMASK           (0x8000U)
#define DTCR0_CAP16_BITMASK           (0x10000U)
#define DTCR0_CAP17_BITMASK           (0x20000U)
#define DTCR0_CAP18_BITMASK           (0x40000U)
#define DTCR0_CAP19_BITMASK           (0x80000U)
#define DTCR0_CAP20_BITMASK           (0x100000U)
#define DTCR0_CAP21_BITMASK           (0x200000U)
#define DTCR0_CAP22_BITMASK           (0x400000U)
#define DTCR0_CAP23_BITMASK           (0x800000U)
#define DTCR0_CAP24_BITMASK           (0x1000000U)
#define DTCR0_CAP25_BITMASK           (0x2000000U)
#define DTCR0_CAP26_BITMASK           (0x4000000U)
#define DTCR0_CAP27_BITMASK           (0x8000000U)
#define DTCR0_CAP28_BITMASK           (0x10000000U)
#define DTCR0_CAP29_BITMASK           (0x20000000U)
#define DTCR0_CAP30_BITMASK           (0x40000000U)
#define DTCR0_CAP31_BITMASK           (0x80000000U)
#define DTCR0_CAP_GRPMASK             (0xFFFFFFFFU)
#define DTCR0_CAP_GRPPOS              (0U)

/*** DTCN0 - DMA Timer 0 Counter.; 0x0000040C ***/
#define DTCN0                         (*((volatile uint32 *)(&__IPSBAR[0x0000040CUL])))
#define DTCN0_CNT0_BITMASK            (0x1U)
#define DTCN0_CNT1_BITMASK            (0x2U)
#define DTCN0_CNT2_BITMASK            (0x4U)
#define DTCN0_CNT3_BITMASK            (0x8U)
#define DTCN0_CNT4_BITMASK            (0x10U)
#define DTCN0_CNT5_BITMASK            (0x20U)
#define DTCN0_CNT6_BITMASK            (0x40U)
#define DTCN0_CNT7_BITMASK            (0x80U)
#define DTCN0_CNT8_BITMASK            (0x100U)
#define DTCN0_CNT9_BITMASK            (0x200U)
#define DTCN0_CNT10_BITMASK           (0x400U)
#define DTCN0_CNT11_BITMASK           (0x800U)
#define DTCN0_CNT12_BITMASK           (0x1000U)
#define DTCN0_CNT13_BITMASK           (0x2000U)
#define DTCN0_CNT14_BITMASK           (0x4000U)
#define DTCN0_CNT15_BITMASK           (0x8000U)
#define DTCN0_CNT16_BITMASK           (0x10000U)
#define DTCN0_CNT17_BITMASK           (0x20000U)
#define DTCN0_CNT18_BITMASK           (0x40000U)
#define DTCN0_CNT19_BITMASK           (0x80000U)
#define DTCN0_CNT20_BITMASK           (0x100000U)
#define DTCN0_CNT21_BITMASK           (0x200000U)
#define DTCN0_CNT22_BITMASK           (0x400000U)
#define DTCN0_CNT23_BITMASK           (0x800000U)
#define DTCN0_CNT24_BITMASK           (0x1000000U)
#define DTCN0_CNT25_BITMASK           (0x2000000U)
#define DTCN0_CNT26_BITMASK           (0x4000000U)
#define DTCN0_CNT27_BITMASK           (0x8000000U)
#define DTCN0_CNT28_BITMASK           (0x10000000U)
#define DTCN0_CNT29_BITMASK           (0x20000000U)
#define DTCN0_CNT30_BITMASK           (0x40000000U)
#define DTCN0_CNT31_BITMASK           (0x80000000U)
#define DTCN0_CNT_GRPMASK             (0xFFFFFFFFU)
#define DTCN0_CNT_GRPPOS              (0U)


/******************************************
*** Peripheral DTIM1
*******************************************/

/*** DTMR1 - DMA Timer 1 Mode Register.; 0x00000440 ***/
#define DTMR1                         (*((volatile uint16 *)(&__IPSBAR[0x00000440UL])))
#define DTMR1_RST_BITMASK             (0x1U)
#define DTMR1_CLK0_BITMASK            (0x2U)
#define DTMR1_CLK1_BITMASK            (0x4U)
#define DTMR1_FRR_BITMASK             (0x8U)
#define DTMR1_ORRI_BITMASK            (0x10U)
#define DTMR1_OM_BITMASK              (0x20U)
#define DTMR1_CE0_BITMASK             (0x40U)
#define DTMR1_CE1_BITMASK             (0x80U)
#define DTMR1_PS0_BITMASK             (0x100U)
#define DTMR1_PS1_BITMASK             (0x200U)
#define DTMR1_PS2_BITMASK             (0x400U)
#define DTMR1_PS3_BITMASK             (0x800U)
#define DTMR1_PS4_BITMASK             (0x1000U)
#define DTMR1_PS5_BITMASK             (0x2000U)
#define DTMR1_PS6_BITMASK             (0x4000U)
#define DTMR1_PS7_BITMASK             (0x8000U)
#define DTMR1_CLK_GRPMASK             (0x6U)
#define DTMR1_CLK_GRPPOS              (0x1U)
#define DTMR1_CE_GRPMASK              (0xC0U)
#define DTMR1_CE_GRPPOS               (0x6U)
#define DTMR1_PS_GRPMASK              (0xFF00U)
#define DTMR1_PS_GRPPOS               (0x8U)

/*** DTXMR1 - DMA Timer 1  Extended Mode Register.; 0x00000442 ***/
#define DTXMR1                        (*((volatile uint8 *)(&__IPSBAR[0x00000442UL])))
#define DTXMR1_MODE16_BITMASK         (0x1U)
#define DTXMR1_HALTED_BITMASK         (0x40U)
#define DTXMR1_DMAEN_BITMASK          (0x80U)

/*** DTER1 - DMA Timer 1 Event Register.; 0x00000443 ***/
#define DTER1                         (*((volatile uint8 *)(&__IPSBAR[0x00000443UL])))
#define DTER1_CAP_BITMASK             (0x1U)
#define DTER1_REF_BITMASK             (0x2U)

/*** DTRR1 - DMA Timer 1 Reference Register.; 0x00000444 ***/
#define DTRR1                         (*((volatile uint32 *)(&__IPSBAR[0x00000444UL])))
#define DTRR1_REF0_BITMASK            (0x1U)
#define DTRR1_REF1_BITMASK            (0x2U)
#define DTRR1_REF2_BITMASK            (0x4U)
#define DTRR1_REF3_BITMASK            (0x8U)
#define DTRR1_REF4_BITMASK            (0x10U)
#define DTRR1_REF5_BITMASK            (0x20U)
#define DTRR1_REF6_BITMASK            (0x40U)
#define DTRR1_REF7_BITMASK            (0x80U)
#define DTRR1_REF8_BITMASK            (0x100U)
#define DTRR1_REF9_BITMASK            (0x200U)
#define DTRR1_REF10_BITMASK           (0x400U)
#define DTRR1_REF11_BITMASK           (0x800U)
#define DTRR1_REF12_BITMASK           (0x1000U)
#define DTRR1_REF13_BITMASK           (0x2000U)
#define DTRR1_REF14_BITMASK           (0x4000U)
#define DTRR1_REF15_BITMASK           (0x8000U)
#define DTRR1_REF16_BITMASK           (0x10000U)
#define DTRR1_REF17_BITMASK           (0x20000U)
#define DTRR1_REF18_BITMASK           (0x40000U)
#define DTRR1_REF19_BITMASK           (0x80000U)
#define DTRR1_REF20_BITMASK           (0x100000U)
#define DTRR1_REF21_BITMASK           (0x200000U)
#define DTRR1_REF22_BITMASK           (0x400000U)
#define DTRR1_REF23_BITMASK           (0x800000U)
#define DTRR1_REF24_BITMASK           (0x1000000U)
#define DTRR1_REF25_BITMASK           (0x2000000U)
#define DTRR1_REF26_BITMASK           (0x4000000U)
#define DTRR1_REF27_BITMASK           (0x8000000U)
#define DTRR1_REF28_BITMASK           (0x10000000U)
#define DTRR1_REF29_BITMASK           (0x20000000U)
#define DTRR1_REF30_BITMASK           (0x40000000U)
#define DTRR1_REF31_BITMASK           (0x80000000U)
#define DTRR1_REF_GRPMASK             (0xFFFFFFFFU)
#define DTRR1_REF_GRPPOS              (0U)

/*** DTCR1 - DMA Timer 1 Capture Register.; 0x00000448 ***/
#define DTCR1                         (*((volatile uint32 *)(&__IPSBAR[0x00000448UL])))
#define DTCR1_CAP0_BITMASK            (0x1U)
#define DTCR1_CAP1_BITMASK            (0x2U)
#define DTCR1_CAP2_BITMASK            (0x4U)
#define DTCR1_CAP3_BITMASK            (0x8U)
#define DTCR1_CAP4_BITMASK            (0x10U)
#define DTCR1_CAP5_BITMASK            (0x20U)
#define DTCR1_CAP6_BITMASK            (0x40U)
#define DTCR1_CAP7_BITMASK            (0x80U)
#define DTCR1_CAP8_BITMASK            (0x100U)
#define DTCR1_CAP9_BITMASK            (0x200U)
#define DTCR1_CAP10_BITMASK           (0x400U)
#define DTCR1_CAP11_BITMASK           (0x800U)
#define DTCR1_CAP12_BITMASK           (0x1000U)
#define DTCR1_CAP13_BITMASK           (0x2000U)
#define DTCR1_CAP14_BITMASK           (0x4000U)
#define DTCR1_CAP15_BITMASK           (0x8000U)
#define DTCR1_CAP16_BITMASK           (0x10000U)
#define DTCR1_CAP17_BITMASK           (0x20000U)
#define DTCR1_CAP18_BITMASK           (0x40000U)
#define DTCR1_CAP19_BITMASK           (0x80000U)
#define DTCR1_CAP20_BITMASK           (0x100000U)
#define DTCR1_CAP21_BITMASK           (0x200000U)
#define DTCR1_CAP22_BITMASK           (0x400000U)
#define DTCR1_CAP23_BITMASK           (0x800000U)
#define DTCR1_CAP24_BITMASK           (0x1000000U)
#define DTCR1_CAP25_BITMASK           (0x2000000U)
#define DTCR1_CAP26_BITMASK           (0x4000000U)
#define DTCR1_CAP27_BITMASK           (0x8000000U)
#define DTCR1_CAP28_BITMASK           (0x10000000U)
#define DTCR1_CAP29_BITMASK           (0x20000000U)
#define DTCR1_CAP30_BITMASK           (0x40000000U)
#define DTCR1_CAP31_BITMASK           (0x80000000U)
#define DTCR1_CAP_GRPMASK             (0xFFFFFFFFU)
#define DTCR1_CAP_GRPPOS              (0U)

/*** DTCN1 - DMA Timer 1 Counter.; 0x0000044C ***/
#define DTCN1                         (*((volatile uint32 *)(&__IPSBAR[0x0000044CUL])))
#define DTCN1_CNT0_BITMASK            (0x1U)
#define DTCN1_CNT1_BITMASK            (0x2U)
#define DTCN1_CNT2_BITMASK            (0x4U)
#define DTCN1_CNT3_BITMASK            (0x8U)
#define DTCN1_CNT4_BITMASK            (0x10U)
#define DTCN1_CNT5_BITMASK            (0x20U)
#define DTCN1_CNT6_BITMASK            (0x40U)
#define DTCN1_CNT7_BITMASK            (0x80U)
#define DTCN1_CNT8_BITMASK            (0x100U)
#define DTCN1_CNT9_BITMASK            (0x200U)
#define DTCN1_CNT10_BITMASK           (0x400U)
#define DTCN1_CNT11_BITMASK           (0x800U)
#define DTCN1_CNT12_BITMASK           (0x1000U)
#define DTCN1_CNT13_BITMASK           (0x2000U)
#define DTCN1_CNT14_BITMASK           (0x4000U)
#define DTCN1_CNT15_BITMASK           (0x8000U)
#define DTCN1_CNT16_BITMASK           (0x10000U)
#define DTCN1_CNT17_BITMASK           (0x20000U)
#define DTCN1_CNT18_BITMASK           (0x40000U)
#define DTCN1_CNT19_BITMASK           (0x80000U)
#define DTCN1_CNT20_BITMASK           (0x100000U)
#define DTCN1_CNT21_BITMASK           (0x200000U)
#define DTCN1_CNT22_BITMASK           (0x400000U)
#define DTCN1_CNT23_BITMASK           (0x800000U)
#define DTCN1_CNT24_BITMASK           (0x1000000U)
#define DTCN1_CNT25_BITMASK           (0x2000000U)
#define DTCN1_CNT26_BITMASK           (0x4000000U)
#define DTCN1_CNT27_BITMASK           (0x8000000U)
#define DTCN1_CNT28_BITMASK           (0x10000000U)
#define DTCN1_CNT29_BITMASK           (0x20000000U)
#define DTCN1_CNT30_BITMASK           (0x40000000U)
#define DTCN1_CNT31_BITMASK           (0x80000000U)
#define DTCN1_CNT_GRPMASK             (0xFFFFFFFFU)
#define DTCN1_CNT_GRPPOS              (0U)


/******************************************
*** Peripheral DTIM2
*******************************************/

/*** DTMR2 - DMA Timer 2 Mode Register.; 0x00000480 ***/
#define DTMR2                         (*((volatile uint16 *)(&__IPSBAR[0x00000480UL])))
#define DTMR2_RST_BITMASK             (0x1U)
#define DTMR2_CLK0_BITMASK            (0x2U)
#define DTMR2_CLK1_BITMASK            (0x4U)
#define DTMR2_FRR_BITMASK             (0x8U)
#define DTMR2_ORRI_BITMASK            (0x10U)
#define DTMR2_OM_BITMASK              (0x20U)
#define DTMR2_CE0_BITMASK             (0x40U)
#define DTMR2_CE1_BITMASK             (0x80U)
#define DTMR2_PS0_BITMASK             (0x100U)
#define DTMR2_PS1_BITMASK             (0x200U)
#define DTMR2_PS2_BITMASK             (0x400U)
#define DTMR2_PS3_BITMASK             (0x800U)
#define DTMR2_PS4_BITMASK             (0x1000U)
#define DTMR2_PS5_BITMASK             (0x2000U)
#define DTMR2_PS6_BITMASK             (0x4000U)
#define DTMR2_PS7_BITMASK             (0x8000U)
#define DTMR2_CLK_GRPMASK             (0x6U)
#define DTMR2_CLK_GRPPOS              (0x1U)
#define DTMR2_CE_GRPMASK              (0xC0U)
#define DTMR2_CE_GRPPOS               (0x6U)
#define DTMR2_PS_GRPMASK              (0xFF00U)
#define DTMR2_PS_GRPPOS               (0x8U)

/*** DTXMR2 - DMA Timer 2  Extended Mode Register.; 0x00000482 ***/
#define DTXMR2                        (*((volatile uint8 *)(&__IPSBAR[0x00000482UL])))
#define DTXMR2_MODE16_BITMASK         (0x1U)
#define DTXMR2_HALTED_BITMASK         (0x40U)
#define DTXMR2_DMAEN_BITMASK          (0x80U)

/*** DTER2 - DMA Timer 2 Event Register.; 0x00000483 ***/
#define DTER2                         (*((volatile uint8 *)(&__IPSBAR[0x00000483UL])))
#define DTER2_CAP_BITMASK             (0x1U)
#define DTER2_REF_BITMASK             (0x2U)

/*** DTRR2 - DMA Timer 2 Reference Register.; 0x00000484 ***/
#define DTRR2                         (*((volatile uint32 *)(&__IPSBAR[0x00000484UL])))
#define DTRR2_REF0_BITMASK            (0x1U)
#define DTRR2_REF1_BITMASK            (0x2U)
#define DTRR2_REF2_BITMASK            (0x4U)
#define DTRR2_REF3_BITMASK            (0x8U)
#define DTRR2_REF4_BITMASK            (0x10U)
#define DTRR2_REF5_BITMASK            (0x20U)
#define DTRR2_REF6_BITMASK            (0x40U)
#define DTRR2_REF7_BITMASK            (0x80U)
#define DTRR2_REF8_BITMASK            (0x100U)
#define DTRR2_REF9_BITMASK            (0x200U)
#define DTRR2_REF10_BITMASK           (0x400U)
#define DTRR2_REF11_BITMASK           (0x800U)
#define DTRR2_REF12_BITMASK           (0x1000U)
#define DTRR2_REF13_BITMASK           (0x2000U)
#define DTRR2_REF14_BITMASK           (0x4000U)
#define DTRR2_REF15_BITMASK           (0x8000U)
#define DTRR2_REF16_BITMASK           (0x10000U)
#define DTRR2_REF17_BITMASK           (0x20000U)
#define DTRR2_REF18_BITMASK           (0x40000U)
#define DTRR2_REF19_BITMASK           (0x80000U)
#define DTRR2_REF20_BITMASK           (0x100000U)
#define DTRR2_REF21_BITMASK           (0x200000U)
#define DTRR2_REF22_BITMASK           (0x400000U)
#define DTRR2_REF23_BITMASK           (0x800000U)
#define DTRR2_REF24_BITMASK           (0x1000000U)
#define DTRR2_REF25_BITMASK           (0x2000000U)
#define DTRR2_REF26_BITMASK           (0x4000000U)
#define DTRR2_REF27_BITMASK           (0x8000000U)
#define DTRR2_REF28_BITMASK           (0x10000000U)
#define DTRR2_REF29_BITMASK           (0x20000000U)
#define DTRR2_REF30_BITMASK           (0x40000000U)
#define DTRR2_REF31_BITMASK           (0x80000000U)
#define DTRR2_REF_GRPMASK             (0xFFFFFFFFU)
#define DTRR2_REF_GRPPOS              (0U)

/*** DTCR2 - DMA Timer 2 Capture Register.; 0x00000488 ***/
#define DTCR2                         (*((volatile uint32 *)(&__IPSBAR[0x00000488UL])))
#define DTCR2_CAP0_BITMASK            (0x1U)
#define DTCR2_CAP1_BITMASK            (0x2U)
#define DTCR2_CAP2_BITMASK            (0x4U)
#define DTCR2_CAP3_BITMASK            (0x8U)
#define DTCR2_CAP4_BITMASK            (0x10U)
#define DTCR2_CAP5_BITMASK            (0x20U)
#define DTCR2_CAP6_BITMASK            (0x40U)
#define DTCR2_CAP7_BITMASK            (0x80U)
#define DTCR2_CAP8_BITMASK            (0x100U)
#define DTCR2_CAP9_BITMASK            (0x200U)
#define DTCR2_CAP10_BITMASK           (0x400U)
#define DTCR2_CAP11_BITMASK           (0x800U)
#define DTCR2_CAP12_BITMASK           (0x1000U)
#define DTCR2_CAP13_BITMASK           (0x2000U)
#define DTCR2_CAP14_BITMASK           (0x4000U)
#define DTCR2_CAP15_BITMASK           (0x8000U)
#define DTCR2_CAP16_BITMASK           (0x10000U)
#define DTCR2_CAP17_BITMASK           (0x20000U)
#define DTCR2_CAP18_BITMASK           (0x40000U)
#define DTCR2_CAP19_BITMASK           (0x80000U)
#define DTCR2_CAP20_BITMASK           (0x100000U)
#define DTCR2_CAP21_BITMASK           (0x200000U)
#define DTCR2_CAP22_BITMASK           (0x400000U)
#define DTCR2_CAP23_BITMASK           (0x800000U)
#define DTCR2_CAP24_BITMASK           (0x1000000U)
#define DTCR2_CAP25_BITMASK           (0x2000000U)
#define DTCR2_CAP26_BITMASK           (0x4000000U)
#define DTCR2_CAP27_BITMASK           (0x8000000U)
#define DTCR2_CAP28_BITMASK           (0x10000000U)
#define DTCR2_CAP29_BITMASK           (0x20000000U)
#define DTCR2_CAP30_BITMASK           (0x40000000U)
#define DTCR2_CAP31_BITMASK           (0x80000000U)
#define DTCR2_CAP_GRPMASK             (0xFFFFFFFFU)
#define DTCR2_CAP_GRPPOS              (0U)

/*** DTCN2 - DMA Timer 2 Counter.; 0x0000048C ***/
#define DTCN2                         (*((volatile uint32 *)(&__IPSBAR[0x0000048CUL])))
#define DTCN2_CNT0_BITMASK            (0x1U)
#define DTCN2_CNT1_BITMASK            (0x2U)
#define DTCN2_CNT2_BITMASK            (0x4U)
#define DTCN2_CNT3_BITMASK            (0x8U)
#define DTCN2_CNT4_BITMASK            (0x10U)
#define DTCN2_CNT5_BITMASK            (0x20U)
#define DTCN2_CNT6_BITMASK            (0x40U)
#define DTCN2_CNT7_BITMASK            (0x80U)
#define DTCN2_CNT8_BITMASK            (0x100U)
#define DTCN2_CNT9_BITMASK            (0x200U)
#define DTCN2_CNT10_BITMASK           (0x400U)
#define DTCN2_CNT11_BITMASK           (0x800U)
#define DTCN2_CNT12_BITMASK           (0x1000U)
#define DTCN2_CNT13_BITMASK           (0x2000U)
#define DTCN2_CNT14_BITMASK           (0x4000U)
#define DTCN2_CNT15_BITMASK           (0x8000U)
#define DTCN2_CNT16_BITMASK           (0x10000U)
#define DTCN2_CNT17_BITMASK           (0x20000U)
#define DTCN2_CNT18_BITMASK           (0x40000U)
#define DTCN2_CNT19_BITMASK           (0x80000U)
#define DTCN2_CNT20_BITMASK           (0x100000U)
#define DTCN2_CNT21_BITMASK           (0x200000U)
#define DTCN2_CNT22_BITMASK           (0x400000U)
#define DTCN2_CNT23_BITMASK           (0x800000U)
#define DTCN2_CNT24_BITMASK           (0x1000000U)
#define DTCN2_CNT25_BITMASK           (0x2000000U)
#define DTCN2_CNT26_BITMASK           (0x4000000U)
#define DTCN2_CNT27_BITMASK           (0x8000000U)
#define DTCN2_CNT28_BITMASK           (0x10000000U)
#define DTCN2_CNT29_BITMASK           (0x20000000U)
#define DTCN2_CNT30_BITMASK           (0x40000000U)
#define DTCN2_CNT31_BITMASK           (0x80000000U)
#define DTCN2_CNT_GRPMASK             (0xFFFFFFFFU)
#define DTCN2_CNT_GRPPOS              (0U)


/******************************************
*** Peripheral DTIM3
*******************************************/

/*** DTMR3 - DMA Timer 3 Mode Register.; 0x000004C0 ***/
#define DTMR3                         (*((volatile uint16 *)(&__IPSBAR[0x000004C0UL])))
#define DTMR3_RST_BITMASK             (0x1U)
#define DTMR3_CLK0_BITMASK            (0x2U)
#define DTMR3_CLK1_BITMASK            (0x4U)
#define DTMR3_FRR_BITMASK             (0x8U)
#define DTMR3_ORRI_BITMASK            (0x10U)
#define DTMR3_OM_BITMASK              (0x20U)
#define DTMR3_CE0_BITMASK             (0x40U)
#define DTMR3_CE1_BITMASK             (0x80U)
#define DTMR3_PS0_BITMASK             (0x100U)
#define DTMR3_PS1_BITMASK             (0x200U)
#define DTMR3_PS2_BITMASK             (0x400U)
#define DTMR3_PS3_BITMASK             (0x800U)
#define DTMR3_PS4_BITMASK             (0x1000U)
#define DTMR3_PS5_BITMASK             (0x2000U)
#define DTMR3_PS6_BITMASK             (0x4000U)
#define DTMR3_PS7_BITMASK             (0x8000U)
#define DTMR3_CLK_GRPMASK             (0x6U)
#define DTMR3_CLK_GRPPOS              (0x1U)
#define DTMR3_CE_GRPMASK              (0xC0U)
#define DTMR3_CE_GRPPOS               (0x6U)
#define DTMR3_PS_GRPMASK              (0xFF00U)
#define DTMR3_PS_GRPPOS               (0x8U)

/*** DTXMR3 - DMA Timer 3  Extended Mode Register.; 0x000004C2 ***/
#define DTXMR3                        (*((volatile uint8 *)(&__IPSBAR[0x000004C2UL])))
#define DTXMR3_MODE16_BITMASK         (0x1U)
#define DTXMR3_HALTED_BITMASK         (0x40U)
#define DTXMR3_DMAEN_BITMASK          (0x80U)

/*** DTER3 - DMA Timer 3 Event Register.; 0x000004C3 ***/
#define DTER3                         (*((volatile uint8 *)(&__IPSBAR[0x000004C3UL])))
#define DTER3_CAP_BITMASK             (0x1U)
#define DTER3_REF_BITMASK             (0x2U)

/*** DTRR3 - DMA Timer 3 Reference Register.; 0x000004C4 ***/
#define DTRR3                         (*((volatile uint32 *)(&__IPSBAR[0x000004C4UL])))
#define DTRR3_REF0_BITMASK            (0x1U)
#define DTRR3_REF1_BITMASK            (0x2U)
#define DTRR3_REF2_BITMASK            (0x4U)
#define DTRR3_REF3_BITMASK            (0x8U)
#define DTRR3_REF4_BITMASK            (0x10U)
#define DTRR3_REF5_BITMASK            (0x20U)
#define DTRR3_REF6_BITMASK            (0x40U)
#define DTRR3_REF7_BITMASK            (0x80U)
#define DTRR3_REF8_BITMASK            (0x100U)
#define DTRR3_REF9_BITMASK            (0x200U)
#define DTRR3_REF10_BITMASK           (0x400U)
#define DTRR3_REF11_BITMASK           (0x800U)
#define DTRR3_REF12_BITMASK           (0x1000U)
#define DTRR3_REF13_BITMASK           (0x2000U)
#define DTRR3_REF14_BITMASK           (0x4000U)
#define DTRR3_REF15_BITMASK           (0x8000U)
#define DTRR3_REF16_BITMASK           (0x10000U)
#define DTRR3_REF17_BITMASK           (0x20000U)
#define DTRR3_REF18_BITMASK           (0x40000U)
#define DTRR3_REF19_BITMASK           (0x80000U)
#define DTRR3_REF20_BITMASK           (0x100000U)
#define DTRR3_REF21_BITMASK           (0x200000U)
#define DTRR3_REF22_BITMASK           (0x400000U)
#define DTRR3_REF23_BITMASK           (0x800000U)
#define DTRR3_REF24_BITMASK           (0x1000000U)
#define DTRR3_REF25_BITMASK           (0x2000000U)
#define DTRR3_REF26_BITMASK           (0x4000000U)
#define DTRR3_REF27_BITMASK           (0x8000000U)
#define DTRR3_REF28_BITMASK           (0x10000000U)
#define DTRR3_REF29_BITMASK           (0x20000000U)
#define DTRR3_REF30_BITMASK           (0x40000000U)
#define DTRR3_REF31_BITMASK           (0x80000000U)
#define DTRR3_REF_GRPMASK             (0xFFFFFFFFU)
#define DTRR3_REF_GRPPOS              (0U)

/*** DTCR3 - DMA Timer 3 Capture Register.; 0x000004C8 ***/
#define DTCR3                         (*((volatile uint32 *)(&__IPSBAR[0x000004C8UL])))
#define DTCR3_CAP0_BITMASK            (0x1U)
#define DTCR3_CAP1_BITMASK            (0x2U)
#define DTCR3_CAP2_BITMASK            (0x4U)
#define DTCR3_CAP3_BITMASK            (0x8U)
#define DTCR3_CAP4_BITMASK            (0x10U)
#define DTCR3_CAP5_BITMASK            (0x20U)
#define DTCR3_CAP6_BITMASK            (0x40U)
#define DTCR3_CAP7_BITMASK            (0x80U)
#define DTCR3_CAP8_BITMASK            (0x100U)
#define DTCR3_CAP9_BITMASK            (0x200U)
#define DTCR3_CAP10_BITMASK           (0x400U)
#define DTCR3_CAP11_BITMASK           (0x800U)
#define DTCR3_CAP12_BITMASK           (0x1000U)
#define DTCR3_CAP13_BITMASK           (0x2000U)
#define DTCR3_CAP14_BITMASK           (0x4000U)
#define DTCR3_CAP15_BITMASK           (0x8000U)
#define DTCR3_CAP16_BITMASK           (0x10000U)
#define DTCR3_CAP17_BITMASK           (0x20000U)
#define DTCR3_CAP18_BITMASK           (0x40000U)
#define DTCR3_CAP19_BITMASK           (0x80000U)
#define DTCR3_CAP20_BITMASK           (0x100000U)
#define DTCR3_CAP21_BITMASK           (0x200000U)
#define DTCR3_CAP22_BITMASK           (0x400000U)
#define DTCR3_CAP23_BITMASK           (0x800000U)
#define DTCR3_CAP24_BITMASK           (0x1000000U)
#define DTCR3_CAP25_BITMASK           (0x2000000U)
#define DTCR3_CAP26_BITMASK           (0x4000000U)
#define DTCR3_CAP27_BITMASK           (0x8000000U)
#define DTCR3_CAP28_BITMASK           (0x10000000U)
#define DTCR3_CAP29_BITMASK           (0x20000000U)
#define DTCR3_CAP30_BITMASK           (0x40000000U)
#define DTCR3_CAP31_BITMASK           (0x80000000U)
#define DTCR3_CAP_GRPMASK             (0xFFFFFFFFU)
#define DTCR3_CAP_GRPPOS              (0U)

/*** DTCN3 - DMA Timer 3 Counter.; 0x000004CC ***/
#define DTCN3                         (*((volatile uint32 *)(&__IPSBAR[0x000004CCUL])))
#define DTCN3_CNT0_BITMASK            (0x1U)
#define DTCN3_CNT1_BITMASK            (0x2U)
#define DTCN3_CNT2_BITMASK            (0x4U)
#define DTCN3_CNT3_BITMASK            (0x8U)
#define DTCN3_CNT4_BITMASK            (0x10U)
#define DTCN3_CNT5_BITMASK            (0x20U)
#define DTCN3_CNT6_BITMASK            (0x40U)
#define DTCN3_CNT7_BITMASK            (0x80U)
#define DTCN3_CNT8_BITMASK            (0x100U)
#define DTCN3_CNT9_BITMASK            (0x200U)
#define DTCN3_CNT10_BITMASK           (0x400U)
#define DTCN3_CNT11_BITMASK           (0x800U)
#define DTCN3_CNT12_BITMASK           (0x1000U)
#define DTCN3_CNT13_BITMASK           (0x2000U)
#define DTCN3_CNT14_BITMASK           (0x4000U)
#define DTCN3_CNT15_BITMASK           (0x8000U)
#define DTCN3_CNT16_BITMASK           (0x10000U)
#define DTCN3_CNT17_BITMASK           (0x20000U)
#define DTCN3_CNT18_BITMASK           (0x40000U)
#define DTCN3_CNT19_BITMASK           (0x80000U)
#define DTCN3_CNT20_BITMASK           (0x100000U)
#define DTCN3_CNT21_BITMASK           (0x200000U)
#define DTCN3_CNT22_BITMASK           (0x400000U)
#define DTCN3_CNT23_BITMASK           (0x800000U)
#define DTCN3_CNT24_BITMASK           (0x1000000U)
#define DTCN3_CNT25_BITMASK           (0x2000000U)
#define DTCN3_CNT26_BITMASK           (0x4000000U)
#define DTCN3_CNT27_BITMASK           (0x8000000U)
#define DTCN3_CNT28_BITMASK           (0x10000000U)
#define DTCN3_CNT29_BITMASK           (0x20000000U)
#define DTCN3_CNT30_BITMASK           (0x40000000U)
#define DTCN3_CNT31_BITMASK           (0x80000000U)
#define DTCN3_CNT_GRPMASK             (0xFFFFFFFFU)
#define DTCN3_CNT_GRPPOS              (0U)


/******************************************
*** Peripheral INTC0
*******************************************/

/*** IPRH0 - Interrupt Pending Register High.; 0x00000C00 ***/
#define IPRH0                         (*((volatile uint32 *)(&__IPSBAR[0x00000C00UL])))
#define IPRH0_INT32_BITMASK           (0x1U)
#define IPRH0_INT33_BITMASK           (0x2U)
#define IPRH0_INT34_BITMASK           (0x4U)
#define IPRH0_INT35_BITMASK           (0x8U)
#define IPRH0_INT36_BITMASK           (0x10U)
#define IPRH0_INT37_BITMASK           (0x20U)
#define IPRH0_INT38_BITMASK           (0x40U)
#define IPRH0_INT39_BITMASK           (0x80U)
#define IPRH0_INT40_BITMASK           (0x100U)
#define IPRH0_INT41_BITMASK           (0x200U)
#define IPRH0_INT42_BITMASK           (0x400U)
#define IPRH0_INT43_BITMASK           (0x800U)
#define IPRH0_INT44_BITMASK           (0x1000U)
#define IPRH0_INT45_BITMASK           (0x2000U)
#define IPRH0_INT46_BITMASK           (0x4000U)
#define IPRH0_INT47_BITMASK           (0x8000U)
#define IPRH0_INT48_BITMASK           (0x10000U)
#define IPRH0_INT49_BITMASK           (0x20000U)
#define IPRH0_INT50_BITMASK           (0x40000U)
#define IPRH0_INT51_BITMASK           (0x80000U)
#define IPRH0_INT52_BITMASK           (0x100000U)
#define IPRH0_INT53_BITMASK           (0x200000U)
#define IPRH0_INT54_BITMASK           (0x400000U)
#define IPRH0_INT55_BITMASK           (0x800000U)
#define IPRH0_INT56_BITMASK           (0x1000000U)
#define IPRH0_INT57_BITMASK           (0x2000000U)
#define IPRH0_INT58_BITMASK           (0x4000000U)
#define IPRH0_INT59_BITMASK           (0x8000000U)
#define IPRH0_INT60_BITMASK           (0x10000000U)
#define IPRH0_INT61_BITMASK           (0x20000000U)
#define IPRH0_INT62_BITMASK           (0x40000000U)
#define IPRH0_INT63_BITMASK           (0x80000000U)

/*** IPRL0 - Interrupt Pending Register Low.; 0x00000C04 ***/
#define IPRL0                         (*((volatile uint32 *)(&__IPSBAR[0x00000C04UL])))
#define IPRL0_INT1_BITMASK            (0x2U)
#define IPRL0_INT2_BITMASK            (0x4U)
#define IPRL0_INT3_BITMASK            (0x8U)
#define IPRL0_INT4_BITMASK            (0x10U)
#define IPRL0_INT5_BITMASK            (0x20U)
#define IPRL0_INT6_BITMASK            (0x40U)
#define IPRL0_INT7_BITMASK            (0x80U)
#define IPRL0_INT8_BITMASK            (0x100U)
#define IPRL0_INT9_BITMASK            (0x200U)
#define IPRL0_INT10_BITMASK           (0x400U)
#define IPRL0_INT11_BITMASK           (0x800U)
#define IPRL0_INT12_BITMASK           (0x1000U)
#define IPRL0_INT13_BITMASK           (0x2000U)
#define IPRL0_INT14_BITMASK           (0x4000U)
#define IPRL0_INT15_BITMASK           (0x8000U)
#define IPRL0_INT16_BITMASK           (0x10000U)
#define IPRL0_INT17_BITMASK           (0x20000U)
#define IPRL0_INT18_BITMASK           (0x40000U)
#define IPRL0_INT19_BITMASK           (0x80000U)
#define IPRL0_INT20_BITMASK           (0x100000U)
#define IPRL0_INT21_BITMASK           (0x200000U)
#define IPRL0_INT22_BITMASK           (0x400000U)
#define IPRL0_INT23_BITMASK           (0x800000U)
#define IPRL0_INT24_BITMASK           (0x1000000U)
#define IPRL0_INT25_BITMASK           (0x2000000U)
#define IPRL0_INT26_BITMASK           (0x4000000U)
#define IPRL0_INT27_BITMASK           (0x8000000U)
#define IPRL0_INT28_BITMASK           (0x10000000U)
#define IPRL0_INT29_BITMASK           (0x20000000U)
#define IPRL0_INT30_BITMASK           (0x40000000U)
#define IPRL0_INT31_BITMASK           (0x80000000U)

/*** IMRH0 - Interrupt Mask Register High.; 0x00000C08 ***/
#define IMRH0                         (*((volatile uint32 *)(&__IPSBAR[0x00000C08UL])))
#define IMRH0_INT_MASK32_BITMASK      (0x1U)
#define IMRH0_INT_MASK33_BITMASK      (0x2U)
#define IMRH0_INT_MASK34_BITMASK      (0x4U)
#define IMRH0_INT_MASK35_BITMASK      (0x8U)
#define IMRH0_INT_MASK36_BITMASK      (0x10U)
#define IMRH0_INT_MASK37_BITMASK      (0x20U)
#define IMRH0_INT_MASK38_BITMASK      (0x40U)
#define IMRH0_INT_MASK39_BITMASK      (0x80U)
#define IMRH0_INT_MASK40_BITMASK      (0x100U)
#define IMRH0_INT_MASK41_BITMASK      (0x200U)
#define IMRH0_INT_MASK42_BITMASK      (0x400U)
#define IMRH0_INT_MASK43_BITMASK      (0x800U)
#define IMRH0_INT_MASK44_BITMASK      (0x1000U)
#define IMRH0_INT_MASK45_BITMASK      (0x2000U)
#define IMRH0_INT_MASK46_BITMASK      (0x4000U)
#define IMRH0_INT_MASK47_BITMASK      (0x8000U)
#define IMRH0_INT_MASK48_BITMASK      (0x10000U)
#define IMRH0_INT_MASK49_BITMASK      (0x20000U)
#define IMRH0_INT_MASK50_BITMASK      (0x40000U)
#define IMRH0_INT_MASK51_BITMASK      (0x80000U)
#define IMRH0_INT_MASK52_BITMASK      (0x100000U)
#define IMRH0_INT_MASK53_BITMASK      (0x200000U)
#define IMRH0_INT_MASK54_BITMASK      (0x400000U)
#define IMRH0_INT_MASK55_BITMASK      (0x800000U)
#define IMRH0_INT_MASK56_BITMASK      (0x1000000U)
#define IMRH0_INT_MASK57_BITMASK      (0x2000000U)
#define IMRH0_INT_MASK58_BITMASK      (0x4000000U)
#define IMRH0_INT_MASK59_BITMASK      (0x8000000U)
#define IMRH0_INT_MASK60_BITMASK      (0x10000000U)
#define IMRH0_INT_MASK61_BITMASK      (0x20000000U)
#define IMRH0_INT_MASK62_BITMASK      (0x40000000U)
#define IMRH0_INT_MASK63_BITMASK      (0x80000000U)

/*** IMRL0 - Interrupt Mask Register Low.; 0x00000C0C ***/
#define IMRL0                         (*((volatile uint32 *)(&__IPSBAR[0x00000C0CUL])))
#define IMRL0_MASKALL_BITMASK         (0x1U)
#define IMRL0_INT_MASK1_BITMASK       (0x2U)
#define IMRL0_INT_MASK2_BITMASK       (0x4U)
#define IMRL0_INT_MASK3_BITMASK       (0x8U)
#define IMRL0_INT_MASK4_BITMASK       (0x10U)
#define IMRL0_INT_MASK5_BITMASK       (0x20U)
#define IMRL0_INT_MASK6_BITMASK       (0x40U)
#define IMRL0_INT_MASK7_BITMASK       (0x80U)
#define IMRL0_INT_MASK8_BITMASK       (0x100U)
#define IMRL0_INT_MASK9_BITMASK       (0x200U)
#define IMRL0_INT_MASK10_BITMASK      (0x400U)
#define IMRL0_INT_MASK11_BITMASK      (0x800U)
#define IMRL0_INT_MASK12_BITMASK      (0x1000U)
#define IMRL0_INT_MASK13_BITMASK      (0x2000U)
#define IMRL0_INT_MASK14_BITMASK      (0x4000U)
#define IMRL0_INT_MASK15_BITMASK      (0x8000U)
#define IMRL0_INT_MASK16_BITMASK      (0x10000U)
#define IMRL0_INT_MASK17_BITMASK      (0x20000U)
#define IMRL0_INT_MASK18_BITMASK      (0x40000U)
#define IMRL0_INT_MASK19_BITMASK      (0x80000U)
#define IMRL0_INT_MASK20_BITMASK      (0x100000U)
#define IMRL0_INT_MASK21_BITMASK      (0x200000U)
#define IMRL0_INT_MASK22_BITMASK      (0x400000U)
#define IMRL0_INT_MASK23_BITMASK      (0x800000U)
#define IMRL0_INT_MASK24_BITMASK      (0x1000000U)
#define IMRL0_INT_MASK25_BITMASK      (0x2000000U)
#define IMRL0_INT_MASK26_BITMASK      (0x4000000U)
#define IMRL0_INT_MASK27_BITMASK      (0x8000000U)
#define IMRL0_INT_MASK28_BITMASK      (0x10000000U)
#define IMRL0_INT_MASK29_BITMASK      (0x20000000U)
#define IMRL0_INT_MASK30_BITMASK      (0x40000000U)
#define IMRL0_INT_MASK31_BITMASK      (0x80000000U)

/*** INTFRCH0 - Interrupt Force Register High.; 0x00000C10 ***/
#define INTFRCH0                      (*((volatile uint32 *)(&__IPSBAR[0x00000C10UL])))
#define INTFRCH0_INTFRC32_BITMASK     (0x1U)
#define INTFRCH0_INTFRC33_BITMASK     (0x2U)
#define INTFRCH0_INTFRC34_BITMASK     (0x4U)
#define INTFRCH0_INTFRC35_BITMASK     (0x8U)
#define INTFRCH0_INTFRC36_BITMASK     (0x10U)
#define INTFRCH0_INTFRC37_BITMASK     (0x20U)
#define INTFRCH0_INTFRC38_BITMASK     (0x40U)
#define INTFRCH0_INTFRC39_BITMASK     (0x80U)
#define INTFRCH0_INTFRC40_BITMASK     (0x100U)
#define INTFRCH0_INTFRC41_BITMASK     (0x200U)
#define INTFRCH0_INTFRC42_BITMASK     (0x400U)
#define INTFRCH0_INTFRC43_BITMASK     (0x800U)
#define INTFRCH0_INTFRC44_BITMASK     (0x1000U)
#define INTFRCH0_INTFRC45_BITMASK     (0x2000U)
#define INTFRCH0_INTFRC46_BITMASK     (0x4000U)
#define INTFRCH0_INTFRC47_BITMASK     (0x8000U)
#define INTFRCH0_INTFRC48_BITMASK     (0x10000U)
#define INTFRCH0_INTFRC49_BITMASK     (0x20000U)
#define INTFRCH0_INTFRC50_BITMASK     (0x40000U)
#define INTFRCH0_INTFRC51_BITMASK     (0x80000U)
#define INTFRCH0_INTFRC52_BITMASK     (0x100000U)
#define INTFRCH0_INTFRC53_BITMASK     (0x200000U)
#define INTFRCH0_INTFRC54_BITMASK     (0x400000U)
#define INTFRCH0_INTFRC55_BITMASK     (0x800000U)
#define INTFRCH0_INTFRC56_BITMASK     (0x1000000U)
#define INTFRCH0_INTFRC57_BITMASK     (0x2000000U)
#define INTFRCH0_INTFRC58_BITMASK     (0x4000000U)
#define INTFRCH0_INTFRC59_BITMASK     (0x8000000U)
#define INTFRCH0_INTFRC60_BITMASK     (0x10000000U)
#define INTFRCH0_INTFRC61_BITMASK     (0x20000000U)
#define INTFRCH0_INTFRC62_BITMASK     (0x40000000U)
#define INTFRCH0_INTFRC63_BITMASK     (0x80000000U)

/*** INTFRCL0 - Interrupt Force Register Low.; 0x00000C14 ***/
#define INTFRCL0                      (*((volatile uint32 *)(&__IPSBAR[0x00000C14UL])))
#define INTFRCL0_INTFRC1_BITMASK      (0x2U)
#define INTFRCL0_INTFRC2_BITMASK      (0x4U)
#define INTFRCL0_INTFRC3_BITMASK      (0x8U)
#define INTFRCL0_INTFRC4_BITMASK      (0x10U)
#define INTFRCL0_INTFRC5_BITMASK      (0x20U)
#define INTFRCL0_INTFRC6_BITMASK      (0x40U)
#define INTFRCL0_INTFRC7_BITMASK      (0x80U)
#define INTFRCL0_INTFRC8_BITMASK      (0x100U)
#define INTFRCL0_INTFRC9_BITMASK      (0x200U)
#define INTFRCL0_INTFRC10_BITMASK     (0x400U)
#define INTFRCL0_INTFRC11_BITMASK     (0x800U)
#define INTFRCL0_INTFRC12_BITMASK     (0x1000U)
#define INTFRCL0_INTFRC13_BITMASK     (0x2000U)
#define INTFRCL0_INTFRC14_BITMASK     (0x4000U)
#define INTFRCL0_INTFRC15_BITMASK     (0x8000U)
#define INTFRCL0_INTFRC16_BITMASK     (0x10000U)
#define INTFRCL0_INTFRC17_BITMASK     (0x20000U)
#define INTFRCL0_INTFRC18_BITMASK     (0x40000U)
#define INTFRCL0_INTFRC19_BITMASK     (0x80000U)
#define INTFRCL0_INTFRC20_BITMASK     (0x100000U)
#define INTFRCL0_INTFRC21_BITMASK     (0x200000U)
#define INTFRCL0_INTFRC22_BITMASK     (0x400000U)
#define INTFRCL0_INTFRC23_BITMASK     (0x800000U)
#define INTFRCL0_INTFRC24_BITMASK     (0x1000000U)
#define INTFRCL0_INTFRC25_BITMASK     (0x2000000U)
#define INTFRCL0_INTFRC26_BITMASK     (0x4000000U)
#define INTFRCL0_INTFRC27_BITMASK     (0x8000000U)
#define INTFRCL0_INTFRC28_BITMASK     (0x10000000U)
#define INTFRCL0_INTFRC29_BITMASK     (0x20000000U)
#define INTFRCL0_INTFRC30_BITMASK     (0x40000000U)
#define INTFRCL0_INTFRC31_BITMASK     (0x80000000U)

/*** IRLR0 - Interrupt Request Level Register.; 0x00000C18 ***/
#define IRLR0                         (*((volatile uint8 *)(&__IPSBAR[0x00000C18UL])))
#define IRLR0_IRQ1_BITMASK            (0x2U)
#define IRLR0_IRQ2_BITMASK            (0x4U)
#define IRLR0_IRQ3_BITMASK            (0x8U)
#define IRLR0_IRQ4_BITMASK            (0x10U)
#define IRLR0_IRQ5_BITMASK            (0x20U)
#define IRLR0_IRQ6_BITMASK            (0x40U)
#define IRLR0_IRQ7_BITMASK            (0x80U)
#define IRLR0_IRQ_GRPMASK             (0xFEU)
#define IRLR0_IRQ_GRPPOS              (0x1U)

/*** IACKLPR0 - Interrupt Acknowledge Level and Priority Register.; 0x00000C19 ***/
#define IACKLPR0                      (*((volatile uint8 *)(&__IPSBAR[0x00000C19UL])))
#define IACKLPR0_PRI0_BITMASK         (0x1U)
#define IACKLPR0_PRI1_BITMASK         (0x2U)
#define IACKLPR0_PRI2_BITMASK         (0x4U)
#define IACKLPR0_PRI3_BITMASK         (0x8U)
#define IACKLPR0_LEVEL0_BITMASK       (0x10U)
#define IACKLPR0_LEVEL1_BITMASK       (0x20U)
#define IACKLPR0_LEVEL2_BITMASK       (0x40U)
#define IACKLPR0_PRI_GRPMASK          (0xFU)
#define IACKLPR0_PRI_GRPPOS           (0U)
#define IACKLPR0_LEVEL_GRPMASK        (0x70U)
#define IACKLPR0_LEVEL_GRPPOS         (0x4U)

/*** ICR001 - Interrupt Control Register 1.; 0x00000C41 ***/
#define ICR001                        (*((volatile uint8 *)(&__IPSBAR[0x00000C41UL])))
#define ICR001_IP0_BITMASK            (0x1U)
#define ICR001_IP1_BITMASK            (0x2U)
#define ICR001_IP2_BITMASK            (0x4U)
#define ICR001_IL0_BITMASK            (0x8U)
#define ICR001_IL1_BITMASK            (0x10U)
#define ICR001_IL2_BITMASK            (0x20U)
#define ICR001_IP_GRPMASK             (0x7U)
#define ICR001_IP_GRPPOS              (0U)
#define ICR001_IL_GRPMASK             (0x38U)
#define ICR001_IL_GRPPOS              (0x3U)

/*** ICR002 - Interrupt Control Register 2.; 0x00000C42 ***/
#define ICR002                        (*((volatile uint8 *)(&__IPSBAR[0x00000C42UL])))
#define ICR002_IP0_BITMASK            (0x1U)
#define ICR002_IP1_BITMASK            (0x2U)
#define ICR002_IP2_BITMASK            (0x4U)
#define ICR002_IL0_BITMASK            (0x8U)
#define ICR002_IL1_BITMASK            (0x10U)
#define ICR002_IL2_BITMASK            (0x20U)
#define ICR002_IP_GRPMASK             (0x7U)
#define ICR002_IP_GRPPOS              (0U)
#define ICR002_IL_GRPMASK             (0x38U)
#define ICR002_IL_GRPPOS              (0x3U)

/*** ICR003 - Interrupt Control Register 3.; 0x00000C43 ***/
#define ICR003                        (*((volatile uint8 *)(&__IPSBAR[0x00000C43UL])))
#define ICR003_IP0_BITMASK            (0x1U)
#define ICR003_IP1_BITMASK            (0x2U)
#define ICR003_IP2_BITMASK            (0x4U)
#define ICR003_IL0_BITMASK            (0x8U)
#define ICR003_IL1_BITMASK            (0x10U)
#define ICR003_IL2_BITMASK            (0x20U)
#define ICR003_IP_GRPMASK             (0x7U)
#define ICR003_IP_GRPPOS              (0U)
#define ICR003_IL_GRPMASK             (0x38U)
#define ICR003_IL_GRPPOS              (0x3U)

/*** ICR004 - Interrupt Control Register 4.; 0x00000C44 ***/
#define ICR004                        (*((volatile uint8 *)(&__IPSBAR[0x00000C44UL])))
#define ICR004_IP0_BITMASK            (0x1U)
#define ICR004_IP1_BITMASK            (0x2U)
#define ICR004_IP2_BITMASK            (0x4U)
#define ICR004_IL0_BITMASK            (0x8U)
#define ICR004_IL1_BITMASK            (0x10U)
#define ICR004_IL2_BITMASK            (0x20U)
#define ICR004_IP_GRPMASK             (0x7U)
#define ICR004_IP_GRPPOS              (0U)
#define ICR004_IL_GRPMASK             (0x38U)
#define ICR004_IL_GRPPOS              (0x3U)

/*** ICR005 - Interrupt Control Register 5.; 0x00000C45 ***/
#define ICR005                        (*((volatile uint8 *)(&__IPSBAR[0x00000C45UL])))
#define ICR005_IP0_BITMASK            (0x1U)
#define ICR005_IP1_BITMASK            (0x2U)
#define ICR005_IP2_BITMASK            (0x4U)
#define ICR005_IL0_BITMASK            (0x8U)
#define ICR005_IL1_BITMASK            (0x10U)
#define ICR005_IL2_BITMASK            (0x20U)
#define ICR005_IP_GRPMASK             (0x7U)
#define ICR005_IP_GRPPOS              (0U)
#define ICR005_IL_GRPMASK             (0x38U)
#define ICR005_IL_GRPPOS              (0x3U)

/*** ICR006 - Interrupt Control Register 6.; 0x00000C46 ***/
#define ICR006                        (*((volatile uint8 *)(&__IPSBAR[0x00000C46UL])))
#define ICR006_IP0_BITMASK            (0x1U)
#define ICR006_IP1_BITMASK            (0x2U)
#define ICR006_IP2_BITMASK            (0x4U)
#define ICR006_IL0_BITMASK            (0x8U)
#define ICR006_IL1_BITMASK            (0x10U)
#define ICR006_IL2_BITMASK            (0x20U)
#define ICR006_IP_GRPMASK             (0x7U)
#define ICR006_IP_GRPPOS              (0U)
#define ICR006_IL_GRPMASK             (0x38U)
#define ICR006_IL_GRPPOS              (0x3U)

/*** ICR007 - Interrupt Control Register 7.; 0x00000C47 ***/
#define ICR007                        (*((volatile uint8 *)(&__IPSBAR[0x00000C47UL])))
#define ICR007_IP0_BITMASK            (0x1U)
#define ICR007_IP1_BITMASK            (0x2U)
#define ICR007_IP2_BITMASK            (0x4U)
#define ICR007_IL0_BITMASK            (0x8U)
#define ICR007_IL1_BITMASK            (0x10U)
#define ICR007_IL2_BITMASK            (0x20U)
#define ICR007_IP_GRPMASK             (0x7U)
#define ICR007_IP_GRPPOS              (0U)
#define ICR007_IL_GRPMASK             (0x38U)
#define ICR007_IL_GRPPOS              (0x3U)

/*** ICR008 - Interrupt Control Register 8.; 0x00000C48 ***/
#define ICR008                        (*((volatile uint8 *)(&__IPSBAR[0x00000C48UL])))
#define ICR008_IP0_BITMASK            (0x1U)
#define ICR008_IP1_BITMASK            (0x2U)
#define ICR008_IP2_BITMASK            (0x4U)
#define ICR008_IL0_BITMASK            (0x8U)
#define ICR008_IL1_BITMASK            (0x10U)
#define ICR008_IL2_BITMASK            (0x20U)
#define ICR008_IP_GRPMASK             (0x7U)
#define ICR008_IP_GRPPOS              (0U)
#define ICR008_IL_GRPMASK             (0x38U)
#define ICR008_IL_GRPPOS              (0x3U)

/*** ICR009 - Interrupt Control Register 9.; 0x00000C49 ***/
#define ICR009                        (*((volatile uint8 *)(&__IPSBAR[0x00000C49UL])))
#define ICR009_IP0_BITMASK            (0x1U)
#define ICR009_IP1_BITMASK            (0x2U)
#define ICR009_IP2_BITMASK            (0x4U)
#define ICR009_IL0_BITMASK            (0x8U)
#define ICR009_IL1_BITMASK            (0x10U)
#define ICR009_IL2_BITMASK            (0x20U)
#define ICR009_IP_GRPMASK             (0x7U)
#define ICR009_IP_GRPPOS              (0U)
#define ICR009_IL_GRPMASK             (0x38U)
#define ICR009_IL_GRPPOS              (0x3U)

/*** ICR010 - Interrupt Control Register 10.; 0x00000C4A ***/
#define ICR010                        (*((volatile uint8 *)(&__IPSBAR[0x00000C4AUL])))
#define ICR010_IP0_BITMASK            (0x1U)
#define ICR010_IP1_BITMASK            (0x2U)
#define ICR010_IP2_BITMASK            (0x4U)
#define ICR010_IL0_BITMASK            (0x8U)
#define ICR010_IL1_BITMASK            (0x10U)
#define ICR010_IL2_BITMASK            (0x20U)
#define ICR010_IP_GRPMASK             (0x7U)
#define ICR010_IP_GRPPOS              (0U)
#define ICR010_IL_GRPMASK             (0x38U)
#define ICR010_IL_GRPPOS              (0x3U)

/*** ICR011 - Interrupt Control Register 11.; 0x00000C4B ***/
#define ICR011                        (*((volatile uint8 *)(&__IPSBAR[0x00000C4BUL])))
#define ICR011_IP0_BITMASK            (0x1U)
#define ICR011_IP1_BITMASK            (0x2U)
#define ICR011_IP2_BITMASK            (0x4U)
#define ICR011_IL0_BITMASK            (0x8U)
#define ICR011_IL1_BITMASK            (0x10U)
#define ICR011_IL2_BITMASK            (0x20U)
#define ICR011_IP_GRPMASK             (0x7U)
#define ICR011_IP_GRPPOS              (0U)
#define ICR011_IL_GRPMASK             (0x38U)
#define ICR011_IL_GRPPOS              (0x3U)

/*** ICR012 - Interrupt Control Register 12.; 0x00000C4C ***/
#define ICR012                        (*((volatile uint8 *)(&__IPSBAR[0x00000C4CUL])))
#define ICR012_IP0_BITMASK            (0x1U)
#define ICR012_IP1_BITMASK            (0x2U)
#define ICR012_IP2_BITMASK            (0x4U)
#define ICR012_IL0_BITMASK            (0x8U)
#define ICR012_IL1_BITMASK            (0x10U)
#define ICR012_IL2_BITMASK            (0x20U)
#define ICR012_IP_GRPMASK             (0x7U)
#define ICR012_IP_GRPPOS              (0U)
#define ICR012_IL_GRPMASK             (0x38U)
#define ICR012_IL_GRPPOS              (0x3U)

/*** ICR013 - Interrupt Control Register 13.; 0x00000C4D ***/
#define ICR013                        (*((volatile uint8 *)(&__IPSBAR[0x00000C4DUL])))
#define ICR013_IP0_BITMASK            (0x1U)
#define ICR013_IP1_BITMASK            (0x2U)
#define ICR013_IP2_BITMASK            (0x4U)
#define ICR013_IL0_BITMASK            (0x8U)
#define ICR013_IL1_BITMASK            (0x10U)
#define ICR013_IL2_BITMASK            (0x20U)
#define ICR013_IP_GRPMASK             (0x7U)
#define ICR013_IP_GRPPOS              (0U)
#define ICR013_IL_GRPMASK             (0x38U)
#define ICR013_IL_GRPPOS              (0x3U)

/*** ICR014 - Interrupt Control Register 14.; 0x00000C4E ***/
#define ICR014                        (*((volatile uint8 *)(&__IPSBAR[0x00000C4EUL])))
#define ICR014_IP0_BITMASK            (0x1U)
#define ICR014_IP1_BITMASK            (0x2U)
#define ICR014_IP2_BITMASK            (0x4U)
#define ICR014_IL0_BITMASK            (0x8U)
#define ICR014_IL1_BITMASK            (0x10U)
#define ICR014_IL2_BITMASK            (0x20U)
#define ICR014_IP_GRPMASK             (0x7U)
#define ICR014_IP_GRPPOS              (0U)
#define ICR014_IL_GRPMASK             (0x38U)
#define ICR014_IL_GRPPOS              (0x3U)

/*** ICR015 - Interrupt Control Register 15.; 0x00000C4F ***/
#define ICR015                        (*((volatile uint8 *)(&__IPSBAR[0x00000C4FUL])))
#define ICR015_IP0_BITMASK            (0x1U)
#define ICR015_IP1_BITMASK            (0x2U)
#define ICR015_IP2_BITMASK            (0x4U)
#define ICR015_IL0_BITMASK            (0x8U)
#define ICR015_IL1_BITMASK            (0x10U)
#define ICR015_IL2_BITMASK            (0x20U)
#define ICR015_IP_GRPMASK             (0x7U)
#define ICR015_IP_GRPPOS              (0U)
#define ICR015_IL_GRPMASK             (0x38U)
#define ICR015_IL_GRPPOS              (0x3U)

/*** ICR016 - Interrupt Control Register 16.; 0x00000C50 ***/
#define ICR016                        (*((volatile uint8 *)(&__IPSBAR[0x00000C50UL])))
#define ICR016_IP0_BITMASK            (0x1U)
#define ICR016_IP1_BITMASK            (0x2U)
#define ICR016_IP2_BITMASK            (0x4U)
#define ICR016_IL0_BITMASK            (0x8U)
#define ICR016_IL1_BITMASK            (0x10U)
#define ICR016_IL2_BITMASK            (0x20U)
#define ICR016_IP_GRPMASK             (0x7U)
#define ICR016_IP_GRPPOS              (0U)
#define ICR016_IL_GRPMASK             (0x38U)
#define ICR016_IL_GRPPOS              (0x3U)

/*** ICR017 - Interrupt Control Register 17.; 0x00000C51 ***/
#define ICR017                        (*((volatile uint8 *)(&__IPSBAR[0x00000C51UL])))
#define ICR017_IP0_BITMASK            (0x1U)
#define ICR017_IP1_BITMASK            (0x2U)
#define ICR017_IP2_BITMASK            (0x4U)
#define ICR017_IL0_BITMASK            (0x8U)
#define ICR017_IL1_BITMASK            (0x10U)
#define ICR017_IL2_BITMASK            (0x20U)
#define ICR017_IP_GRPMASK             (0x7U)
#define ICR017_IP_GRPPOS              (0U)
#define ICR017_IL_GRPMASK             (0x38U)
#define ICR017_IL_GRPPOS              (0x3U)

/*** ICR018 - Interrupt Control Register 18.; 0x00000C52 ***/
#define ICR018                        (*((volatile uint8 *)(&__IPSBAR[0x00000C52UL])))
#define ICR018_IP0_BITMASK            (0x1U)
#define ICR018_IP1_BITMASK            (0x2U)
#define ICR018_IP2_BITMASK            (0x4U)
#define ICR018_IL0_BITMASK            (0x8U)
#define ICR018_IL1_BITMASK            (0x10U)
#define ICR018_IL2_BITMASK            (0x20U)
#define ICR018_IP_GRPMASK             (0x7U)
#define ICR018_IP_GRPPOS              (0U)
#define ICR018_IL_GRPMASK             (0x38U)
#define ICR018_IL_GRPPOS              (0x3U)

/*** ICR019 - Interrupt Control Register 19.; 0x00000C53 ***/
#define ICR019                        (*((volatile uint8 *)(&__IPSBAR[0x00000C53UL])))
#define ICR019_IP0_BITMASK            (0x1U)
#define ICR019_IP1_BITMASK            (0x2U)
#define ICR019_IP2_BITMASK            (0x4U)
#define ICR019_IL0_BITMASK            (0x8U)
#define ICR019_IL1_BITMASK            (0x10U)
#define ICR019_IL2_BITMASK            (0x20U)
#define ICR019_IP_GRPMASK             (0x7U)
#define ICR019_IP_GRPPOS              (0U)
#define ICR019_IL_GRPMASK             (0x38U)
#define ICR019_IL_GRPPOS              (0x3U)

/*** ICR020 - Interrupt Control Register 20.; 0x00000C54 ***/
#define ICR020                        (*((volatile uint8 *)(&__IPSBAR[0x00000C54UL])))
#define ICR020_IP0_BITMASK            (0x1U)
#define ICR020_IP1_BITMASK            (0x2U)
#define ICR020_IP2_BITMASK            (0x4U)
#define ICR020_IL0_BITMASK            (0x8U)
#define ICR020_IL1_BITMASK            (0x10U)
#define ICR020_IL2_BITMASK            (0x20U)
#define ICR020_IP_GRPMASK             (0x7U)
#define ICR020_IP_GRPPOS              (0U)
#define ICR020_IL_GRPMASK             (0x38U)
#define ICR020_IL_GRPPOS              (0x3U)

/*** ICR021 - Interrupt Control Register 21.; 0x00000C55 ***/
#define ICR021                        (*((volatile uint8 *)(&__IPSBAR[0x00000C55UL])))
#define ICR021_IP0_BITMASK            (0x1U)
#define ICR021_IP1_BITMASK            (0x2U)
#define ICR021_IP2_BITMASK            (0x4U)
#define ICR021_IL0_BITMASK            (0x8U)
#define ICR021_IL1_BITMASK            (0x10U)
#define ICR021_IL2_BITMASK            (0x20U)
#define ICR021_IP_GRPMASK             (0x7U)
#define ICR021_IP_GRPPOS              (0U)
#define ICR021_IL_GRPMASK             (0x38U)
#define ICR021_IL_GRPPOS              (0x3U)

/*** ICR022 - Interrupt Control Register 22.; 0x00000C56 ***/
#define ICR022                        (*((volatile uint8 *)(&__IPSBAR[0x00000C56UL])))
#define ICR022_IP0_BITMASK            (0x1U)
#define ICR022_IP1_BITMASK            (0x2U)
#define ICR022_IP2_BITMASK            (0x4U)
#define ICR022_IL0_BITMASK            (0x8U)
#define ICR022_IL1_BITMASK            (0x10U)
#define ICR022_IL2_BITMASK            (0x20U)
#define ICR022_IP_GRPMASK             (0x7U)
#define ICR022_IP_GRPPOS              (0U)
#define ICR022_IL_GRPMASK             (0x38U)
#define ICR022_IL_GRPPOS              (0x3U)

/*** ICR023 - Interrupt Control Register 23.; 0x00000C57 ***/
#define ICR023                        (*((volatile uint8 *)(&__IPSBAR[0x00000C57UL])))
#define ICR023_IP0_BITMASK            (0x1U)
#define ICR023_IP1_BITMASK            (0x2U)
#define ICR023_IP2_BITMASK            (0x4U)
#define ICR023_IL0_BITMASK            (0x8U)
#define ICR023_IL1_BITMASK            (0x10U)
#define ICR023_IL2_BITMASK            (0x20U)
#define ICR023_IP_GRPMASK             (0x7U)
#define ICR023_IP_GRPPOS              (0U)
#define ICR023_IL_GRPMASK             (0x38U)
#define ICR023_IL_GRPPOS              (0x3U)

/*** ICR024 - Interrupt Control Register 24.; 0x00000C58 ***/
#define ICR024                        (*((volatile uint8 *)(&__IPSBAR[0x00000C58UL])))
#define ICR024_IP0_BITMASK            (0x1U)
#define ICR024_IP1_BITMASK            (0x2U)
#define ICR024_IP2_BITMASK            (0x4U)
#define ICR024_IL0_BITMASK            (0x8U)
#define ICR024_IL1_BITMASK            (0x10U)
#define ICR024_IL2_BITMASK            (0x20U)
#define ICR024_IP_GRPMASK             (0x7U)
#define ICR024_IP_GRPPOS              (0U)
#define ICR024_IL_GRPMASK             (0x38U)
#define ICR024_IL_GRPPOS              (0x3U)

/*** ICR025 - Interrupt Control Register 25.; 0x00000C59 ***/
#define ICR025                        (*((volatile uint8 *)(&__IPSBAR[0x00000C59UL])))
#define ICR025_IP0_BITMASK            (0x1U)
#define ICR025_IP1_BITMASK            (0x2U)
#define ICR025_IP2_BITMASK            (0x4U)
#define ICR025_IL0_BITMASK            (0x8U)
#define ICR025_IL1_BITMASK            (0x10U)
#define ICR025_IL2_BITMASK            (0x20U)
#define ICR025_IP_GRPMASK             (0x7U)
#define ICR025_IP_GRPPOS              (0U)
#define ICR025_IL_GRPMASK             (0x38U)
#define ICR025_IL_GRPPOS              (0x3U)

/*** ICR026 - Interrupt Control Register 26.; 0x00000C5A ***/
#define ICR026                        (*((volatile uint8 *)(&__IPSBAR[0x00000C5AUL])))
#define ICR026_IP0_BITMASK            (0x1U)
#define ICR026_IP1_BITMASK            (0x2U)
#define ICR026_IP2_BITMASK            (0x4U)
#define ICR026_IL0_BITMASK            (0x8U)
#define ICR026_IL1_BITMASK            (0x10U)
#define ICR026_IL2_BITMASK            (0x20U)
#define ICR026_IP_GRPMASK             (0x7U)
#define ICR026_IP_GRPPOS              (0U)
#define ICR026_IL_GRPMASK             (0x38U)
#define ICR026_IL_GRPPOS              (0x3U)

/*** ICR027 - Interrupt Control Register 27.; 0x00000C5B ***/
#define ICR027                        (*((volatile uint8 *)(&__IPSBAR[0x00000C5BUL])))
#define ICR027_IP0_BITMASK            (0x1U)
#define ICR027_IP1_BITMASK            (0x2U)
#define ICR027_IP2_BITMASK            (0x4U)
#define ICR027_IL0_BITMASK            (0x8U)
#define ICR027_IL1_BITMASK            (0x10U)
#define ICR027_IL2_BITMASK            (0x20U)
#define ICR027_IP_GRPMASK             (0x7U)
#define ICR027_IP_GRPPOS              (0U)
#define ICR027_IL_GRPMASK             (0x38U)
#define ICR027_IL_GRPPOS              (0x3U)

/*** ICR028 - Interrupt Control Register 28.; 0x00000C5C ***/
#define ICR028                        (*((volatile uint8 *)(&__IPSBAR[0x00000C5CUL])))
#define ICR028_IP0_BITMASK            (0x1U)
#define ICR028_IP1_BITMASK            (0x2U)
#define ICR028_IP2_BITMASK            (0x4U)
#define ICR028_IL0_BITMASK            (0x8U)
#define ICR028_IL1_BITMASK            (0x10U)
#define ICR028_IL2_BITMASK            (0x20U)
#define ICR028_IP_GRPMASK             (0x7U)
#define ICR028_IP_GRPPOS              (0U)
#define ICR028_IL_GRPMASK             (0x38U)
#define ICR028_IL_GRPPOS              (0x3U)

/*** ICR029 - Interrupt Control Register 29.; 0x00000C5D ***/
#define ICR029                        (*((volatile uint8 *)(&__IPSBAR[0x00000C5DUL])))
#define ICR029_IP0_BITMASK            (0x1U)
#define ICR029_IP1_BITMASK            (0x2U)
#define ICR029_IP2_BITMASK            (0x4U)
#define ICR029_IL0_BITMASK            (0x8U)
#define ICR029_IL1_BITMASK            (0x10U)
#define ICR029_IL2_BITMASK            (0x20U)
#define ICR029_IP_GRPMASK             (0x7U)
#define ICR029_IP_GRPPOS              (0U)
#define ICR029_IL_GRPMASK             (0x38U)
#define ICR029_IL_GRPPOS              (0x3U)

/*** ICR030 - Interrupt Control Register 30.; 0x00000C5E ***/
#define ICR030                        (*((volatile uint8 *)(&__IPSBAR[0x00000C5EUL])))
#define ICR030_IP0_BITMASK            (0x1U)
#define ICR030_IP1_BITMASK            (0x2U)
#define ICR030_IP2_BITMASK            (0x4U)
#define ICR030_IL0_BITMASK            (0x8U)
#define ICR030_IL1_BITMASK            (0x10U)
#define ICR030_IL2_BITMASK            (0x20U)
#define ICR030_IP_GRPMASK             (0x7U)
#define ICR030_IP_GRPPOS              (0U)
#define ICR030_IL_GRPMASK             (0x38U)
#define ICR030_IL_GRPPOS              (0x3U)

/*** ICR031 - Interrupt Control Register 31.; 0x00000C5F ***/
#define ICR031                        (*((volatile uint8 *)(&__IPSBAR[0x00000C5FUL])))
#define ICR031_IP0_BITMASK            (0x1U)
#define ICR031_IP1_BITMASK            (0x2U)
#define ICR031_IP2_BITMASK            (0x4U)
#define ICR031_IL0_BITMASK            (0x8U)
#define ICR031_IL1_BITMASK            (0x10U)
#define ICR031_IL2_BITMASK            (0x20U)
#define ICR031_IP_GRPMASK             (0x7U)
#define ICR031_IP_GRPPOS              (0U)
#define ICR031_IL_GRPMASK             (0x38U)
#define ICR031_IL_GRPPOS              (0x3U)

/*** ICR032 - Interrupt Control Register 32.; 0x00000C60 ***/
#define ICR032                        (*((volatile uint8 *)(&__IPSBAR[0x00000C60UL])))
#define ICR032_IP0_BITMASK            (0x1U)
#define ICR032_IP1_BITMASK            (0x2U)
#define ICR032_IP2_BITMASK            (0x4U)
#define ICR032_IL0_BITMASK            (0x8U)
#define ICR032_IL1_BITMASK            (0x10U)
#define ICR032_IL2_BITMASK            (0x20U)
#define ICR032_IP_GRPMASK             (0x7U)
#define ICR032_IP_GRPPOS              (0U)
#define ICR032_IL_GRPMASK             (0x38U)
#define ICR032_IL_GRPPOS              (0x3U)

/*** ICR033 - Interrupt Control Register 33.; 0x00000C61 ***/
#define ICR033                        (*((volatile uint8 *)(&__IPSBAR[0x00000C61UL])))
#define ICR033_IP0_BITMASK            (0x1U)
#define ICR033_IP1_BITMASK            (0x2U)
#define ICR033_IP2_BITMASK            (0x4U)
#define ICR033_IL0_BITMASK            (0x8U)
#define ICR033_IL1_BITMASK            (0x10U)
#define ICR033_IL2_BITMASK            (0x20U)
#define ICR033_IP_GRPMASK             (0x7U)
#define ICR033_IP_GRPPOS              (0U)
#define ICR033_IL_GRPMASK             (0x38U)
#define ICR033_IL_GRPPOS              (0x3U)

/*** ICR034 - Interrupt Control Register 34.; 0x00000C62 ***/
#define ICR034                        (*((volatile uint8 *)(&__IPSBAR[0x00000C62UL])))
#define ICR034_IP0_BITMASK            (0x1U)
#define ICR034_IP1_BITMASK            (0x2U)
#define ICR034_IP2_BITMASK            (0x4U)
#define ICR034_IL0_BITMASK            (0x8U)
#define ICR034_IL1_BITMASK            (0x10U)
#define ICR034_IL2_BITMASK            (0x20U)
#define ICR034_IP_GRPMASK             (0x7U)
#define ICR034_IP_GRPPOS              (0U)
#define ICR034_IL_GRPMASK             (0x38U)
#define ICR034_IL_GRPPOS              (0x3U)

/*** ICR035 - Interrupt Control Register 35.; 0x00000C63 ***/
#define ICR035                        (*((volatile uint8 *)(&__IPSBAR[0x00000C63UL])))
#define ICR035_IP0_BITMASK            (0x1U)
#define ICR035_IP1_BITMASK            (0x2U)
#define ICR035_IP2_BITMASK            (0x4U)
#define ICR035_IL0_BITMASK            (0x8U)
#define ICR035_IL1_BITMASK            (0x10U)
#define ICR035_IL2_BITMASK            (0x20U)
#define ICR035_IP_GRPMASK             (0x7U)
#define ICR035_IP_GRPPOS              (0U)
#define ICR035_IL_GRPMASK             (0x38U)
#define ICR035_IL_GRPPOS              (0x3U)

/*** ICR036 - Interrupt Control Register 36.; 0x00000C64 ***/
#define ICR036                        (*((volatile uint8 *)(&__IPSBAR[0x00000C64UL])))
#define ICR036_IP0_BITMASK            (0x1U)
#define ICR036_IP1_BITMASK            (0x2U)
#define ICR036_IP2_BITMASK            (0x4U)
#define ICR036_IL0_BITMASK            (0x8U)
#define ICR036_IL1_BITMASK            (0x10U)
#define ICR036_IL2_BITMASK            (0x20U)
#define ICR036_IP_GRPMASK             (0x7U)
#define ICR036_IP_GRPPOS              (0U)
#define ICR036_IL_GRPMASK             (0x38U)
#define ICR036_IL_GRPPOS              (0x3U)

/*** ICR037 - Interrupt Control Register 37.; 0x00000C65 ***/
#define ICR037                        (*((volatile uint8 *)(&__IPSBAR[0x00000C65UL])))
#define ICR037_IP0_BITMASK            (0x1U)
#define ICR037_IP1_BITMASK            (0x2U)
#define ICR037_IP2_BITMASK            (0x4U)
#define ICR037_IL0_BITMASK            (0x8U)
#define ICR037_IL1_BITMASK            (0x10U)
#define ICR037_IL2_BITMASK            (0x20U)
#define ICR037_IP_GRPMASK             (0x7U)
#define ICR037_IP_GRPPOS              (0U)
#define ICR037_IL_GRPMASK             (0x38U)
#define ICR037_IL_GRPPOS              (0x3U)

/*** ICR038 - Interrupt Control Register 38.; 0x00000C66 ***/
#define ICR038                        (*((volatile uint8 *)(&__IPSBAR[0x00000C66UL])))
#define ICR038_IP0_BITMASK            (0x1U)
#define ICR038_IP1_BITMASK            (0x2U)
#define ICR038_IP2_BITMASK            (0x4U)
#define ICR038_IL0_BITMASK            (0x8U)
#define ICR038_IL1_BITMASK            (0x10U)
#define ICR038_IL2_BITMASK            (0x20U)
#define ICR038_IP_GRPMASK             (0x7U)
#define ICR038_IP_GRPPOS              (0U)
#define ICR038_IL_GRPMASK             (0x38U)
#define ICR038_IL_GRPPOS              (0x3U)

/*** ICR039 - Interrupt Control Register 39.; 0x00000C67 ***/
#define ICR039                        (*((volatile uint8 *)(&__IPSBAR[0x00000C67UL])))
#define ICR039_IP0_BITMASK            (0x1U)
#define ICR039_IP1_BITMASK            (0x2U)
#define ICR039_IP2_BITMASK            (0x4U)
#define ICR039_IL0_BITMASK            (0x8U)
#define ICR039_IL1_BITMASK            (0x10U)
#define ICR039_IL2_BITMASK            (0x20U)
#define ICR039_IP_GRPMASK             (0x7U)
#define ICR039_IP_GRPPOS              (0U)
#define ICR039_IL_GRPMASK             (0x38U)
#define ICR039_IL_GRPPOS              (0x3U)

/*** ICR040 - Interrupt Control Register 40.; 0x00000C68 ***/
#define ICR040                        (*((volatile uint8 *)(&__IPSBAR[0x00000C68UL])))
#define ICR040_IP0_BITMASK            (0x1U)
#define ICR040_IP1_BITMASK            (0x2U)
#define ICR040_IP2_BITMASK            (0x4U)
#define ICR040_IL0_BITMASK            (0x8U)
#define ICR040_IL1_BITMASK            (0x10U)
#define ICR040_IL2_BITMASK            (0x20U)
#define ICR040_IP_GRPMASK             (0x7U)
#define ICR040_IP_GRPPOS              (0U)
#define ICR040_IL_GRPMASK             (0x38U)
#define ICR040_IL_GRPPOS              (0x3U)

/*** ICR041 - Interrupt Control Register 41.; 0x00000C69 ***/
#define ICR041                        (*((volatile uint8 *)(&__IPSBAR[0x00000C69UL])))
#define ICR041_IP0_BITMASK            (0x1U)
#define ICR041_IP1_BITMASK            (0x2U)
#define ICR041_IP2_BITMASK            (0x4U)
#define ICR041_IL0_BITMASK            (0x8U)
#define ICR041_IL1_BITMASK            (0x10U)
#define ICR041_IL2_BITMASK            (0x20U)
#define ICR041_IP_GRPMASK             (0x7U)
#define ICR041_IP_GRPPOS              (0U)
#define ICR041_IL_GRPMASK             (0x38U)
#define ICR041_IL_GRPPOS              (0x3U)

/*** ICR042 - Interrupt Control Register 42.; 0x00000C6A ***/
#define ICR042                        (*((volatile uint8 *)(&__IPSBAR[0x00000C6AUL])))
#define ICR042_IP0_BITMASK            (0x1U)
#define ICR042_IP1_BITMASK            (0x2U)
#define ICR042_IP2_BITMASK            (0x4U)
#define ICR042_IL0_BITMASK            (0x8U)
#define ICR042_IL1_BITMASK            (0x10U)
#define ICR042_IL2_BITMASK            (0x20U)
#define ICR042_IP_GRPMASK             (0x7U)
#define ICR042_IP_GRPPOS              (0U)
#define ICR042_IL_GRPMASK             (0x38U)
#define ICR042_IL_GRPPOS              (0x3U)

/*** ICR043 - Interrupt Control Register 43.; 0x00000C6B ***/
#define ICR043                        (*((volatile uint8 *)(&__IPSBAR[0x00000C6BUL])))
#define ICR043_IP0_BITMASK            (0x1U)
#define ICR043_IP1_BITMASK            (0x2U)
#define ICR043_IP2_BITMASK            (0x4U)
#define ICR043_IL0_BITMASK            (0x8U)
#define ICR043_IL1_BITMASK            (0x10U)
#define ICR043_IL2_BITMASK            (0x20U)
#define ICR043_IP_GRPMASK             (0x7U)
#define ICR043_IP_GRPPOS              (0U)
#define ICR043_IL_GRPMASK             (0x38U)
#define ICR043_IL_GRPPOS              (0x3U)

/*** ICR044 - Interrupt Control Register 44.; 0x00000C6C ***/
#define ICR044                        (*((volatile uint8 *)(&__IPSBAR[0x00000C6CUL])))
#define ICR044_IP0_BITMASK            (0x1U)
#define ICR044_IP1_BITMASK            (0x2U)
#define ICR044_IP2_BITMASK            (0x4U)
#define ICR044_IL0_BITMASK            (0x8U)
#define ICR044_IL1_BITMASK            (0x10U)
#define ICR044_IL2_BITMASK            (0x20U)
#define ICR044_IP_GRPMASK             (0x7U)
#define ICR044_IP_GRPPOS              (0U)
#define ICR044_IL_GRPMASK             (0x38U)
#define ICR044_IL_GRPPOS              (0x3U)

/*** ICR045 - Interrupt Control Register 45.; 0x00000C6D ***/
#define ICR045                        (*((volatile uint8 *)(&__IPSBAR[0x00000C6DUL])))
#define ICR045_IP0_BITMASK            (0x1U)
#define ICR045_IP1_BITMASK            (0x2U)
#define ICR045_IP2_BITMASK            (0x4U)
#define ICR045_IL0_BITMASK            (0x8U)
#define ICR045_IL1_BITMASK            (0x10U)
#define ICR045_IL2_BITMASK            (0x20U)
#define ICR045_IP_GRPMASK             (0x7U)
#define ICR045_IP_GRPPOS              (0U)
#define ICR045_IL_GRPMASK             (0x38U)
#define ICR045_IL_GRPPOS              (0x3U)

/*** ICR046 - Interrupt Control Register 46.; 0x00000C6E ***/
#define ICR046                        (*((volatile uint8 *)(&__IPSBAR[0x00000C6EUL])))
#define ICR046_IP0_BITMASK            (0x1U)
#define ICR046_IP1_BITMASK            (0x2U)
#define ICR046_IP2_BITMASK            (0x4U)
#define ICR046_IL0_BITMASK            (0x8U)
#define ICR046_IL1_BITMASK            (0x10U)
#define ICR046_IL2_BITMASK            (0x20U)
#define ICR046_IP_GRPMASK             (0x7U)
#define ICR046_IP_GRPPOS              (0U)
#define ICR046_IL_GRPMASK             (0x38U)
#define ICR046_IL_GRPPOS              (0x3U)

/*** ICR047 - Interrupt Control Register 47.; 0x00000C6F ***/
#define ICR047                        (*((volatile uint8 *)(&__IPSBAR[0x00000C6FUL])))
#define ICR047_IP0_BITMASK            (0x1U)
#define ICR047_IP1_BITMASK            (0x2U)
#define ICR047_IP2_BITMASK            (0x4U)
#define ICR047_IL0_BITMASK            (0x8U)
#define ICR047_IL1_BITMASK            (0x10U)
#define ICR047_IL2_BITMASK            (0x20U)
#define ICR047_IP_GRPMASK             (0x7U)
#define ICR047_IP_GRPPOS              (0U)
#define ICR047_IL_GRPMASK             (0x38U)
#define ICR047_IL_GRPPOS              (0x3U)

/*** ICR048 - Interrupt Control Register 48.; 0x00000C70 ***/
#define ICR048                        (*((volatile uint8 *)(&__IPSBAR[0x00000C70UL])))
#define ICR048_IP0_BITMASK            (0x1U)
#define ICR048_IP1_BITMASK            (0x2U)
#define ICR048_IP2_BITMASK            (0x4U)
#define ICR048_IL0_BITMASK            (0x8U)
#define ICR048_IL1_BITMASK            (0x10U)
#define ICR048_IL2_BITMASK            (0x20U)
#define ICR048_IP_GRPMASK             (0x7U)
#define ICR048_IP_GRPPOS              (0U)
#define ICR048_IL_GRPMASK             (0x38U)
#define ICR048_IL_GRPPOS              (0x3U)

/*** ICR049 - Interrupt Control Register 49.; 0x00000C71 ***/
#define ICR049                        (*((volatile uint8 *)(&__IPSBAR[0x00000C71UL])))
#define ICR049_IP0_BITMASK            (0x1U)
#define ICR049_IP1_BITMASK            (0x2U)
#define ICR049_IP2_BITMASK            (0x4U)
#define ICR049_IL0_BITMASK            (0x8U)
#define ICR049_IL1_BITMASK            (0x10U)
#define ICR049_IL2_BITMASK            (0x20U)
#define ICR049_IP_GRPMASK             (0x7U)
#define ICR049_IP_GRPPOS              (0U)
#define ICR049_IL_GRPMASK             (0x38U)
#define ICR049_IL_GRPPOS              (0x3U)

/*** ICR050 - Interrupt Control Register 50.; 0x00000C72 ***/
#define ICR050                        (*((volatile uint8 *)(&__IPSBAR[0x00000C72UL])))
#define ICR050_IP0_BITMASK            (0x1U)
#define ICR050_IP1_BITMASK            (0x2U)
#define ICR050_IP2_BITMASK            (0x4U)
#define ICR050_IL0_BITMASK            (0x8U)
#define ICR050_IL1_BITMASK            (0x10U)
#define ICR050_IL2_BITMASK            (0x20U)
#define ICR050_IP_GRPMASK             (0x7U)
#define ICR050_IP_GRPPOS              (0U)
#define ICR050_IL_GRPMASK             (0x38U)
#define ICR050_IL_GRPPOS              (0x3U)

/*** ICR051 - Interrupt Control Register 51.; 0x00000C73 ***/
#define ICR051                        (*((volatile uint8 *)(&__IPSBAR[0x00000C73UL])))
#define ICR051_IP0_BITMASK            (0x1U)
#define ICR051_IP1_BITMASK            (0x2U)
#define ICR051_IP2_BITMASK            (0x4U)
#define ICR051_IL0_BITMASK            (0x8U)
#define ICR051_IL1_BITMASK            (0x10U)
#define ICR051_IL2_BITMASK            (0x20U)
#define ICR051_IP_GRPMASK             (0x7U)
#define ICR051_IP_GRPPOS              (0U)
#define ICR051_IL_GRPMASK             (0x38U)
#define ICR051_IL_GRPPOS              (0x3U)

/*** ICR052 - Interrupt Control Register 52.; 0x00000C74 ***/
#define ICR052                        (*((volatile uint8 *)(&__IPSBAR[0x00000C74UL])))
#define ICR052_IP0_BITMASK            (0x1U)
#define ICR052_IP1_BITMASK            (0x2U)
#define ICR052_IP2_BITMASK            (0x4U)
#define ICR052_IL0_BITMASK            (0x8U)
#define ICR052_IL1_BITMASK            (0x10U)
#define ICR052_IL2_BITMASK            (0x20U)
#define ICR052_IP_GRPMASK             (0x7U)
#define ICR052_IP_GRPPOS              (0U)
#define ICR052_IL_GRPMASK             (0x38U)
#define ICR052_IL_GRPPOS              (0x3U)

/*** ICR053 - Interrupt Control Register 53.; 0x00000C75 ***/
#define ICR053                        (*((volatile uint8 *)(&__IPSBAR[0x00000C75UL])))
#define ICR053_IP0_BITMASK            (0x1U)
#define ICR053_IP1_BITMASK            (0x2U)
#define ICR053_IP2_BITMASK            (0x4U)
#define ICR053_IL0_BITMASK            (0x8U)
#define ICR053_IL1_BITMASK            (0x10U)
#define ICR053_IL2_BITMASK            (0x20U)
#define ICR053_IP_GRPMASK             (0x7U)
#define ICR053_IP_GRPPOS              (0U)
#define ICR053_IL_GRPMASK             (0x38U)
#define ICR053_IL_GRPPOS              (0x3U)

/*** ICR054 - Interrupt Control Register 54.; 0x00000C76 ***/
#define ICR054                        (*((volatile uint8 *)(&__IPSBAR[0x00000C76UL])))
#define ICR054_IP0_BITMASK            (0x1U)
#define ICR054_IP1_BITMASK            (0x2U)
#define ICR054_IP2_BITMASK            (0x4U)
#define ICR054_IL0_BITMASK            (0x8U)
#define ICR054_IL1_BITMASK            (0x10U)
#define ICR054_IL2_BITMASK            (0x20U)
#define ICR054_IP_GRPMASK             (0x7U)
#define ICR054_IP_GRPPOS              (0U)
#define ICR054_IL_GRPMASK             (0x38U)
#define ICR054_IL_GRPPOS              (0x3U)

/*** ICR055 - Interrupt Control Register 55.; 0x00000C77 ***/
#define ICR055                        (*((volatile uint8 *)(&__IPSBAR[0x00000C77UL])))
#define ICR055_IP0_BITMASK            (0x1U)
#define ICR055_IP1_BITMASK            (0x2U)
#define ICR055_IP2_BITMASK            (0x4U)
#define ICR055_IL0_BITMASK            (0x8U)
#define ICR055_IL1_BITMASK            (0x10U)
#define ICR055_IL2_BITMASK            (0x20U)
#define ICR055_IP_GRPMASK             (0x7U)
#define ICR055_IP_GRPPOS              (0U)
#define ICR055_IL_GRPMASK             (0x38U)
#define ICR055_IL_GRPPOS              (0x3U)

/*** ICR056 - Interrupt Control Register 56.; 0x00000C78 ***/
#define ICR056                        (*((volatile uint8 *)(&__IPSBAR[0x00000C78UL])))
#define ICR056_IP0_BITMASK            (0x1U)
#define ICR056_IP1_BITMASK            (0x2U)
#define ICR056_IP2_BITMASK            (0x4U)
#define ICR056_IL0_BITMASK            (0x8U)
#define ICR056_IL1_BITMASK            (0x10U)
#define ICR056_IL2_BITMASK            (0x20U)
#define ICR056_IP_GRPMASK             (0x7U)
#define ICR056_IP_GRPPOS              (0U)
#define ICR056_IL_GRPMASK             (0x38U)
#define ICR056_IL_GRPPOS              (0x3U)

/*** ICR057 - Interrupt Control Register 57.; 0x00000C79 ***/
#define ICR057                        (*((volatile uint8 *)(&__IPSBAR[0x00000C79UL])))
#define ICR057_IP0_BITMASK            (0x1U)
#define ICR057_IP1_BITMASK            (0x2U)
#define ICR057_IP2_BITMASK            (0x4U)
#define ICR057_IL0_BITMASK            (0x8U)
#define ICR057_IL1_BITMASK            (0x10U)
#define ICR057_IL2_BITMASK            (0x20U)
#define ICR057_IP_GRPMASK             (0x7U)
#define ICR057_IP_GRPPOS              (0U)
#define ICR057_IL_GRPMASK             (0x38U)
#define ICR057_IL_GRPPOS              (0x3U)

/*** ICR058 - Interrupt Control Register 58.; 0x00000C7A ***/
#define ICR058                        (*((volatile uint8 *)(&__IPSBAR[0x00000C7AUL])))
#define ICR058_IP0_BITMASK            (0x1U)
#define ICR058_IP1_BITMASK            (0x2U)
#define ICR058_IP2_BITMASK            (0x4U)
#define ICR058_IL0_BITMASK            (0x8U)
#define ICR058_IL1_BITMASK            (0x10U)
#define ICR058_IL2_BITMASK            (0x20U)
#define ICR058_IP_GRPMASK             (0x7U)
#define ICR058_IP_GRPPOS              (0U)
#define ICR058_IL_GRPMASK             (0x38U)
#define ICR058_IL_GRPPOS              (0x3U)

/*** ICR059 - Interrupt Control Register 59.; 0x00000C7B ***/
#define ICR059                        (*((volatile uint8 *)(&__IPSBAR[0x00000C7BUL])))
#define ICR059_IP0_BITMASK            (0x1U)
#define ICR059_IP1_BITMASK            (0x2U)
#define ICR059_IP2_BITMASK            (0x4U)
#define ICR059_IL0_BITMASK            (0x8U)
#define ICR059_IL1_BITMASK            (0x10U)
#define ICR059_IL2_BITMASK            (0x20U)
#define ICR059_IP_GRPMASK             (0x7U)
#define ICR059_IP_GRPPOS              (0U)
#define ICR059_IL_GRPMASK             (0x38U)
#define ICR059_IL_GRPPOS              (0x3U)

/*** ICR060 - Interrupt Control Register 60.; 0x00000C7C ***/
#define ICR060                        (*((volatile uint8 *)(&__IPSBAR[0x00000C7CUL])))
#define ICR060_IP0_BITMASK            (0x1U)
#define ICR060_IP1_BITMASK            (0x2U)
#define ICR060_IP2_BITMASK            (0x4U)
#define ICR060_IL0_BITMASK            (0x8U)
#define ICR060_IL1_BITMASK            (0x10U)
#define ICR060_IL2_BITMASK            (0x20U)
#define ICR060_IP_GRPMASK             (0x7U)
#define ICR060_IP_GRPPOS              (0U)
#define ICR060_IL_GRPMASK             (0x38U)
#define ICR060_IL_GRPPOS              (0x3U)

/*** ICR061 - Interrupt Control Register 61.; 0x00000C7D ***/
#define ICR061                        (*((volatile uint8 *)(&__IPSBAR[0x00000C7DUL])))
#define ICR061_IP0_BITMASK            (0x1U)
#define ICR061_IP1_BITMASK            (0x2U)
#define ICR061_IP2_BITMASK            (0x4U)
#define ICR061_IL0_BITMASK            (0x8U)
#define ICR061_IL1_BITMASK            (0x10U)
#define ICR061_IL2_BITMASK            (0x20U)
#define ICR061_IP_GRPMASK             (0x7U)
#define ICR061_IP_GRPPOS              (0U)
#define ICR061_IL_GRPMASK             (0x38U)
#define ICR061_IL_GRPPOS              (0x3U)

/*** ICR062 - Interrupt Control Register 62.; 0x00000C7E ***/
#define ICR062                        (*((volatile uint8 *)(&__IPSBAR[0x00000C7EUL])))
#define ICR062_IP0_BITMASK            (0x1U)
#define ICR062_IP1_BITMASK            (0x2U)
#define ICR062_IP2_BITMASK            (0x4U)
#define ICR062_IL0_BITMASK            (0x8U)
#define ICR062_IL1_BITMASK            (0x10U)
#define ICR062_IL2_BITMASK            (0x20U)
#define ICR062_IP_GRPMASK             (0x7U)
#define ICR062_IP_GRPPOS              (0U)
#define ICR062_IL_GRPMASK             (0x38U)
#define ICR062_IL_GRPPOS              (0x3U)

/*** ICR063 - Interrupt Control Register 63.; 0x00000C7F ***/
#define ICR063                        (*((volatile uint8 *)(&__IPSBAR[0x00000C7FUL])))
#define ICR063_IP0_BITMASK            (0x1U)
#define ICR063_IP1_BITMASK            (0x2U)
#define ICR063_IP2_BITMASK            (0x4U)
#define ICR063_IL0_BITMASK            (0x8U)
#define ICR063_IL1_BITMASK            (0x10U)
#define ICR063_IL2_BITMASK            (0x20U)
#define ICR063_IP_GRPMASK             (0x7U)
#define ICR063_IP_GRPPOS              (0U)
#define ICR063_IL_GRPMASK             (0x38U)
#define ICR063_IL_GRPPOS              (0x3U)

/*** SWIACK0 - Software IACK Register.; 0x00000CE0 ***/
#define SWIACK0                       (*((volatile uint8 *)(&__IPSBAR[0x00000CE0UL])))
#define SWIACK0_VECTOR0_BITMASK       (0x1U)
#define SWIACK0_VECTOR1_BITMASK       (0x2U)
#define SWIACK0_VECTOR2_BITMASK       (0x4U)
#define SWIACK0_VECTOR3_BITMASK       (0x8U)
#define SWIACK0_VECTOR4_BITMASK       (0x10U)
#define SWIACK0_VECTOR5_BITMASK       (0x20U)
#define SWIACK0_VECTOR6_BITMASK       (0x40U)
#define SWIACK0_VECTOR7_BITMASK       (0x80U)
#define SWIACK0_VECTOR_GRPMASK        (0xFFU)
#define SWIACK0_VECTOR_GRPPOS         (0U)

/*** L1IACK0 - Level 1 IACK Register.; 0x00000CE4 ***/
#define L1IACK0                       (*((volatile uint8 *)(&__IPSBAR[0x00000CE4UL])))
#define L1IACK0_VECTOR0_BITMASK       (0x1U)
#define L1IACK0_VECTOR1_BITMASK       (0x2U)
#define L1IACK0_VECTOR2_BITMASK       (0x4U)
#define L1IACK0_VECTOR3_BITMASK       (0x8U)
#define L1IACK0_VECTOR4_BITMASK       (0x10U)
#define L1IACK0_VECTOR5_BITMASK       (0x20U)
#define L1IACK0_VECTOR6_BITMASK       (0x40U)
#define L1IACK0_VECTOR7_BITMASK       (0x80U)
#define L1IACK0_VECTOR_GRPMASK        (0xFFU)
#define L1IACK0_VECTOR_GRPPOS         (0U)

/*** L2IACK0 - Level 2 IACK Register.; 0x00000CE8 ***/
#define L2IACK0                       (*((volatile uint8 *)(&__IPSBAR[0x00000CE8UL])))
#define L2IACK0_VECTOR0_BITMASK       (0x1U)
#define L2IACK0_VECTOR1_BITMASK       (0x2U)
#define L2IACK0_VECTOR2_BITMASK       (0x4U)
#define L2IACK0_VECTOR3_BITMASK       (0x8U)
#define L2IACK0_VECTOR4_BITMASK       (0x10U)
#define L2IACK0_VECTOR5_BITMASK       (0x20U)
#define L2IACK0_VECTOR6_BITMASK       (0x40U)
#define L2IACK0_VECTOR7_BITMASK       (0x80U)
#define L2IACK0_VECTOR_GRPMASK        (0xFFU)
#define L2IACK0_VECTOR_GRPPOS         (0U)

/*** L3IACK0 - Level 3 IACK Register.; 0x00000CEC ***/
#define L3IACK0                       (*((volatile uint8 *)(&__IPSBAR[0x00000CECUL])))
#define L3IACK0_VECTOR0_BITMASK       (0x1U)
#define L3IACK0_VECTOR1_BITMASK       (0x2U)
#define L3IACK0_VECTOR2_BITMASK       (0x4U)
#define L3IACK0_VECTOR3_BITMASK       (0x8U)
#define L3IACK0_VECTOR4_BITMASK       (0x10U)
#define L3IACK0_VECTOR5_BITMASK       (0x20U)
#define L3IACK0_VECTOR6_BITMASK       (0x40U)
#define L3IACK0_VECTOR7_BITMASK       (0x80U)
#define L3IACK0_VECTOR_GRPMASK        (0xFFU)
#define L3IACK0_VECTOR_GRPPOS         (0U)

/*** L4IACK0 - Level 4 IACK Register.; 0x00000CF0 ***/
#define L4IACK0                       (*((volatile uint8 *)(&__IPSBAR[0x00000CF0UL])))
#define L4IACK0_VECTOR0_BITMASK       (0x1U)
#define L4IACK0_VECTOR1_BITMASK       (0x2U)
#define L4IACK0_VECTOR2_BITMASK       (0x4U)
#define L4IACK0_VECTOR3_BITMASK       (0x8U)
#define L4IACK0_VECTOR4_BITMASK       (0x10U)
#define L4IACK0_VECTOR5_BITMASK       (0x20U)
#define L4IACK0_VECTOR6_BITMASK       (0x40U)
#define L4IACK0_VECTOR7_BITMASK       (0x80U)
#define L4IACK0_VECTOR_GRPMASK        (0xFFU)
#define L4IACK0_VECTOR_GRPPOS         (0U)

/*** L5IACK0 - Level 5 IACK Register.; 0x00000CF4 ***/
#define L5IACK0                       (*((volatile uint8 *)(&__IPSBAR[0x00000CF4UL])))
#define L5IACK0_VECTOR0_BITMASK       (0x1U)
#define L5IACK0_VECTOR1_BITMASK       (0x2U)
#define L5IACK0_VECTOR2_BITMASK       (0x4U)
#define L5IACK0_VECTOR3_BITMASK       (0x8U)
#define L5IACK0_VECTOR4_BITMASK       (0x10U)
#define L5IACK0_VECTOR5_BITMASK       (0x20U)
#define L5IACK0_VECTOR6_BITMASK       (0x40U)
#define L5IACK0_VECTOR7_BITMASK       (0x80U)
#define L5IACK0_VECTOR_GRPMASK        (0xFFU)
#define L5IACK0_VECTOR_GRPPOS         (0U)

/*** L6IACK0 - Level 6 IACK Register.; 0x00000CF8 ***/
#define L6IACK0                       (*((volatile uint8 *)(&__IPSBAR[0x00000CF8UL])))
#define L6IACK0_VECTOR0_BITMASK       (0x1U)
#define L6IACK0_VECTOR1_BITMASK       (0x2U)
#define L6IACK0_VECTOR2_BITMASK       (0x4U)
#define L6IACK0_VECTOR3_BITMASK       (0x8U)
#define L6IACK0_VECTOR4_BITMASK       (0x10U)
#define L6IACK0_VECTOR5_BITMASK       (0x20U)
#define L6IACK0_VECTOR6_BITMASK       (0x40U)
#define L6IACK0_VECTOR7_BITMASK       (0x80U)
#define L6IACK0_VECTOR_GRPMASK        (0xFFU)
#define L6IACK0_VECTOR_GRPPOS         (0U)

/*** L7IACK0 - Level 7 IACK Register.; 0x00000CFC ***/
#define L7IACK0                       (*((volatile uint8 *)(&__IPSBAR[0x00000CFCUL])))
#define L7IACK0_VECTOR0_BITMASK       (0x1U)
#define L7IACK0_VECTOR1_BITMASK       (0x2U)
#define L7IACK0_VECTOR2_BITMASK       (0x4U)
#define L7IACK0_VECTOR3_BITMASK       (0x8U)
#define L7IACK0_VECTOR4_BITMASK       (0x10U)
#define L7IACK0_VECTOR5_BITMASK       (0x20U)
#define L7IACK0_VECTOR6_BITMASK       (0x40U)
#define L7IACK0_VECTOR7_BITMASK       (0x80U)
#define L7IACK0_VECTOR_GRPMASK        (0xFFU)
#define L7IACK0_VECTOR_GRPPOS         (0U)


/******************************************
*** Peripheral INTC1
*******************************************/

/*** IPRH1 - Interrupt Pending Register High.; 0x00000D00 ***/
#define IPRH1                         (*((volatile uint32 *)(&__IPSBAR[0x00000D00UL])))
#define IPRH1_INT32_BITMASK           (0x1U)
#define IPRH1_INT33_BITMASK           (0x2U)
#define IPRH1_INT34_BITMASK           (0x4U)
#define IPRH1_INT35_BITMASK           (0x8U)
#define IPRH1_INT36_BITMASK           (0x10U)
#define IPRH1_INT37_BITMASK           (0x20U)
#define IPRH1_INT38_BITMASK           (0x40U)
#define IPRH1_INT39_BITMASK           (0x80U)
#define IPRH1_INT40_BITMASK           (0x100U)
#define IPRH1_INT41_BITMASK           (0x200U)
#define IPRH1_INT42_BITMASK           (0x400U)
#define IPRH1_INT43_BITMASK           (0x800U)
#define IPRH1_INT44_BITMASK           (0x1000U)
#define IPRH1_INT45_BITMASK           (0x2000U)
#define IPRH1_INT46_BITMASK           (0x4000U)
#define IPRH1_INT47_BITMASK           (0x8000U)
#define IPRH1_INT48_BITMASK           (0x10000U)
#define IPRH1_INT49_BITMASK           (0x20000U)
#define IPRH1_INT50_BITMASK           (0x40000U)
#define IPRH1_INT51_BITMASK           (0x80000U)
#define IPRH1_INT52_BITMASK           (0x100000U)
#define IPRH1_INT53_BITMASK           (0x200000U)
#define IPRH1_INT54_BITMASK           (0x400000U)
#define IPRH1_INT55_BITMASK           (0x800000U)
#define IPRH1_INT56_BITMASK           (0x1000000U)
#define IPRH1_INT57_BITMASK           (0x2000000U)
#define IPRH1_INT58_BITMASK           (0x4000000U)
#define IPRH1_INT59_BITMASK           (0x8000000U)
#define IPRH1_INT60_BITMASK           (0x10000000U)
#define IPRH1_INT61_BITMASK           (0x20000000U)
#define IPRH1_INT62_BITMASK           (0x40000000U)
#define IPRH1_INT63_BITMASK           (0x80000000U)

/*** IPRL1 - Interrupt Pending Register Low.; 0x00000D04 ***/
#define IPRL1                         (*((volatile uint32 *)(&__IPSBAR[0x00000D04UL])))
#define IPRL1_INT1_BITMASK            (0x2U)
#define IPRL1_INT2_BITMASK            (0x4U)
#define IPRL1_INT3_BITMASK            (0x8U)
#define IPRL1_INT4_BITMASK            (0x10U)
#define IPRL1_INT5_BITMASK            (0x20U)
#define IPRL1_INT6_BITMASK            (0x40U)
#define IPRL1_INT7_BITMASK            (0x80U)
#define IPRL1_INT8_BITMASK            (0x100U)
#define IPRL1_INT9_BITMASK            (0x200U)
#define IPRL1_INT10_BITMASK           (0x400U)
#define IPRL1_INT11_BITMASK           (0x800U)
#define IPRL1_INT12_BITMASK           (0x1000U)
#define IPRL1_INT13_BITMASK           (0x2000U)
#define IPRL1_INT14_BITMASK           (0x4000U)
#define IPRL1_INT15_BITMASK           (0x8000U)
#define IPRL1_INT16_BITMASK           (0x10000U)
#define IPRL1_INT17_BITMASK           (0x20000U)
#define IPRL1_INT18_BITMASK           (0x40000U)
#define IPRL1_INT19_BITMASK           (0x80000U)
#define IPRL1_INT20_BITMASK           (0x100000U)
#define IPRL1_INT21_BITMASK           (0x200000U)
#define IPRL1_INT22_BITMASK           (0x400000U)
#define IPRL1_INT23_BITMASK           (0x800000U)
#define IPRL1_INT24_BITMASK           (0x1000000U)
#define IPRL1_INT25_BITMASK           (0x2000000U)
#define IPRL1_INT26_BITMASK           (0x4000000U)
#define IPRL1_INT27_BITMASK           (0x8000000U)
#define IPRL1_INT28_BITMASK           (0x10000000U)
#define IPRL1_INT29_BITMASK           (0x20000000U)
#define IPRL1_INT30_BITMASK           (0x40000000U)
#define IPRL1_INT31_BITMASK           (0x80000000U)

/*** IMRH1 - Interrupt Mask Register High.; 0x00000D08 ***/
#define IMRH1                         (*((volatile uint32 *)(&__IPSBAR[0x00000D08UL])))
#define IMRH1_INT_MASK32_BITMASK      (0x1U)
#define IMRH1_INT_MASK33_BITMASK      (0x2U)
#define IMRH1_INT_MASK34_BITMASK      (0x4U)
#define IMRH1_INT_MASK35_BITMASK      (0x8U)
#define IMRH1_INT_MASK36_BITMASK      (0x10U)
#define IMRH1_INT_MASK37_BITMASK      (0x20U)
#define IMRH1_INT_MASK38_BITMASK      (0x40U)
#define IMRH1_INT_MASK39_BITMASK      (0x80U)
#define IMRH1_INT_MASK40_BITMASK      (0x100U)
#define IMRH1_INT_MASK41_BITMASK      (0x200U)
#define IMRH1_INT_MASK42_BITMASK      (0x400U)
#define IMRH1_INT_MASK43_BITMASK      (0x800U)
#define IMRH1_INT_MASK44_BITMASK      (0x1000U)
#define IMRH1_INT_MASK45_BITMASK      (0x2000U)
#define IMRH1_INT_MASK46_BITMASK      (0x4000U)
#define IMRH1_INT_MASK47_BITMASK      (0x8000U)
#define IMRH1_INT_MASK48_BITMASK      (0x10000U)
#define IMRH1_INT_MASK49_BITMASK      (0x20000U)
#define IMRH1_INT_MASK50_BITMASK      (0x40000U)
#define IMRH1_INT_MASK51_BITMASK      (0x80000U)
#define IMRH1_INT_MASK52_BITMASK      (0x100000U)
#define IMRH1_INT_MASK53_BITMASK      (0x200000U)
#define IMRH1_INT_MASK54_BITMASK      (0x400000U)
#define IMRH1_INT_MASK55_BITMASK      (0x800000U)
#define IMRH1_INT_MASK56_BITMASK      (0x1000000U)
#define IMRH1_INT_MASK57_BITMASK      (0x2000000U)
#define IMRH1_INT_MASK58_BITMASK      (0x4000000U)
#define IMRH1_INT_MASK59_BITMASK      (0x8000000U)
#define IMRH1_INT_MASK60_BITMASK      (0x10000000U)
#define IMRH1_INT_MASK61_BITMASK      (0x20000000U)
#define IMRH1_INT_MASK62_BITMASK      (0x40000000U)
#define IMRH1_INT_MASK63_BITMASK      (0x80000000U)

/*** IMRL1 - Interrupt Mask Register Low.; 0x00000D0C ***/
#define IMRL1                         (*((volatile uint32 *)(&__IPSBAR[0x00000D0CUL])))
#define IMRL1_MASKALL_BITMASK         (0x1U)
#define IMRL1_INT_MASK1_BITMASK       (0x2U)
#define IMRL1_INT_MASK2_BITMASK       (0x4U)
#define IMRL1_INT_MASK3_BITMASK       (0x8U)
#define IMRL1_INT_MASK4_BITMASK       (0x10U)
#define IMRL1_INT_MASK5_BITMASK       (0x20U)
#define IMRL1_INT_MASK6_BITMASK       (0x40U)
#define IMRL1_INT_MASK7_BITMASK       (0x80U)
#define IMRL1_INT_MASK8_BITMASK       (0x100U)
#define IMRL1_INT_MASK9_BITMASK       (0x200U)
#define IMRL1_INT_MASK10_BITMASK      (0x400U)
#define IMRL1_INT_MASK11_BITMASK      (0x800U)
#define IMRL1_INT_MASK12_BITMASK      (0x1000U)
#define IMRL1_INT_MASK13_BITMASK      (0x2000U)
#define IMRL1_INT_MASK14_BITMASK      (0x4000U)
#define IMRL1_INT_MASK15_BITMASK      (0x8000U)
#define IMRL1_INT_MASK16_BITMASK      (0x10000U)
#define IMRL1_INT_MASK17_BITMASK      (0x20000U)
#define IMRL1_INT_MASK18_BITMASK      (0x40000U)
#define IMRL1_INT_MASK19_BITMASK      (0x80000U)
#define IMRL1_INT_MASK20_BITMASK      (0x100000U)
#define IMRL1_INT_MASK21_BITMASK      (0x200000U)
#define IMRL1_INT_MASK22_BITMASK      (0x400000U)
#define IMRL1_INT_MASK23_BITMASK      (0x800000U)
#define IMRL1_INT_MASK24_BITMASK      (0x1000000U)
#define IMRL1_INT_MASK25_BITMASK      (0x2000000U)
#define IMRL1_INT_MASK26_BITMASK      (0x4000000U)
#define IMRL1_INT_MASK27_BITMASK      (0x8000000U)
#define IMRL1_INT_MASK28_BITMASK      (0x10000000U)
#define IMRL1_INT_MASK29_BITMASK      (0x20000000U)
#define IMRL1_INT_MASK30_BITMASK      (0x40000000U)
#define IMRL1_INT_MASK31_BITMASK      (0x80000000U)

/*** INTFRCH1 - Interrupt Force Register High.; 0x00000D10 ***/
#define INTFRCH1                      (*((volatile uint32 *)(&__IPSBAR[0x00000D10UL])))
#define INTFRCH1_INTFRC32_BITMASK     (0x1U)
#define INTFRCH1_INTFRC33_BITMASK     (0x2U)
#define INTFRCH1_INTFRC34_BITMASK     (0x4U)
#define INTFRCH1_INTFRC35_BITMASK     (0x8U)
#define INTFRCH1_INTFRC36_BITMASK     (0x10U)
#define INTFRCH1_INTFRC37_BITMASK     (0x20U)
#define INTFRCH1_INTFRC38_BITMASK     (0x40U)
#define INTFRCH1_INTFRC39_BITMASK     (0x80U)
#define INTFRCH1_INTFRC40_BITMASK     (0x100U)
#define INTFRCH1_INTFRC41_BITMASK     (0x200U)
#define INTFRCH1_INTFRC42_BITMASK     (0x400U)
#define INTFRCH1_INTFRC43_BITMASK     (0x800U)
#define INTFRCH1_INTFRC44_BITMASK     (0x1000U)
#define INTFRCH1_INTFRC45_BITMASK     (0x2000U)
#define INTFRCH1_INTFRC46_BITMASK     (0x4000U)
#define INTFRCH1_INTFRC47_BITMASK     (0x8000U)
#define INTFRCH1_INTFRC48_BITMASK     (0x10000U)
#define INTFRCH1_INTFRC49_BITMASK     (0x20000U)
#define INTFRCH1_INTFRC50_BITMASK     (0x40000U)
#define INTFRCH1_INTFRC51_BITMASK     (0x80000U)
#define INTFRCH1_INTFRC52_BITMASK     (0x100000U)
#define INTFRCH1_INTFRC53_BITMASK     (0x200000U)
#define INTFRCH1_INTFRC54_BITMASK     (0x400000U)
#define INTFRCH1_INTFRC55_BITMASK     (0x800000U)
#define INTFRCH1_INTFRC56_BITMASK     (0x1000000U)
#define INTFRCH1_INTFRC57_BITMASK     (0x2000000U)
#define INTFRCH1_INTFRC58_BITMASK     (0x4000000U)
#define INTFRCH1_INTFRC59_BITMASK     (0x8000000U)
#define INTFRCH1_INTFRC60_BITMASK     (0x10000000U)
#define INTFRCH1_INTFRC61_BITMASK     (0x20000000U)
#define INTFRCH1_INTFRC62_BITMASK     (0x40000000U)
#define INTFRCH1_INTFRC63_BITMASK     (0x80000000U)

/*** INTFRCL1 - Interrupt Force Register Low.; 0x00000D14 ***/
#define INTFRCL1                      (*((volatile uint32 *)(&__IPSBAR[0x00000D14UL])))
#define INTFRCL1_INTFRC1_BITMASK      (0x2U)
#define INTFRCL1_INTFRC2_BITMASK      (0x4U)
#define INTFRCL1_INTFRC3_BITMASK      (0x8U)
#define INTFRCL1_INTFRC4_BITMASK      (0x10U)
#define INTFRCL1_INTFRC5_BITMASK      (0x20U)
#define INTFRCL1_INTFRC6_BITMASK      (0x40U)
#define INTFRCL1_INTFRC7_BITMASK      (0x80U)
#define INTFRCL1_INTFRC8_BITMASK      (0x100U)
#define INTFRCL1_INTFRC9_BITMASK      (0x200U)
#define INTFRCL1_INTFRC10_BITMASK     (0x400U)
#define INTFRCL1_INTFRC11_BITMASK     (0x800U)
#define INTFRCL1_INTFRC12_BITMASK     (0x1000U)
#define INTFRCL1_INTFRC13_BITMASK     (0x2000U)
#define INTFRCL1_INTFRC14_BITMASK     (0x4000U)
#define INTFRCL1_INTFRC15_BITMASK     (0x8000U)
#define INTFRCL1_INTFRC16_BITMASK     (0x10000U)
#define INTFRCL1_INTFRC17_BITMASK     (0x20000U)
#define INTFRCL1_INTFRC18_BITMASK     (0x40000U)
#define INTFRCL1_INTFRC19_BITMASK     (0x80000U)
#define INTFRCL1_INTFRC20_BITMASK     (0x100000U)
#define INTFRCL1_INTFRC21_BITMASK     (0x200000U)
#define INTFRCL1_INTFRC22_BITMASK     (0x400000U)
#define INTFRCL1_INTFRC23_BITMASK     (0x800000U)
#define INTFRCL1_INTFRC24_BITMASK     (0x1000000U)
#define INTFRCL1_INTFRC25_BITMASK     (0x2000000U)
#define INTFRCL1_INTFRC26_BITMASK     (0x4000000U)
#define INTFRCL1_INTFRC27_BITMASK     (0x8000000U)
#define INTFRCL1_INTFRC28_BITMASK     (0x10000000U)
#define INTFRCL1_INTFRC29_BITMASK     (0x20000000U)
#define INTFRCL1_INTFRC30_BITMASK     (0x40000000U)
#define INTFRCL1_INTFRC31_BITMASK     (0x80000000U)

/*** IRLR1 - Interrupt Request Level Register.; 0x00000D18 ***/
#define IRLR1                         (*((volatile uint8 *)(&__IPSBAR[0x00000D18UL])))
#define IRLR1_IRQ1_BITMASK            (0x2U)
#define IRLR1_IRQ2_BITMASK            (0x4U)
#define IRLR1_IRQ3_BITMASK            (0x8U)
#define IRLR1_IRQ4_BITMASK            (0x10U)
#define IRLR1_IRQ5_BITMASK            (0x20U)
#define IRLR1_IRQ6_BITMASK            (0x40U)
#define IRLR1_IRQ7_BITMASK            (0x80U)
#define IRLR1_IRQ_GRPMASK             (0xFEU)
#define IRLR1_IRQ_GRPPOS              (0x1U)

/*** IACKLPR1 - Interrupt Acknowledge Level and Priority Register.; 0x00000D19 ***/
#define IACKLPR1                      (*((volatile uint8 *)(&__IPSBAR[0x00000D19UL])))
#define IACKLPR1_PRI0_BITMASK         (0x1U)
#define IACKLPR1_PRI1_BITMASK         (0x2U)
#define IACKLPR1_PRI2_BITMASK         (0x4U)
#define IACKLPR1_PRI3_BITMASK         (0x8U)
#define IACKLPR1_LEVEL0_BITMASK       (0x10U)
#define IACKLPR1_LEVEL1_BITMASK       (0x20U)
#define IACKLPR1_LEVEL2_BITMASK       (0x40U)
#define IACKLPR1_PRI_GRPMASK          (0xFU)
#define IACKLPR1_PRI_GRPPOS           (0U)
#define IACKLPR1_LEVEL_GRPMASK        (0x70U)
#define IACKLPR1_LEVEL_GRPPOS         (0x4U)

/*** ICR101 - Interrupt Control Register 1.; 0x00000D41 ***/
#define ICR101                        (*((volatile uint8 *)(&__IPSBAR[0x00000D41UL])))
#define ICR101_IP0_BITMASK            (0x1U)
#define ICR101_IP1_BITMASK            (0x2U)
#define ICR101_IP2_BITMASK            (0x4U)
#define ICR101_IL0_BITMASK            (0x8U)
#define ICR101_IL1_BITMASK            (0x10U)
#define ICR101_IL2_BITMASK            (0x20U)
#define ICR101_IP_GRPMASK             (0x7U)
#define ICR101_IP_GRPPOS              (0U)
#define ICR101_IL_GRPMASK             (0x38U)
#define ICR101_IL_GRPPOS              (0x3U)

/*** ICR102 - Interrupt Control Register 2.; 0x00000D42 ***/
#define ICR102                        (*((volatile uint8 *)(&__IPSBAR[0x00000D42UL])))
#define ICR102_IP0_BITMASK            (0x1U)
#define ICR102_IP1_BITMASK            (0x2U)
#define ICR102_IP2_BITMASK            (0x4U)
#define ICR102_IL0_BITMASK            (0x8U)
#define ICR102_IL1_BITMASK            (0x10U)
#define ICR102_IL2_BITMASK            (0x20U)
#define ICR102_IP_GRPMASK             (0x7U)
#define ICR102_IP_GRPPOS              (0U)
#define ICR102_IL_GRPMASK             (0x38U)
#define ICR102_IL_GRPPOS              (0x3U)

/*** ICR103 - Interrupt Control Register 3.; 0x00000D43 ***/
#define ICR103                        (*((volatile uint8 *)(&__IPSBAR[0x00000D43UL])))
#define ICR103_IP0_BITMASK            (0x1U)
#define ICR103_IP1_BITMASK            (0x2U)
#define ICR103_IP2_BITMASK            (0x4U)
#define ICR103_IL0_BITMASK            (0x8U)
#define ICR103_IL1_BITMASK            (0x10U)
#define ICR103_IL2_BITMASK            (0x20U)
#define ICR103_IP_GRPMASK             (0x7U)
#define ICR103_IP_GRPPOS              (0U)
#define ICR103_IL_GRPMASK             (0x38U)
#define ICR103_IL_GRPPOS              (0x3U)

/*** ICR104 - Interrupt Control Register 4.; 0x00000D44 ***/
#define ICR104                        (*((volatile uint8 *)(&__IPSBAR[0x00000D44UL])))
#define ICR104_IP0_BITMASK            (0x1U)
#define ICR104_IP1_BITMASK            (0x2U)
#define ICR104_IP2_BITMASK            (0x4U)
#define ICR104_IL0_BITMASK            (0x8U)
#define ICR104_IL1_BITMASK            (0x10U)
#define ICR104_IL2_BITMASK            (0x20U)
#define ICR104_IP_GRPMASK             (0x7U)
#define ICR104_IP_GRPPOS              (0U)
#define ICR104_IL_GRPMASK             (0x38U)
#define ICR104_IL_GRPPOS              (0x3U)

/*** ICR105 - Interrupt Control Register 5.; 0x00000D45 ***/
#define ICR105                        (*((volatile uint8 *)(&__IPSBAR[0x00000D45UL])))
#define ICR105_IP0_BITMASK            (0x1U)
#define ICR105_IP1_BITMASK            (0x2U)
#define ICR105_IP2_BITMASK            (0x4U)
#define ICR105_IL0_BITMASK            (0x8U)
#define ICR105_IL1_BITMASK            (0x10U)
#define ICR105_IL2_BITMASK            (0x20U)
#define ICR105_IP_GRPMASK             (0x7U)
#define ICR105_IP_GRPPOS              (0U)
#define ICR105_IL_GRPMASK             (0x38U)
#define ICR105_IL_GRPPOS              (0x3U)

/*** ICR106 - Interrupt Control Register 6.; 0x00000D46 ***/
#define ICR106                        (*((volatile uint8 *)(&__IPSBAR[0x00000D46UL])))
#define ICR106_IP0_BITMASK            (0x1U)
#define ICR106_IP1_BITMASK            (0x2U)
#define ICR106_IP2_BITMASK            (0x4U)
#define ICR106_IL0_BITMASK            (0x8U)
#define ICR106_IL1_BITMASK            (0x10U)
#define ICR106_IL2_BITMASK            (0x20U)
#define ICR106_IP_GRPMASK             (0x7U)
#define ICR106_IP_GRPPOS              (0U)
#define ICR106_IL_GRPMASK             (0x38U)
#define ICR106_IL_GRPPOS              (0x3U)

/*** ICR107 - Interrupt Control Register 7.; 0x00000D47 ***/
#define ICR107                        (*((volatile uint8 *)(&__IPSBAR[0x00000D47UL])))
#define ICR107_IP0_BITMASK            (0x1U)
#define ICR107_IP1_BITMASK            (0x2U)
#define ICR107_IP2_BITMASK            (0x4U)
#define ICR107_IL0_BITMASK            (0x8U)
#define ICR107_IL1_BITMASK            (0x10U)
#define ICR107_IL2_BITMASK            (0x20U)
#define ICR107_IP_GRPMASK             (0x7U)
#define ICR107_IP_GRPPOS              (0U)
#define ICR107_IL_GRPMASK             (0x38U)
#define ICR107_IL_GRPPOS              (0x3U)

/*** ICR108 - Interrupt Control Register 8.; 0x00000D48 ***/
#define ICR108                        (*((volatile uint8 *)(&__IPSBAR[0x00000D48UL])))
#define ICR108_IP0_BITMASK            (0x1U)
#define ICR108_IP1_BITMASK            (0x2U)
#define ICR108_IP2_BITMASK            (0x4U)
#define ICR108_IL0_BITMASK            (0x8U)
#define ICR108_IL1_BITMASK            (0x10U)
#define ICR108_IL2_BITMASK            (0x20U)
#define ICR108_IP_GRPMASK             (0x7U)
#define ICR108_IP_GRPPOS              (0U)
#define ICR108_IL_GRPMASK             (0x38U)
#define ICR108_IL_GRPPOS              (0x3U)

/*** ICR109 - Interrupt Control Register 9.; 0x00000D49 ***/
#define ICR109                        (*((volatile uint8 *)(&__IPSBAR[0x00000D49UL])))
#define ICR109_IP0_BITMASK            (0x1U)
#define ICR109_IP1_BITMASK            (0x2U)
#define ICR109_IP2_BITMASK            (0x4U)
#define ICR109_IL0_BITMASK            (0x8U)
#define ICR109_IL1_BITMASK            (0x10U)
#define ICR109_IL2_BITMASK            (0x20U)
#define ICR109_IP_GRPMASK             (0x7U)
#define ICR109_IP_GRPPOS              (0U)
#define ICR109_IL_GRPMASK             (0x38U)
#define ICR109_IL_GRPPOS              (0x3U)

/*** ICR110 - Interrupt Control Register 10.; 0x00000D4A ***/
#define ICR110                        (*((volatile uint8 *)(&__IPSBAR[0x00000D4AUL])))
#define ICR110_IP0_BITMASK            (0x1U)
#define ICR110_IP1_BITMASK            (0x2U)
#define ICR110_IP2_BITMASK            (0x4U)
#define ICR110_IL0_BITMASK            (0x8U)
#define ICR110_IL1_BITMASK            (0x10U)
#define ICR110_IL2_BITMASK            (0x20U)
#define ICR110_IP_GRPMASK             (0x7U)
#define ICR110_IP_GRPPOS              (0U)
#define ICR110_IL_GRPMASK             (0x38U)
#define ICR110_IL_GRPPOS              (0x3U)

/*** ICR111 - Interrupt Control Register 11.; 0x00000D4B ***/
#define ICR111                        (*((volatile uint8 *)(&__IPSBAR[0x00000D4BUL])))
#define ICR111_IP0_BITMASK            (0x1U)
#define ICR111_IP1_BITMASK            (0x2U)
#define ICR111_IP2_BITMASK            (0x4U)
#define ICR111_IL0_BITMASK            (0x8U)
#define ICR111_IL1_BITMASK            (0x10U)
#define ICR111_IL2_BITMASK            (0x20U)
#define ICR111_IP_GRPMASK             (0x7U)
#define ICR111_IP_GRPPOS              (0U)
#define ICR111_IL_GRPMASK             (0x38U)
#define ICR111_IL_GRPPOS              (0x3U)

/*** ICR112 - Interrupt Control Register 12.; 0x00000D4C ***/
#define ICR112                        (*((volatile uint8 *)(&__IPSBAR[0x00000D4CUL])))
#define ICR112_IP0_BITMASK            (0x1U)
#define ICR112_IP1_BITMASK            (0x2U)
#define ICR112_IP2_BITMASK            (0x4U)
#define ICR112_IL0_BITMASK            (0x8U)
#define ICR112_IL1_BITMASK            (0x10U)
#define ICR112_IL2_BITMASK            (0x20U)
#define ICR112_IP_GRPMASK             (0x7U)
#define ICR112_IP_GRPPOS              (0U)
#define ICR112_IL_GRPMASK             (0x38U)
#define ICR112_IL_GRPPOS              (0x3U)

/*** ICR113 - Interrupt Control Register 13.; 0x00000D4D ***/
#define ICR113                        (*((volatile uint8 *)(&__IPSBAR[0x00000D4DUL])))
#define ICR113_IP0_BITMASK            (0x1U)
#define ICR113_IP1_BITMASK            (0x2U)
#define ICR113_IP2_BITMASK            (0x4U)
#define ICR113_IL0_BITMASK            (0x8U)
#define ICR113_IL1_BITMASK            (0x10U)
#define ICR113_IL2_BITMASK            (0x20U)
#define ICR113_IP_GRPMASK             (0x7U)
#define ICR113_IP_GRPPOS              (0U)
#define ICR113_IL_GRPMASK             (0x38U)
#define ICR113_IL_GRPPOS              (0x3U)

/*** ICR114 - Interrupt Control Register 14.; 0x00000D4E ***/
#define ICR114                        (*((volatile uint8 *)(&__IPSBAR[0x00000D4EUL])))
#define ICR114_IP0_BITMASK            (0x1U)
#define ICR114_IP1_BITMASK            (0x2U)
#define ICR114_IP2_BITMASK            (0x4U)
#define ICR114_IL0_BITMASK            (0x8U)
#define ICR114_IL1_BITMASK            (0x10U)
#define ICR114_IL2_BITMASK            (0x20U)
#define ICR114_IP_GRPMASK             (0x7U)
#define ICR114_IP_GRPPOS              (0U)
#define ICR114_IL_GRPMASK             (0x38U)
#define ICR114_IL_GRPPOS              (0x3U)

/*** ICR115 - Interrupt Control Register 15.; 0x00000D4F ***/
#define ICR115                        (*((volatile uint8 *)(&__IPSBAR[0x00000D4FUL])))
#define ICR115_IP0_BITMASK            (0x1U)
#define ICR115_IP1_BITMASK            (0x2U)
#define ICR115_IP2_BITMASK            (0x4U)
#define ICR115_IL0_BITMASK            (0x8U)
#define ICR115_IL1_BITMASK            (0x10U)
#define ICR115_IL2_BITMASK            (0x20U)
#define ICR115_IP_GRPMASK             (0x7U)
#define ICR115_IP_GRPPOS              (0U)
#define ICR115_IL_GRPMASK             (0x38U)
#define ICR115_IL_GRPPOS              (0x3U)

/*** ICR116 - Interrupt Control Register 16.; 0x00000D50 ***/
#define ICR116                        (*((volatile uint8 *)(&__IPSBAR[0x00000D50UL])))
#define ICR116_IP0_BITMASK            (0x1U)
#define ICR116_IP1_BITMASK            (0x2U)
#define ICR116_IP2_BITMASK            (0x4U)
#define ICR116_IL0_BITMASK            (0x8U)
#define ICR116_IL1_BITMASK            (0x10U)
#define ICR116_IL2_BITMASK            (0x20U)
#define ICR116_IP_GRPMASK             (0x7U)
#define ICR116_IP_GRPPOS              (0U)
#define ICR116_IL_GRPMASK             (0x38U)
#define ICR116_IL_GRPPOS              (0x3U)

/*** ICR117 - Interrupt Control Register 17.; 0x00000D51 ***/
#define ICR117                        (*((volatile uint8 *)(&__IPSBAR[0x00000D51UL])))
#define ICR117_IP0_BITMASK            (0x1U)
#define ICR117_IP1_BITMASK            (0x2U)
#define ICR117_IP2_BITMASK            (0x4U)
#define ICR117_IL0_BITMASK            (0x8U)
#define ICR117_IL1_BITMASK            (0x10U)
#define ICR117_IL2_BITMASK            (0x20U)
#define ICR117_IP_GRPMASK             (0x7U)
#define ICR117_IP_GRPPOS              (0U)
#define ICR117_IL_GRPMASK             (0x38U)
#define ICR117_IL_GRPPOS              (0x3U)

/*** ICR118 - Interrupt Control Register 18.; 0x00000D52 ***/
#define ICR118                        (*((volatile uint8 *)(&__IPSBAR[0x00000D52UL])))
#define ICR118_IP0_BITMASK            (0x1U)
#define ICR118_IP1_BITMASK            (0x2U)
#define ICR118_IP2_BITMASK            (0x4U)
#define ICR118_IL0_BITMASK            (0x8U)
#define ICR118_IL1_BITMASK            (0x10U)
#define ICR118_IL2_BITMASK            (0x20U)
#define ICR118_IP_GRPMASK             (0x7U)
#define ICR118_IP_GRPPOS              (0U)
#define ICR118_IL_GRPMASK             (0x38U)
#define ICR118_IL_GRPPOS              (0x3U)

/*** ICR119 - Interrupt Control Register 19.; 0x00000D53 ***/
#define ICR119                        (*((volatile uint8 *)(&__IPSBAR[0x00000D53UL])))
#define ICR119_IP0_BITMASK            (0x1U)
#define ICR119_IP1_BITMASK            (0x2U)
#define ICR119_IP2_BITMASK            (0x4U)
#define ICR119_IL0_BITMASK            (0x8U)
#define ICR119_IL1_BITMASK            (0x10U)
#define ICR119_IL2_BITMASK            (0x20U)
#define ICR119_IP_GRPMASK             (0x7U)
#define ICR119_IP_GRPPOS              (0U)
#define ICR119_IL_GRPMASK             (0x38U)
#define ICR119_IL_GRPPOS              (0x3U)

/*** ICR120 - Interrupt Control Register 20.; 0x00000D54 ***/
#define ICR120                        (*((volatile uint8 *)(&__IPSBAR[0x00000D54UL])))
#define ICR120_IP0_BITMASK            (0x1U)
#define ICR120_IP1_BITMASK            (0x2U)
#define ICR120_IP2_BITMASK            (0x4U)
#define ICR120_IL0_BITMASK            (0x8U)
#define ICR120_IL1_BITMASK            (0x10U)
#define ICR120_IL2_BITMASK            (0x20U)
#define ICR120_IP_GRPMASK             (0x7U)
#define ICR120_IP_GRPPOS              (0U)
#define ICR120_IL_GRPMASK             (0x38U)
#define ICR120_IL_GRPPOS              (0x3U)

/*** ICR121 - Interrupt Control Register 21.; 0x00000D55 ***/
#define ICR121                        (*((volatile uint8 *)(&__IPSBAR[0x00000D55UL])))
#define ICR121_IP0_BITMASK            (0x1U)
#define ICR121_IP1_BITMASK            (0x2U)
#define ICR121_IP2_BITMASK            (0x4U)
#define ICR121_IL0_BITMASK            (0x8U)
#define ICR121_IL1_BITMASK            (0x10U)
#define ICR121_IL2_BITMASK            (0x20U)
#define ICR121_IP_GRPMASK             (0x7U)
#define ICR121_IP_GRPPOS              (0U)
#define ICR121_IL_GRPMASK             (0x38U)
#define ICR121_IL_GRPPOS              (0x3U)

/*** ICR122 - Interrupt Control Register 22.; 0x00000D56 ***/
#define ICR122                        (*((volatile uint8 *)(&__IPSBAR[0x00000D56UL])))
#define ICR122_IP0_BITMASK            (0x1U)
#define ICR122_IP1_BITMASK            (0x2U)
#define ICR122_IP2_BITMASK            (0x4U)
#define ICR122_IL0_BITMASK            (0x8U)
#define ICR122_IL1_BITMASK            (0x10U)
#define ICR122_IL2_BITMASK            (0x20U)
#define ICR122_IP_GRPMASK             (0x7U)
#define ICR122_IP_GRPPOS              (0U)
#define ICR122_IL_GRPMASK             (0x38U)
#define ICR122_IL_GRPPOS              (0x3U)

/*** ICR123 - Interrupt Control Register 23.; 0x00000D57 ***/
#define ICR123                        (*((volatile uint8 *)(&__IPSBAR[0x00000D57UL])))
#define ICR123_IP0_BITMASK            (0x1U)
#define ICR123_IP1_BITMASK            (0x2U)
#define ICR123_IP2_BITMASK            (0x4U)
#define ICR123_IL0_BITMASK            (0x8U)
#define ICR123_IL1_BITMASK            (0x10U)
#define ICR123_IL2_BITMASK            (0x20U)
#define ICR123_IP_GRPMASK             (0x7U)
#define ICR123_IP_GRPPOS              (0U)
#define ICR123_IL_GRPMASK             (0x38U)
#define ICR123_IL_GRPPOS              (0x3U)

/*** ICR124 - Interrupt Control Register 24.; 0x00000D58 ***/
#define ICR124                        (*((volatile uint8 *)(&__IPSBAR[0x00000D58UL])))
#define ICR124_IP0_BITMASK            (0x1U)
#define ICR124_IP1_BITMASK            (0x2U)
#define ICR124_IP2_BITMASK            (0x4U)
#define ICR124_IL0_BITMASK            (0x8U)
#define ICR124_IL1_BITMASK            (0x10U)
#define ICR124_IL2_BITMASK            (0x20U)
#define ICR124_IP_GRPMASK             (0x7U)
#define ICR124_IP_GRPPOS              (0U)
#define ICR124_IL_GRPMASK             (0x38U)
#define ICR124_IL_GRPPOS              (0x3U)

/*** ICR125 - Interrupt Control Register 25.; 0x00000D59 ***/
#define ICR125                        (*((volatile uint8 *)(&__IPSBAR[0x00000D59UL])))
#define ICR125_IP0_BITMASK            (0x1U)
#define ICR125_IP1_BITMASK            (0x2U)
#define ICR125_IP2_BITMASK            (0x4U)
#define ICR125_IL0_BITMASK            (0x8U)
#define ICR125_IL1_BITMASK            (0x10U)
#define ICR125_IL2_BITMASK            (0x20U)
#define ICR125_IP_GRPMASK             (0x7U)
#define ICR125_IP_GRPPOS              (0U)
#define ICR125_IL_GRPMASK             (0x38U)
#define ICR125_IL_GRPPOS              (0x3U)

/*** ICR126 - Interrupt Control Register 26.; 0x00000D5A ***/
#define ICR126                        (*((volatile uint8 *)(&__IPSBAR[0x00000D5AUL])))
#define ICR126_IP0_BITMASK            (0x1U)
#define ICR126_IP1_BITMASK            (0x2U)
#define ICR126_IP2_BITMASK            (0x4U)
#define ICR126_IL0_BITMASK            (0x8U)
#define ICR126_IL1_BITMASK            (0x10U)
#define ICR126_IL2_BITMASK            (0x20U)
#define ICR126_IP_GRPMASK             (0x7U)
#define ICR126_IP_GRPPOS              (0U)
#define ICR126_IL_GRPMASK             (0x38U)
#define ICR126_IL_GRPPOS              (0x3U)

/*** ICR127 - Interrupt Control Register 27.; 0x00000D5B ***/
#define ICR127                        (*((volatile uint8 *)(&__IPSBAR[0x00000D5BUL])))
#define ICR127_IP0_BITMASK            (0x1U)
#define ICR127_IP1_BITMASK            (0x2U)
#define ICR127_IP2_BITMASK            (0x4U)
#define ICR127_IL0_BITMASK            (0x8U)
#define ICR127_IL1_BITMASK            (0x10U)
#define ICR127_IL2_BITMASK            (0x20U)
#define ICR127_IP_GRPMASK             (0x7U)
#define ICR127_IP_GRPPOS              (0U)
#define ICR127_IL_GRPMASK             (0x38U)
#define ICR127_IL_GRPPOS              (0x3U)

/*** ICR128 - Interrupt Control Register 28.; 0x00000D5C ***/
#define ICR128                        (*((volatile uint8 *)(&__IPSBAR[0x00000D5CUL])))
#define ICR128_IP0_BITMASK            (0x1U)
#define ICR128_IP1_BITMASK            (0x2U)
#define ICR128_IP2_BITMASK            (0x4U)
#define ICR128_IL0_BITMASK            (0x8U)
#define ICR128_IL1_BITMASK            (0x10U)
#define ICR128_IL2_BITMASK            (0x20U)
#define ICR128_IP_GRPMASK             (0x7U)
#define ICR128_IP_GRPPOS              (0U)
#define ICR128_IL_GRPMASK             (0x38U)
#define ICR128_IL_GRPPOS              (0x3U)

/*** ICR129 - Interrupt Control Register 29.; 0x00000D5D ***/
#define ICR129                        (*((volatile uint8 *)(&__IPSBAR[0x00000D5DUL])))
#define ICR129_IP0_BITMASK            (0x1U)
#define ICR129_IP1_BITMASK            (0x2U)
#define ICR129_IP2_BITMASK            (0x4U)
#define ICR129_IL0_BITMASK            (0x8U)
#define ICR129_IL1_BITMASK            (0x10U)
#define ICR129_IL2_BITMASK            (0x20U)
#define ICR129_IP_GRPMASK             (0x7U)
#define ICR129_IP_GRPPOS              (0U)
#define ICR129_IL_GRPMASK             (0x38U)
#define ICR129_IL_GRPPOS              (0x3U)

/*** ICR130 - Interrupt Control Register 30.; 0x00000D5E ***/
#define ICR130                        (*((volatile uint8 *)(&__IPSBAR[0x00000D5EUL])))
#define ICR130_IP0_BITMASK            (0x1U)
#define ICR130_IP1_BITMASK            (0x2U)
#define ICR130_IP2_BITMASK            (0x4U)
#define ICR130_IL0_BITMASK            (0x8U)
#define ICR130_IL1_BITMASK            (0x10U)
#define ICR130_IL2_BITMASK            (0x20U)
#define ICR130_IP_GRPMASK             (0x7U)
#define ICR130_IP_GRPPOS              (0U)
#define ICR130_IL_GRPMASK             (0x38U)
#define ICR130_IL_GRPPOS              (0x3U)

/*** ICR131 - Interrupt Control Register 31.; 0x00000D5F ***/
#define ICR131                        (*((volatile uint8 *)(&__IPSBAR[0x00000D5FUL])))
#define ICR131_IP0_BITMASK            (0x1U)
#define ICR131_IP1_BITMASK            (0x2U)
#define ICR131_IP2_BITMASK            (0x4U)
#define ICR131_IL0_BITMASK            (0x8U)
#define ICR131_IL1_BITMASK            (0x10U)
#define ICR131_IL2_BITMASK            (0x20U)
#define ICR131_IP_GRPMASK             (0x7U)
#define ICR131_IP_GRPPOS              (0U)
#define ICR131_IL_GRPMASK             (0x38U)
#define ICR131_IL_GRPPOS              (0x3U)

/*** ICR132 - Interrupt Control Register 32.; 0x00000D60 ***/
#define ICR132                        (*((volatile uint8 *)(&__IPSBAR[0x00000D60UL])))
#define ICR132_IP0_BITMASK            (0x1U)
#define ICR132_IP1_BITMASK            (0x2U)
#define ICR132_IP2_BITMASK            (0x4U)
#define ICR132_IL0_BITMASK            (0x8U)
#define ICR132_IL1_BITMASK            (0x10U)
#define ICR132_IL2_BITMASK            (0x20U)
#define ICR132_IP_GRPMASK             (0x7U)
#define ICR132_IP_GRPPOS              (0U)
#define ICR132_IL_GRPMASK             (0x38U)
#define ICR132_IL_GRPPOS              (0x3U)

/*** ICR133 - Interrupt Control Register 33.; 0x00000D61 ***/
#define ICR133                        (*((volatile uint8 *)(&__IPSBAR[0x00000D61UL])))
#define ICR133_IP0_BITMASK            (0x1U)
#define ICR133_IP1_BITMASK            (0x2U)
#define ICR133_IP2_BITMASK            (0x4U)
#define ICR133_IL0_BITMASK            (0x8U)
#define ICR133_IL1_BITMASK            (0x10U)
#define ICR133_IL2_BITMASK            (0x20U)
#define ICR133_IP_GRPMASK             (0x7U)
#define ICR133_IP_GRPPOS              (0U)
#define ICR133_IL_GRPMASK             (0x38U)
#define ICR133_IL_GRPPOS              (0x3U)

/*** ICR134 - Interrupt Control Register 34.; 0x00000D62 ***/
#define ICR134                        (*((volatile uint8 *)(&__IPSBAR[0x00000D62UL])))
#define ICR134_IP0_BITMASK            (0x1U)
#define ICR134_IP1_BITMASK            (0x2U)
#define ICR134_IP2_BITMASK            (0x4U)
#define ICR134_IL0_BITMASK            (0x8U)
#define ICR134_IL1_BITMASK            (0x10U)
#define ICR134_IL2_BITMASK            (0x20U)
#define ICR134_IP_GRPMASK             (0x7U)
#define ICR134_IP_GRPPOS              (0U)
#define ICR134_IL_GRPMASK             (0x38U)
#define ICR134_IL_GRPPOS              (0x3U)

/*** ICR135 - Interrupt Control Register 35.; 0x00000D63 ***/
#define ICR135                        (*((volatile uint8 *)(&__IPSBAR[0x00000D63UL])))
#define ICR135_IP0_BITMASK            (0x1U)
#define ICR135_IP1_BITMASK            (0x2U)
#define ICR135_IP2_BITMASK            (0x4U)
#define ICR135_IL0_BITMASK            (0x8U)
#define ICR135_IL1_BITMASK            (0x10U)
#define ICR135_IL2_BITMASK            (0x20U)
#define ICR135_IP_GRPMASK             (0x7U)
#define ICR135_IP_GRPPOS              (0U)
#define ICR135_IL_GRPMASK             (0x38U)
#define ICR135_IL_GRPPOS              (0x3U)

/*** ICR136 - Interrupt Control Register 36.; 0x00000D64 ***/
#define ICR136                        (*((volatile uint8 *)(&__IPSBAR[0x00000D64UL])))
#define ICR136_IP0_BITMASK            (0x1U)
#define ICR136_IP1_BITMASK            (0x2U)
#define ICR136_IP2_BITMASK            (0x4U)
#define ICR136_IL0_BITMASK            (0x8U)
#define ICR136_IL1_BITMASK            (0x10U)
#define ICR136_IL2_BITMASK            (0x20U)
#define ICR136_IP_GRPMASK             (0x7U)
#define ICR136_IP_GRPPOS              (0U)
#define ICR136_IL_GRPMASK             (0x38U)
#define ICR136_IL_GRPPOS              (0x3U)

/*** ICR137 - Interrupt Control Register 37.; 0x00000D65 ***/
#define ICR137                        (*((volatile uint8 *)(&__IPSBAR[0x00000D65UL])))
#define ICR137_IP0_BITMASK            (0x1U)
#define ICR137_IP1_BITMASK            (0x2U)
#define ICR137_IP2_BITMASK            (0x4U)
#define ICR137_IL0_BITMASK            (0x8U)
#define ICR137_IL1_BITMASK            (0x10U)
#define ICR137_IL2_BITMASK            (0x20U)
#define ICR137_IP_GRPMASK             (0x7U)
#define ICR137_IP_GRPPOS              (0U)
#define ICR137_IL_GRPMASK             (0x38U)
#define ICR137_IL_GRPPOS              (0x3U)

/*** ICR138 - Interrupt Control Register 38.; 0x00000D66 ***/
#define ICR138                        (*((volatile uint8 *)(&__IPSBAR[0x00000D66UL])))
#define ICR138_IP0_BITMASK            (0x1U)
#define ICR138_IP1_BITMASK            (0x2U)
#define ICR138_IP2_BITMASK            (0x4U)
#define ICR138_IL0_BITMASK            (0x8U)
#define ICR138_IL1_BITMASK            (0x10U)
#define ICR138_IL2_BITMASK            (0x20U)
#define ICR138_IP_GRPMASK             (0x7U)
#define ICR138_IP_GRPPOS              (0U)
#define ICR138_IL_GRPMASK             (0x38U)
#define ICR138_IL_GRPPOS              (0x3U)

/*** ICR139 - Interrupt Control Register 39.; 0x00000D67 ***/
#define ICR139                        (*((volatile uint8 *)(&__IPSBAR[0x00000D67UL])))
#define ICR139_IP0_BITMASK            (0x1U)
#define ICR139_IP1_BITMASK            (0x2U)
#define ICR139_IP2_BITMASK            (0x4U)
#define ICR139_IL0_BITMASK            (0x8U)
#define ICR139_IL1_BITMASK            (0x10U)
#define ICR139_IL2_BITMASK            (0x20U)
#define ICR139_IP_GRPMASK             (0x7U)
#define ICR139_IP_GRPPOS              (0U)
#define ICR139_IL_GRPMASK             (0x38U)
#define ICR139_IL_GRPPOS              (0x3U)

/*** ICR140 - Interrupt Control Register 40.; 0x00000D68 ***/
#define ICR140                        (*((volatile uint8 *)(&__IPSBAR[0x00000D68UL])))
#define ICR140_IP0_BITMASK            (0x1U)
#define ICR140_IP1_BITMASK            (0x2U)
#define ICR140_IP2_BITMASK            (0x4U)
#define ICR140_IL0_BITMASK            (0x8U)
#define ICR140_IL1_BITMASK            (0x10U)
#define ICR140_IL2_BITMASK            (0x20U)
#define ICR140_IP_GRPMASK             (0x7U)
#define ICR140_IP_GRPPOS              (0U)
#define ICR140_IL_GRPMASK             (0x38U)
#define ICR140_IL_GRPPOS              (0x3U)

/*** ICR141 - Interrupt Control Register 41.; 0x00000D69 ***/
#define ICR141                        (*((volatile uint8 *)(&__IPSBAR[0x00000D69UL])))
#define ICR141_IP0_BITMASK            (0x1U)
#define ICR141_IP1_BITMASK            (0x2U)
#define ICR141_IP2_BITMASK            (0x4U)
#define ICR141_IL0_BITMASK            (0x8U)
#define ICR141_IL1_BITMASK            (0x10U)
#define ICR141_IL2_BITMASK            (0x20U)
#define ICR141_IP_GRPMASK             (0x7U)
#define ICR141_IP_GRPPOS              (0U)
#define ICR141_IL_GRPMASK             (0x38U)
#define ICR141_IL_GRPPOS              (0x3U)

/*** ICR142 - Interrupt Control Register 42.; 0x00000D6A ***/
#define ICR142                        (*((volatile uint8 *)(&__IPSBAR[0x00000D6AUL])))
#define ICR142_IP0_BITMASK            (0x1U)
#define ICR142_IP1_BITMASK            (0x2U)
#define ICR142_IP2_BITMASK            (0x4U)
#define ICR142_IL0_BITMASK            (0x8U)
#define ICR142_IL1_BITMASK            (0x10U)
#define ICR142_IL2_BITMASK            (0x20U)
#define ICR142_IP_GRPMASK             (0x7U)
#define ICR142_IP_GRPPOS              (0U)
#define ICR142_IL_GRPMASK             (0x38U)
#define ICR142_IL_GRPPOS              (0x3U)

/*** ICR143 - Interrupt Control Register 43.; 0x00000D6B ***/
#define ICR143                        (*((volatile uint8 *)(&__IPSBAR[0x00000D6BUL])))
#define ICR143_IP0_BITMASK            (0x1U)
#define ICR143_IP1_BITMASK            (0x2U)
#define ICR143_IP2_BITMASK            (0x4U)
#define ICR143_IL0_BITMASK            (0x8U)
#define ICR143_IL1_BITMASK            (0x10U)
#define ICR143_IL2_BITMASK            (0x20U)
#define ICR143_IP_GRPMASK             (0x7U)
#define ICR143_IP_GRPPOS              (0U)
#define ICR143_IL_GRPMASK             (0x38U)
#define ICR143_IL_GRPPOS              (0x3U)

/*** ICR144 - Interrupt Control Register 44.; 0x00000D6C ***/
#define ICR144                        (*((volatile uint8 *)(&__IPSBAR[0x00000D6CUL])))
#define ICR144_IP0_BITMASK            (0x1U)
#define ICR144_IP1_BITMASK            (0x2U)
#define ICR144_IP2_BITMASK            (0x4U)
#define ICR144_IL0_BITMASK            (0x8U)
#define ICR144_IL1_BITMASK            (0x10U)
#define ICR144_IL2_BITMASK            (0x20U)
#define ICR144_IP_GRPMASK             (0x7U)
#define ICR144_IP_GRPPOS              (0U)
#define ICR144_IL_GRPMASK             (0x38U)
#define ICR144_IL_GRPPOS              (0x3U)

/*** ICR145 - Interrupt Control Register 45.; 0x00000D6D ***/
#define ICR145                        (*((volatile uint8 *)(&__IPSBAR[0x00000D6DUL])))
#define ICR145_IP0_BITMASK            (0x1U)
#define ICR145_IP1_BITMASK            (0x2U)
#define ICR145_IP2_BITMASK            (0x4U)
#define ICR145_IL0_BITMASK            (0x8U)
#define ICR145_IL1_BITMASK            (0x10U)
#define ICR145_IL2_BITMASK            (0x20U)
#define ICR145_IP_GRPMASK             (0x7U)
#define ICR145_IP_GRPPOS              (0U)
#define ICR145_IL_GRPMASK             (0x38U)
#define ICR145_IL_GRPPOS              (0x3U)

/*** ICR146 - Interrupt Control Register 46.; 0x00000D6E ***/
#define ICR146                        (*((volatile uint8 *)(&__IPSBAR[0x00000D6EUL])))
#define ICR146_IP0_BITMASK            (0x1U)
#define ICR146_IP1_BITMASK            (0x2U)
#define ICR146_IP2_BITMASK            (0x4U)
#define ICR146_IL0_BITMASK            (0x8U)
#define ICR146_IL1_BITMASK            (0x10U)
#define ICR146_IL2_BITMASK            (0x20U)
#define ICR146_IP_GRPMASK             (0x7U)
#define ICR146_IP_GRPPOS              (0U)
#define ICR146_IL_GRPMASK             (0x38U)
#define ICR146_IL_GRPPOS              (0x3U)

/*** ICR147 - Interrupt Control Register 47.; 0x00000D6F ***/
#define ICR147                        (*((volatile uint8 *)(&__IPSBAR[0x00000D6FUL])))
#define ICR147_IP0_BITMASK            (0x1U)
#define ICR147_IP1_BITMASK            (0x2U)
#define ICR147_IP2_BITMASK            (0x4U)
#define ICR147_IL0_BITMASK            (0x8U)
#define ICR147_IL1_BITMASK            (0x10U)
#define ICR147_IL2_BITMASK            (0x20U)
#define ICR147_IP_GRPMASK             (0x7U)
#define ICR147_IP_GRPPOS              (0U)
#define ICR147_IL_GRPMASK             (0x38U)
#define ICR147_IL_GRPPOS              (0x3U)

/*** ICR148 - Interrupt Control Register 48.; 0x00000D70 ***/
#define ICR148                        (*((volatile uint8 *)(&__IPSBAR[0x00000D70UL])))
#define ICR148_IP0_BITMASK            (0x1U)
#define ICR148_IP1_BITMASK            (0x2U)
#define ICR148_IP2_BITMASK            (0x4U)
#define ICR148_IL0_BITMASK            (0x8U)
#define ICR148_IL1_BITMASK            (0x10U)
#define ICR148_IL2_BITMASK            (0x20U)
#define ICR148_IP_GRPMASK             (0x7U)
#define ICR148_IP_GRPPOS              (0U)
#define ICR148_IL_GRPMASK             (0x38U)
#define ICR148_IL_GRPPOS              (0x3U)

/*** ICR149 - Interrupt Control Register 49.; 0x00000D71 ***/
#define ICR149                        (*((volatile uint8 *)(&__IPSBAR[0x00000D71UL])))
#define ICR149_IP0_BITMASK            (0x1U)
#define ICR149_IP1_BITMASK            (0x2U)
#define ICR149_IP2_BITMASK            (0x4U)
#define ICR149_IL0_BITMASK            (0x8U)
#define ICR149_IL1_BITMASK            (0x10U)
#define ICR149_IL2_BITMASK            (0x20U)
#define ICR149_IP_GRPMASK             (0x7U)
#define ICR149_IP_GRPPOS              (0U)
#define ICR149_IL_GRPMASK             (0x38U)
#define ICR149_IL_GRPPOS              (0x3U)

/*** ICR150 - Interrupt Control Register 50.; 0x00000D72 ***/
#define ICR150                        (*((volatile uint8 *)(&__IPSBAR[0x00000D72UL])))
#define ICR150_IP0_BITMASK            (0x1U)
#define ICR150_IP1_BITMASK            (0x2U)
#define ICR150_IP2_BITMASK            (0x4U)
#define ICR150_IL0_BITMASK            (0x8U)
#define ICR150_IL1_BITMASK            (0x10U)
#define ICR150_IL2_BITMASK            (0x20U)
#define ICR150_IP_GRPMASK             (0x7U)
#define ICR150_IP_GRPPOS              (0U)
#define ICR150_IL_GRPMASK             (0x38U)
#define ICR150_IL_GRPPOS              (0x3U)

/*** ICR151 - Interrupt Control Register 51.; 0x00000D73 ***/
#define ICR151                        (*((volatile uint8 *)(&__IPSBAR[0x00000D73UL])))
#define ICR151_IP0_BITMASK            (0x1U)
#define ICR151_IP1_BITMASK            (0x2U)
#define ICR151_IP2_BITMASK            (0x4U)
#define ICR151_IL0_BITMASK            (0x8U)
#define ICR151_IL1_BITMASK            (0x10U)
#define ICR151_IL2_BITMASK            (0x20U)
#define ICR151_IP_GRPMASK             (0x7U)
#define ICR151_IP_GRPPOS              (0U)
#define ICR151_IL_GRPMASK             (0x38U)
#define ICR151_IL_GRPPOS              (0x3U)

/*** ICR152 - Interrupt Control Register 52.; 0x00000D74 ***/
#define ICR152                        (*((volatile uint8 *)(&__IPSBAR[0x00000D74UL])))
#define ICR152_IP0_BITMASK            (0x1U)
#define ICR152_IP1_BITMASK            (0x2U)
#define ICR152_IP2_BITMASK            (0x4U)
#define ICR152_IL0_BITMASK            (0x8U)
#define ICR152_IL1_BITMASK            (0x10U)
#define ICR152_IL2_BITMASK            (0x20U)
#define ICR152_IP_GRPMASK             (0x7U)
#define ICR152_IP_GRPPOS              (0U)
#define ICR152_IL_GRPMASK             (0x38U)
#define ICR152_IL_GRPPOS              (0x3U)

/*** ICR153 - Interrupt Control Register 53.; 0x00000D75 ***/
#define ICR153                        (*((volatile uint8 *)(&__IPSBAR[0x00000D75UL])))
#define ICR153_IP0_BITMASK            (0x1U)
#define ICR153_IP1_BITMASK            (0x2U)
#define ICR153_IP2_BITMASK            (0x4U)
#define ICR153_IL0_BITMASK            (0x8U)
#define ICR153_IL1_BITMASK            (0x10U)
#define ICR153_IL2_BITMASK            (0x20U)
#define ICR153_IP_GRPMASK             (0x7U)
#define ICR153_IP_GRPPOS              (0U)
#define ICR153_IL_GRPMASK             (0x38U)
#define ICR153_IL_GRPPOS              (0x3U)

/*** ICR154 - Interrupt Control Register 54.; 0x00000D76 ***/
#define ICR154                        (*((volatile uint8 *)(&__IPSBAR[0x00000D76UL])))
#define ICR154_IP0_BITMASK            (0x1U)
#define ICR154_IP1_BITMASK            (0x2U)
#define ICR154_IP2_BITMASK            (0x4U)
#define ICR154_IL0_BITMASK            (0x8U)
#define ICR154_IL1_BITMASK            (0x10U)
#define ICR154_IL2_BITMASK            (0x20U)
#define ICR154_IP_GRPMASK             (0x7U)
#define ICR154_IP_GRPPOS              (0U)
#define ICR154_IL_GRPMASK             (0x38U)
#define ICR154_IL_GRPPOS              (0x3U)

/*** ICR155 - Interrupt Control Register 55.; 0x00000D77 ***/
#define ICR155                        (*((volatile uint8 *)(&__IPSBAR[0x00000D77UL])))
#define ICR155_IP0_BITMASK            (0x1U)
#define ICR155_IP1_BITMASK            (0x2U)
#define ICR155_IP2_BITMASK            (0x4U)
#define ICR155_IL0_BITMASK            (0x8U)
#define ICR155_IL1_BITMASK            (0x10U)
#define ICR155_IL2_BITMASK            (0x20U)
#define ICR155_IP_GRPMASK             (0x7U)
#define ICR155_IP_GRPPOS              (0U)
#define ICR155_IL_GRPMASK             (0x38U)
#define ICR155_IL_GRPPOS              (0x3U)

/*** ICR156 - Interrupt Control Register 56.; 0x00000D78 ***/
#define ICR156                        (*((volatile uint8 *)(&__IPSBAR[0x00000D78UL])))
#define ICR156_IP0_BITMASK            (0x1U)
#define ICR156_IP1_BITMASK            (0x2U)
#define ICR156_IP2_BITMASK            (0x4U)
#define ICR156_IL0_BITMASK            (0x8U)
#define ICR156_IL1_BITMASK            (0x10U)
#define ICR156_IL2_BITMASK            (0x20U)
#define ICR156_IP_GRPMASK             (0x7U)
#define ICR156_IP_GRPPOS              (0U)
#define ICR156_IL_GRPMASK             (0x38U)
#define ICR156_IL_GRPPOS              (0x3U)

/*** ICR157 - Interrupt Control Register 57.; 0x00000D79 ***/
#define ICR157                        (*((volatile uint8 *)(&__IPSBAR[0x00000D79UL])))
#define ICR157_IP0_BITMASK            (0x1U)
#define ICR157_IP1_BITMASK            (0x2U)
#define ICR157_IP2_BITMASK            (0x4U)
#define ICR157_IL0_BITMASK            (0x8U)
#define ICR157_IL1_BITMASK            (0x10U)
#define ICR157_IL2_BITMASK            (0x20U)
#define ICR157_IP_GRPMASK             (0x7U)
#define ICR157_IP_GRPPOS              (0U)
#define ICR157_IL_GRPMASK             (0x38U)
#define ICR157_IL_GRPPOS              (0x3U)

/*** ICR158 - Interrupt Control Register 58.; 0x00000D7A ***/
#define ICR158                        (*((volatile uint8 *)(&__IPSBAR[0x00000D7AUL])))
#define ICR158_IP0_BITMASK            (0x1U)
#define ICR158_IP1_BITMASK            (0x2U)
#define ICR158_IP2_BITMASK            (0x4U)
#define ICR158_IL0_BITMASK            (0x8U)
#define ICR158_IL1_BITMASK            (0x10U)
#define ICR158_IL2_BITMASK            (0x20U)
#define ICR158_IP_GRPMASK             (0x7U)
#define ICR158_IP_GRPPOS              (0U)
#define ICR158_IL_GRPMASK             (0x38U)
#define ICR158_IL_GRPPOS              (0x3U)

/*** ICR159 - Interrupt Control Register 59.; 0x00000D7B ***/
#define ICR159                        (*((volatile uint8 *)(&__IPSBAR[0x00000D7BUL])))
#define ICR159_IP0_BITMASK            (0x1U)
#define ICR159_IP1_BITMASK            (0x2U)
#define ICR159_IP2_BITMASK            (0x4U)
#define ICR159_IL0_BITMASK            (0x8U)
#define ICR159_IL1_BITMASK            (0x10U)
#define ICR159_IL2_BITMASK            (0x20U)
#define ICR159_IP_GRPMASK             (0x7U)
#define ICR159_IP_GRPPOS              (0U)
#define ICR159_IL_GRPMASK             (0x38U)
#define ICR159_IL_GRPPOS              (0x3U)

/*** ICR160 - Interrupt Control Register 60.; 0x00000D7C ***/
#define ICR160                        (*((volatile uint8 *)(&__IPSBAR[0x00000D7CUL])))
#define ICR160_IP0_BITMASK            (0x1U)
#define ICR160_IP1_BITMASK            (0x2U)
#define ICR160_IP2_BITMASK            (0x4U)
#define ICR160_IL0_BITMASK            (0x8U)
#define ICR160_IL1_BITMASK            (0x10U)
#define ICR160_IL2_BITMASK            (0x20U)
#define ICR160_IP_GRPMASK             (0x7U)
#define ICR160_IP_GRPPOS              (0U)
#define ICR160_IL_GRPMASK             (0x38U)
#define ICR160_IL_GRPPOS              (0x3U)

/*** ICR161 - Interrupt Control Register 61.; 0x00000D7D ***/
#define ICR161                        (*((volatile uint8 *)(&__IPSBAR[0x00000D7DUL])))
#define ICR161_IP0_BITMASK            (0x1U)
#define ICR161_IP1_BITMASK            (0x2U)
#define ICR161_IP2_BITMASK            (0x4U)
#define ICR161_IL0_BITMASK            (0x8U)
#define ICR161_IL1_BITMASK            (0x10U)
#define ICR161_IL2_BITMASK            (0x20U)
#define ICR161_IP_GRPMASK             (0x7U)
#define ICR161_IP_GRPPOS              (0U)
#define ICR161_IL_GRPMASK             (0x38U)
#define ICR161_IL_GRPPOS              (0x3U)

/*** ICR162 - Interrupt Control Register 62.; 0x00000D7E ***/
#define ICR162                        (*((volatile uint8 *)(&__IPSBAR[0x00000D7EUL])))
#define ICR162_IP0_BITMASK            (0x1U)
#define ICR162_IP1_BITMASK            (0x2U)
#define ICR162_IP2_BITMASK            (0x4U)
#define ICR162_IL0_BITMASK            (0x8U)
#define ICR162_IL1_BITMASK            (0x10U)
#define ICR162_IL2_BITMASK            (0x20U)
#define ICR162_IP_GRPMASK             (0x7U)
#define ICR162_IP_GRPPOS              (0U)
#define ICR162_IL_GRPMASK             (0x38U)
#define ICR162_IL_GRPPOS              (0x3U)

/*** ICR163 - Interrupt Control Register 63.; 0x00000D7F ***/
#define ICR163                        (*((volatile uint8 *)(&__IPSBAR[0x00000D7FUL])))
#define ICR163_IP0_BITMASK            (0x1U)
#define ICR163_IP1_BITMASK            (0x2U)
#define ICR163_IP2_BITMASK            (0x4U)
#define ICR163_IL0_BITMASK            (0x8U)
#define ICR163_IL1_BITMASK            (0x10U)
#define ICR163_IL2_BITMASK            (0x20U)
#define ICR163_IP_GRPMASK             (0x7U)
#define ICR163_IP_GRPPOS              (0U)
#define ICR163_IL_GRPMASK             (0x38U)
#define ICR163_IL_GRPPOS              (0x3U)

/*** SWIACK1 - Software IACK Register.; 0x00000DE0 ***/
#define SWIACK1                       (*((volatile uint8 *)(&__IPSBAR[0x00000DE0UL])))
#define SWIACK1_VECTOR0_BITMASK       (0x1U)
#define SWIACK1_VECTOR1_BITMASK       (0x2U)
#define SWIACK1_VECTOR2_BITMASK       (0x4U)
#define SWIACK1_VECTOR3_BITMASK       (0x8U)
#define SWIACK1_VECTOR4_BITMASK       (0x10U)
#define SWIACK1_VECTOR5_BITMASK       (0x20U)
#define SWIACK1_VECTOR6_BITMASK       (0x40U)
#define SWIACK1_VECTOR7_BITMASK       (0x80U)
#define SWIACK1_VECTOR_GRPMASK        (0xFFU)
#define SWIACK1_VECTOR_GRPPOS         (0U)

/*** L1IACK1 - Level 1 IACK Register.; 0x00000DE4 ***/
#define L1IACK1                       (*((volatile uint8 *)(&__IPSBAR[0x00000DE4UL])))
#define L1IACK1_VECTOR0_BITMASK       (0x1U)
#define L1IACK1_VECTOR1_BITMASK       (0x2U)
#define L1IACK1_VECTOR2_BITMASK       (0x4U)
#define L1IACK1_VECTOR3_BITMASK       (0x8U)
#define L1IACK1_VECTOR4_BITMASK       (0x10U)
#define L1IACK1_VECTOR5_BITMASK       (0x20U)
#define L1IACK1_VECTOR6_BITMASK       (0x40U)
#define L1IACK1_VECTOR7_BITMASK       (0x80U)
#define L1IACK1_VECTOR_GRPMASK        (0xFFU)
#define L1IACK1_VECTOR_GRPPOS         (0U)

/*** L2IACK1 - Level 2 IACK Register.; 0x00000DE8 ***/
#define L2IACK1                       (*((volatile uint8 *)(&__IPSBAR[0x00000DE8UL])))
#define L2IACK1_VECTOR0_BITMASK       (0x1U)
#define L2IACK1_VECTOR1_BITMASK       (0x2U)
#define L2IACK1_VECTOR2_BITMASK       (0x4U)
#define L2IACK1_VECTOR3_BITMASK       (0x8U)
#define L2IACK1_VECTOR4_BITMASK       (0x10U)
#define L2IACK1_VECTOR5_BITMASK       (0x20U)
#define L2IACK1_VECTOR6_BITMASK       (0x40U)
#define L2IACK1_VECTOR7_BITMASK       (0x80U)
#define L2IACK1_VECTOR_GRPMASK        (0xFFU)
#define L2IACK1_VECTOR_GRPPOS         (0U)

/*** L3IACK1 - Level 3 IACK Register.; 0x00000DEC ***/
#define L3IACK1                       (*((volatile uint8 *)(&__IPSBAR[0x00000DECUL])))
#define L3IACK1_VECTOR0_BITMASK       (0x1U)
#define L3IACK1_VECTOR1_BITMASK       (0x2U)
#define L3IACK1_VECTOR2_BITMASK       (0x4U)
#define L3IACK1_VECTOR3_BITMASK       (0x8U)
#define L3IACK1_VECTOR4_BITMASK       (0x10U)
#define L3IACK1_VECTOR5_BITMASK       (0x20U)
#define L3IACK1_VECTOR6_BITMASK       (0x40U)
#define L3IACK1_VECTOR7_BITMASK       (0x80U)
#define L3IACK1_VECTOR_GRPMASK        (0xFFU)
#define L3IACK1_VECTOR_GRPPOS         (0U)

/*** L4IACK1 - Level 4 IACK Register.; 0x00000DF0 ***/
#define L4IACK1                       (*((volatile uint8 *)(&__IPSBAR[0x00000DF0UL])))
#define L4IACK1_VECTOR0_BITMASK       (0x1U)
#define L4IACK1_VECTOR1_BITMASK       (0x2U)
#define L4IACK1_VECTOR2_BITMASK       (0x4U)
#define L4IACK1_VECTOR3_BITMASK       (0x8U)
#define L4IACK1_VECTOR4_BITMASK       (0x10U)
#define L4IACK1_VECTOR5_BITMASK       (0x20U)
#define L4IACK1_VECTOR6_BITMASK       (0x40U)
#define L4IACK1_VECTOR7_BITMASK       (0x80U)
#define L4IACK1_VECTOR_GRPMASK        (0xFFU)
#define L4IACK1_VECTOR_GRPPOS         (0U)

/*** L5IACK1 - Level 5 IACK Register.; 0x00000DF4 ***/
#define L5IACK1                       (*((volatile uint8 *)(&__IPSBAR[0x00000DF4UL])))
#define L5IACK1_VECTOR0_BITMASK       (0x1U)
#define L5IACK1_VECTOR1_BITMASK       (0x2U)
#define L5IACK1_VECTOR2_BITMASK       (0x4U)
#define L5IACK1_VECTOR3_BITMASK       (0x8U)
#define L5IACK1_VECTOR4_BITMASK       (0x10U)
#define L5IACK1_VECTOR5_BITMASK       (0x20U)
#define L5IACK1_VECTOR6_BITMASK       (0x40U)
#define L5IACK1_VECTOR7_BITMASK       (0x80U)
#define L5IACK1_VECTOR_GRPMASK        (0xFFU)
#define L5IACK1_VECTOR_GRPPOS         (0U)

/*** L6IACK1 - Level 6 IACK Register.; 0x00000DF8 ***/
#define L6IACK1                       (*((volatile uint8 *)(&__IPSBAR[0x00000DF8UL])))
#define L6IACK1_VECTOR0_BITMASK       (0x1U)
#define L6IACK1_VECTOR1_BITMASK       (0x2U)
#define L6IACK1_VECTOR2_BITMASK       (0x4U)
#define L6IACK1_VECTOR3_BITMASK       (0x8U)
#define L6IACK1_VECTOR4_BITMASK       (0x10U)
#define L6IACK1_VECTOR5_BITMASK       (0x20U)
#define L6IACK1_VECTOR6_BITMASK       (0x40U)
#define L6IACK1_VECTOR7_BITMASK       (0x80U)
#define L6IACK1_VECTOR_GRPMASK        (0xFFU)
#define L6IACK1_VECTOR_GRPPOS         (0U)

/*** L7IACK1 - Level 7 IACK Register.; 0x00000DFC ***/
#define L7IACK1                       (*((volatile uint8 *)(&__IPSBAR[0x00000DFCUL])))
#define L7IACK1_VECTOR0_BITMASK       (0x1U)
#define L7IACK1_VECTOR1_BITMASK       (0x2U)
#define L7IACK1_VECTOR2_BITMASK       (0x4U)
#define L7IACK1_VECTOR3_BITMASK       (0x8U)
#define L7IACK1_VECTOR4_BITMASK       (0x10U)
#define L7IACK1_VECTOR5_BITMASK       (0x20U)
#define L7IACK1_VECTOR6_BITMASK       (0x40U)
#define L7IACK1_VECTOR7_BITMASK       (0x80U)
#define L7IACK1_VECTOR_GRPMASK        (0xFFU)
#define L7IACK1_VECTOR_GRPPOS         (0U)


/******************************************
*** Peripheral FEC
*******************************************/

/*** EIR - Ethernet Interrupt Event Register.; 0x00001004 ***/
#define EIR                           (*((volatile uint32 *)(&__IPSBAR[0x00001004UL])))
#define EIR_UN_BITMASK                (0x80000U)
#define EIR_RL_BITMASK                (0x100000U)
#define EIR_LC_BITMASK                (0x200000U)
#define EIR_EBERR_BITMASK             (0x400000U)
#define EIR_MII_BITMASK               (0x800000U)
#define EIR_RXB_BITMASK               (0x1000000U)
#define EIR_RXF_BITMASK               (0x2000000U)
#define EIR_TXB_BITMASK               (0x4000000U)
#define EIR_TXF_BITMASK               (0x8000000U)
#define EIR_GRA_BITMASK               (0x10000000U)
#define EIR_BABT_BITMASK              (0x20000000U)
#define EIR_BABR_BITMASK              (0x40000000U)
#define EIR_HBERR_BITMASK             (0x80000000U)

/*** EIMR - Interrupt Mask Register.; 0x00001008 ***/
#define EIMR                          (*((volatile uint32 *)(&__IPSBAR[0x00001008UL])))
#define EIMR_UN_BITMASK               (0x80000U)
#define EIMR_RL_BITMASK               (0x100000U)
#define EIMR_LC_BITMASK               (0x200000U)
#define EIMR_EBERR_BITMASK            (0x400000U)
#define EIMR_MII_BITMASK              (0x800000U)
#define EIMR_RXB_BITMASK              (0x1000000U)
#define EIMR_RXF_BITMASK              (0x2000000U)
#define EIMR_TXB_BITMASK              (0x4000000U)
#define EIMR_TXF_BITMASK              (0x8000000U)
#define EIMR_GRA_BITMASK              (0x10000000U)
#define EIMR_BABT_BITMASK             (0x20000000U)
#define EIMR_BABR_BITMASK             (0x40000000U)
#define EIMR_HBERR_BITMASK            (0x80000000U)

/*** RDAR - Receive Descriptor Active Register.; 0x00001010 ***/
#define RDAR                          (*((volatile uint32 *)(&__IPSBAR[0x00001010UL])))
#define RDAR_R_DES_ACTIVE_BITMASK     (0x1000000U)

/*** TDAR - Transmit Descriptor Active Register.; 0x00001014 ***/
#define TDAR                          (*((volatile uint32 *)(&__IPSBAR[0x00001014UL])))
#define TDAR_X_DES_ACTIVE_BITMASK     (0x1000000U)

/*** ECR -  Ethernet Control Register.; 0x00001024 ***/
#define ECR                           (*((volatile uint32 *)(&__IPSBAR[0x00001024UL])))
#define ECR_RESET_BITMASK             (0x1U)
#define ECR_ETHER_EN_BITMASK          (0x2U)

/*** MMFR - MII Management Frame Register.; 0x00001040 ***/
#define MMFR                          (*((volatile uint32 *)(&__IPSBAR[0x00001040UL])))
#define MMFR_DATA0_BITMASK            (0x1U)
#define MMFR_DATA1_BITMASK            (0x2U)
#define MMFR_DATA2_BITMASK            (0x4U)
#define MMFR_DATA3_BITMASK            (0x8U)
#define MMFR_DATA4_BITMASK            (0x10U)
#define MMFR_DATA5_BITMASK            (0x20U)
#define MMFR_DATA6_BITMASK            (0x40U)
#define MMFR_DATA7_BITMASK            (0x80U)
#define MMFR_DATA8_BITMASK            (0x100U)
#define MMFR_DATA9_BITMASK            (0x200U)
#define MMFR_DATA10_BITMASK           (0x400U)
#define MMFR_DATA11_BITMASK           (0x800U)
#define MMFR_DATA12_BITMASK           (0x1000U)
#define MMFR_DATA13_BITMASK           (0x2000U)
#define MMFR_DATA14_BITMASK           (0x4000U)
#define MMFR_DATA15_BITMASK           (0x8000U)
#define MMFR_TA0_BITMASK              (0x10000U)
#define MMFR_TA1_BITMASK              (0x20000U)
#define MMFR_RA0_BITMASK              (0x40000U)
#define MMFR_RA1_BITMASK              (0x80000U)
#define MMFR_RA2_BITMASK              (0x100000U)
#define MMFR_RA3_BITMASK              (0x200000U)
#define MMFR_RA4_BITMASK              (0x400000U)
#define MMFR_PA0_BITMASK              (0x800000U)
#define MMFR_PA1_BITMASK              (0x1000000U)
#define MMFR_PA2_BITMASK              (0x2000000U)
#define MMFR_PA3_BITMASK              (0x4000000U)
#define MMFR_PA4_BITMASK              (0x8000000U)
#define MMFR_OP0_BITMASK              (0x10000000U)
#define MMFR_OP1_BITMASK              (0x20000000U)
#define MMFR_ST0_BITMASK              (0x40000000U)
#define MMFR_ST1_BITMASK              (0x80000000U)
#define MMFR_DATA_GRPMASK             (0xFFFFU)
#define MMFR_DATA_GRPPOS              (0U)
#define MMFR_TA_GRPMASK               (0x30000U)
#define MMFR_TA_GRPPOS                (0x10U)
#define MMFR_RA_GRPMASK               (0x7C0000U)
#define MMFR_RA_GRPPOS                (0x12U)
#define MMFR_PA_GRPMASK               (0xF800000U)
#define MMFR_PA_GRPPOS                (0x17U)
#define MMFR_OP_GRPMASK               (0x30000000U)
#define MMFR_OP_GRPPOS                (0x1CU)
#define MMFR_ST_GRPMASK               (0xC0000000U)
#define MMFR_ST_GRPPOS                (0x1EU)

/*** MSCR - MII Speed Control Register.; 0x00001044 ***/
#define MSCR                          (*((volatile uint32 *)(&__IPSBAR[0x00001044UL])))
#define MSCR_MII_SPEED0_BITMASK       (0x2U)
#define MSCR_MII_SPEED1_BITMASK       (0x4U)
#define MSCR_MII_SPEED2_BITMASK       (0x8U)
#define MSCR_MII_SPEED3_BITMASK       (0x10U)
#define MSCR_MII_SPEED4_BITMASK       (0x20U)
#define MSCR_MII_SPEED5_BITMASK       (0x40U)
#define MSCR_DIS_PREAMBLE_BITMASK     (0x80U)
#define MSCR_MII_SPEED_GRPMASK        (0x7EU)
#define MSCR_MII_SPEED_GRPPOS         (0x1U)

/*** MIBC - MIB Control Register.; 0x00001064 ***/
#define MIBC                          (*((volatile uint32 *)(&__IPSBAR[0x00001064UL])))
#define MIBC_MIB_IDLE_BITMASK         (0x40000000U)
#define MIBC_MIB_DISABLE_BITMASK      (0x80000000U)

/*** FEC_RCR - Receive Control Register.; 0x00001084 ***/
#define FEC_RCR                       (*((volatile uint32 *)(&__IPSBAR[0x00001084UL])))
#define FEC_RCR_LOOP_BITMASK          (0x1U)
#define FEC_RCR_DRT_BITMASK           (0x2U)
#define FEC_RCR_MII_MODE_BITMASK      (0x4U)
#define FEC_RCR_PROM_BITMASK          (0x8U)
#define FEC_RCR_BC_REJ_BITMASK        (0x10U)
#define FEC_RCR_FCE_BITMASK           (0x20U)
#define FEC_RCR_MAX_FL0_BITMASK       (0x10000U)
#define FEC_RCR_MAX_FL1_BITMASK       (0x20000U)
#define FEC_RCR_MAX_FL2_BITMASK       (0x40000U)
#define FEC_RCR_MAX_FL3_BITMASK       (0x80000U)
#define FEC_RCR_MAX_FL4_BITMASK       (0x100000U)
#define FEC_RCR_MAX_FL5_BITMASK       (0x200000U)
#define FEC_RCR_MAX_FL6_BITMASK       (0x400000U)
#define FEC_RCR_MAX_FL7_BITMASK       (0x800000U)
#define FEC_RCR_MAX_FL8_BITMASK       (0x1000000U)
#define FEC_RCR_MAX_FL9_BITMASK       (0x2000000U)
#define FEC_RCR_MAX_FL10_BITMASK      (0x4000000U)
#define FEC_RCR_MAX_FL_GRPMASK        (0x7FF0000U)
#define FEC_RCR_MAX_FL_GRPPOS         (0x10U)

/*** TCR - Transmit Control Register .; 0x000010C4 ***/
#define TCR                           (*((volatile uint32 *)(&__IPSBAR[0x000010C4UL])))
#define TCR_GTS_BITMASK               (0x1U)
#define TCR_HBC_BITMASK               (0x2U)
#define TCR_FDEN_BITMASK              (0x4U)
#define TCR_TFC_PAUSE_BITMASK         (0x8U)
#define TCR_RFC_PAUSE_BITMASK         (0x10U)

/*** PALR - Physical Address Low Register.; 0x000010E4 ***/
#define PALR                          (*((volatile uint32 *)(&__IPSBAR[0x000010E4UL])))
#define PALR_PADDR10_BITMASK          (0x1U)
#define PALR_PADDR11_BITMASK          (0x2U)
#define PALR_PADDR12_BITMASK          (0x4U)
#define PALR_PADDR13_BITMASK          (0x8U)
#define PALR_PADDR14_BITMASK          (0x10U)
#define PALR_PADDR15_BITMASK          (0x20U)
#define PALR_PADDR16_BITMASK          (0x40U)
#define PALR_PADDR17_BITMASK          (0x80U)
#define PALR_PADDR18_BITMASK          (0x100U)
#define PALR_PADDR19_BITMASK          (0x200U)
#define PALR_PADDR110_BITMASK         (0x400U)
#define PALR_PADDR111_BITMASK         (0x800U)
#define PALR_PADDR112_BITMASK         (0x1000U)
#define PALR_PADDR113_BITMASK         (0x2000U)
#define PALR_PADDR114_BITMASK         (0x4000U)
#define PALR_PADDR115_BITMASK         (0x8000U)
#define PALR_PADDR116_BITMASK         (0x10000U)
#define PALR_PADDR117_BITMASK         (0x20000U)
#define PALR_PADDR118_BITMASK         (0x40000U)
#define PALR_PADDR119_BITMASK         (0x80000U)
#define PALR_PADDR120_BITMASK         (0x100000U)
#define PALR_PADDR121_BITMASK         (0x200000U)
#define PALR_PADDR122_BITMASK         (0x400000U)
#define PALR_PADDR123_BITMASK         (0x800000U)
#define PALR_PADDR124_BITMASK         (0x1000000U)
#define PALR_PADDR125_BITMASK         (0x2000000U)
#define PALR_PADDR126_BITMASK         (0x4000000U)
#define PALR_PADDR127_BITMASK         (0x8000000U)
#define PALR_PADDR128_BITMASK         (0x10000000U)
#define PALR_PADDR129_BITMASK         (0x20000000U)
#define PALR_PADDR130_BITMASK         (0x40000000U)
#define PALR_PADDR131_BITMASK         (0x80000000U)
#define PALR_PADDR1_GRPMASK           (0xFFFFFFFFU)
#define PALR_PADDR1_GRPPOS            (0U)

/*** PAUR - Physical Address High Register.; 0x000010E8 ***/
#define PAUR                          (*((volatile uint32 *)(&__IPSBAR[0x000010E8UL])))
#define PAUR_TYPE0_BITMASK            (0x1U)
#define PAUR_TYPE1_BITMASK            (0x2U)
#define PAUR_TYPE2_BITMASK            (0x4U)
#define PAUR_TYPE3_BITMASK            (0x8U)
#define PAUR_TYPE4_BITMASK            (0x10U)
#define PAUR_TYPE5_BITMASK            (0x20U)
#define PAUR_TYPE6_BITMASK            (0x40U)
#define PAUR_TYPE7_BITMASK            (0x80U)
#define PAUR_TYPE8_BITMASK            (0x100U)
#define PAUR_TYPE9_BITMASK            (0x200U)
#define PAUR_TYPE10_BITMASK           (0x400U)
#define PAUR_TYPE11_BITMASK           (0x800U)
#define PAUR_TYPE12_BITMASK           (0x1000U)
#define PAUR_TYPE13_BITMASK           (0x2000U)
#define PAUR_TYPE14_BITMASK           (0x4000U)
#define PAUR_TYPE15_BITMASK           (0x8000U)
#define PAUR_PADDR20_BITMASK          (0x10000U)
#define PAUR_PADDR21_BITMASK          (0x20000U)
#define PAUR_PADDR22_BITMASK          (0x40000U)
#define PAUR_PADDR23_BITMASK          (0x80000U)
#define PAUR_PADDR24_BITMASK          (0x100000U)
#define PAUR_PADDR25_BITMASK          (0x200000U)
#define PAUR_PADDR26_BITMASK          (0x400000U)
#define PAUR_PADDR27_BITMASK          (0x800000U)
#define PAUR_PADDR28_BITMASK          (0x1000000U)
#define PAUR_PADDR29_BITMASK          (0x2000000U)
#define PAUR_PADDR210_BITMASK         (0x4000000U)
#define PAUR_PADDR211_BITMASK         (0x8000000U)
#define PAUR_PADDR212_BITMASK         (0x10000000U)
#define PAUR_PADDR213_BITMASK         (0x20000000U)
#define PAUR_PADDR214_BITMASK         (0x40000000U)
#define PAUR_PADDR215_BITMASK         (0x80000000U)
#define PAUR_TYPE_GRPMASK             (0xFFFFU)
#define PAUR_TYPE_GRPPOS              (0U)
#define PAUR_PADDR2_GRPMASK           (0xFFFF0000U)
#define PAUR_PADDR2_GRPPOS            (0x10U)

/*** OPD - Opcode/Pause Duration Register.; 0x000010EC ***/
#define OPD                           (*((volatile uint32 *)(&__IPSBAR[0x000010ECUL])))
#define OPD_PAUSE_DUR0_BITMASK        (0x1U)
#define OPD_PAUSE_DUR1_BITMASK        (0x2U)
#define OPD_PAUSE_DUR2_BITMASK        (0x4U)
#define OPD_PAUSE_DUR3_BITMASK        (0x8U)
#define OPD_PAUSE_DUR4_BITMASK        (0x10U)
#define OPD_PAUSE_DUR5_BITMASK        (0x20U)
#define OPD_PAUSE_DUR6_BITMASK        (0x40U)
#define OPD_PAUSE_DUR7_BITMASK        (0x80U)
#define OPD_PAUSE_DUR8_BITMASK        (0x100U)
#define OPD_PAUSE_DUR9_BITMASK        (0x200U)
#define OPD_PAUSE_DUR10_BITMASK       (0x400U)
#define OPD_PAUSE_DUR11_BITMASK       (0x800U)
#define OPD_PAUSE_DUR12_BITMASK       (0x1000U)
#define OPD_PAUSE_DUR13_BITMASK       (0x2000U)
#define OPD_PAUSE_DUR14_BITMASK       (0x4000U)
#define OPD_PAUSE_DUR15_BITMASK       (0x8000U)
#define OPD_OPCODE0_BITMASK           (0x10000U)
#define OPD_OPCODE1_BITMASK           (0x20000U)
#define OPD_OPCODE2_BITMASK           (0x40000U)
#define OPD_OPCODE3_BITMASK           (0x80000U)
#define OPD_OPCODE4_BITMASK           (0x100000U)
#define OPD_OPCODE5_BITMASK           (0x200000U)
#define OPD_OPCODE6_BITMASK           (0x400000U)
#define OPD_OPCODE7_BITMASK           (0x800000U)
#define OPD_OPCODE8_BITMASK           (0x1000000U)
#define OPD_OPCODE9_BITMASK           (0x2000000U)
#define OPD_OPCODE10_BITMASK          (0x4000000U)
#define OPD_OPCODE11_BITMASK          (0x8000000U)
#define OPD_OPCODE12_BITMASK          (0x10000000U)
#define OPD_OPCODE13_BITMASK          (0x20000000U)
#define OPD_OPCODE14_BITMASK          (0x40000000U)
#define OPD_OPCODE15_BITMASK          (0x80000000U)
#define OPD_PAUSE_DUR_GRPMASK         (0xFFFFU)
#define OPD_PAUSE_DUR_GRPPOS          (0U)
#define OPD_OPCODE_GRPMASK            (0xFFFF0000U)
#define OPD_OPCODE_GRPPOS             (0x10U)

/*** IAUR - Descriptor Individual Upper Address Register.; 0x00001118 ***/
#define IAUR                          (*((volatile uint32 *)(&__IPSBAR[0x00001118UL])))
#define IAUR_IADDR10_BITMASK          (0x1U)
#define IAUR_IADDR11_BITMASK          (0x2U)
#define IAUR_IADDR12_BITMASK          (0x4U)
#define IAUR_IADDR13_BITMASK          (0x8U)
#define IAUR_IADDR14_BITMASK          (0x10U)
#define IAUR_IADDR15_BITMASK          (0x20U)
#define IAUR_IADDR16_BITMASK          (0x40U)
#define IAUR_IADDR17_BITMASK          (0x80U)
#define IAUR_IADDR18_BITMASK          (0x100U)
#define IAUR_IADDR19_BITMASK          (0x200U)
#define IAUR_IADDR110_BITMASK         (0x400U)
#define IAUR_IADDR111_BITMASK         (0x800U)
#define IAUR_IADDR112_BITMASK         (0x1000U)
#define IAUR_IADDR113_BITMASK         (0x2000U)
#define IAUR_IADDR114_BITMASK         (0x4000U)
#define IAUR_IADDR115_BITMASK         (0x8000U)
#define IAUR_IADDR116_BITMASK         (0x10000U)
#define IAUR_IADDR117_BITMASK         (0x20000U)
#define IAUR_IADDR118_BITMASK         (0x40000U)
#define IAUR_IADDR119_BITMASK         (0x80000U)
#define IAUR_IADDR120_BITMASK         (0x100000U)
#define IAUR_IADDR121_BITMASK         (0x200000U)
#define IAUR_IADDR122_BITMASK         (0x400000U)
#define IAUR_IADDR123_BITMASK         (0x800000U)
#define IAUR_IADDR124_BITMASK         (0x1000000U)
#define IAUR_IADDR125_BITMASK         (0x2000000U)
#define IAUR_IADDR126_BITMASK         (0x4000000U)
#define IAUR_IADDR127_BITMASK         (0x8000000U)
#define IAUR_IADDR128_BITMASK         (0x10000000U)
#define IAUR_IADDR129_BITMASK         (0x20000000U)
#define IAUR_IADDR130_BITMASK         (0x40000000U)
#define IAUR_IADDR131_BITMASK         (0x80000000U)
#define IAUR_IADDR1_GRPMASK           (0xFFFFFFFFU)
#define IAUR_IADDR1_GRPPOS            (0U)

/*** IALR - Descriptor Individual Lower Address Register.; 0x0000111C ***/
#define IALR                          (*((volatile uint32 *)(&__IPSBAR[0x0000111CUL])))
#define IALR_IADDR20_BITMASK          (0x1U)
#define IALR_IADDR21_BITMASK          (0x2U)
#define IALR_IADDR22_BITMASK          (0x4U)
#define IALR_IADDR23_BITMASK          (0x8U)
#define IALR_IADDR24_BITMASK          (0x10U)
#define IALR_IADDR25_BITMASK          (0x20U)
#define IALR_IADDR26_BITMASK          (0x40U)
#define IALR_IADDR27_BITMASK          (0x80U)
#define IALR_IADDR28_BITMASK          (0x100U)
#define IALR_IADDR29_BITMASK          (0x200U)
#define IALR_IADDR210_BITMASK         (0x400U)
#define IALR_IADDR211_BITMASK         (0x800U)
#define IALR_IADDR212_BITMASK         (0x1000U)
#define IALR_IADDR213_BITMASK         (0x2000U)
#define IALR_IADDR214_BITMASK         (0x4000U)
#define IALR_IADDR215_BITMASK         (0x8000U)
#define IALR_IADDR216_BITMASK         (0x10000U)
#define IALR_IADDR217_BITMASK         (0x20000U)
#define IALR_IADDR218_BITMASK         (0x40000U)
#define IALR_IADDR219_BITMASK         (0x80000U)
#define IALR_IADDR220_BITMASK         (0x100000U)
#define IALR_IADDR221_BITMASK         (0x200000U)
#define IALR_IADDR222_BITMASK         (0x400000U)
#define IALR_IADDR223_BITMASK         (0x800000U)
#define IALR_IADDR224_BITMASK         (0x1000000U)
#define IALR_IADDR225_BITMASK         (0x2000000U)
#define IALR_IADDR226_BITMASK         (0x4000000U)
#define IALR_IADDR227_BITMASK         (0x8000000U)
#define IALR_IADDR228_BITMASK         (0x10000000U)
#define IALR_IADDR229_BITMASK         (0x20000000U)
#define IALR_IADDR230_BITMASK         (0x40000000U)
#define IALR_IADDR231_BITMASK         (0x80000000U)
#define IALR_IADDR2_GRPMASK           (0xFFFFFFFFU)
#define IALR_IADDR2_GRPPOS            (0U)

/*** GAUR - Descriptor Group Upper Address Register.; 0x00001120 ***/
#define GAUR                          (*((volatile uint32 *)(&__IPSBAR[0x00001120UL])))
#define GAUR_GADDR10_BITMASK          (0x1U)
#define GAUR_GADDR11_BITMASK          (0x2U)
#define GAUR_GADDR12_BITMASK          (0x4U)
#define GAUR_GADDR13_BITMASK          (0x8U)
#define GAUR_GADDR14_BITMASK          (0x10U)
#define GAUR_GADDR15_BITMASK          (0x20U)
#define GAUR_GADDR16_BITMASK          (0x40U)
#define GAUR_GADDR17_BITMASK          (0x80U)
#define GAUR_GADDR18_BITMASK          (0x100U)
#define GAUR_GADDR19_BITMASK          (0x200U)
#define GAUR_GADDR110_BITMASK         (0x400U)
#define GAUR_GADDR111_BITMASK         (0x800U)
#define GAUR_GADDR112_BITMASK         (0x1000U)
#define GAUR_GADDR113_BITMASK         (0x2000U)
#define GAUR_GADDR114_BITMASK         (0x4000U)
#define GAUR_GADDR115_BITMASK         (0x8000U)
#define GAUR_GADDR116_BITMASK         (0x10000U)
#define GAUR_GADDR117_BITMASK         (0x20000U)
#define GAUR_GADDR118_BITMASK         (0x40000U)
#define GAUR_GADDR119_BITMASK         (0x80000U)
#define GAUR_GADDR120_BITMASK         (0x100000U)
#define GAUR_GADDR121_BITMASK         (0x200000U)
#define GAUR_GADDR122_BITMASK         (0x400000U)
#define GAUR_GADDR123_BITMASK         (0x800000U)
#define GAUR_GADDR124_BITMASK         (0x1000000U)
#define GAUR_GADDR125_BITMASK         (0x2000000U)
#define GAUR_GADDR126_BITMASK         (0x4000000U)
#define GAUR_GADDR127_BITMASK         (0x8000000U)
#define GAUR_GADDR128_BITMASK         (0x10000000U)
#define GAUR_GADDR129_BITMASK         (0x20000000U)
#define GAUR_GADDR130_BITMASK         (0x40000000U)
#define GAUR_GADDR131_BITMASK         (0x80000000U)
#define GAUR_GADDR1_GRPMASK           (0xFFFFFFFFU)
#define GAUR_GADDR1_GRPPOS            (0U)

/*** GALR - Descriptor Group Lower Address Register.; 0x00001124 ***/
#define GALR                          (*((volatile uint32 *)(&__IPSBAR[0x00001124UL])))
#define GALR_GADDR20_BITMASK          (0x1U)
#define GALR_GADDR21_BITMASK          (0x2U)
#define GALR_GADDR22_BITMASK          (0x4U)
#define GALR_GADDR23_BITMASK          (0x8U)
#define GALR_GADDR24_BITMASK          (0x10U)
#define GALR_GADDR25_BITMASK          (0x20U)
#define GALR_GADDR26_BITMASK          (0x40U)
#define GALR_GADDR27_BITMASK          (0x80U)
#define GALR_GADDR28_BITMASK          (0x100U)
#define GALR_GADDR29_BITMASK          (0x200U)
#define GALR_GADDR210_BITMASK         (0x400U)
#define GALR_GADDR211_BITMASK         (0x800U)
#define GALR_GADDR212_BITMASK         (0x1000U)
#define GALR_GADDR213_BITMASK         (0x2000U)
#define GALR_GADDR214_BITMASK         (0x4000U)
#define GALR_GADDR215_BITMASK         (0x8000U)
#define GALR_GADDR216_BITMASK         (0x10000U)
#define GALR_GADDR217_BITMASK         (0x20000U)
#define GALR_GADDR218_BITMASK         (0x40000U)
#define GALR_GADDR219_BITMASK         (0x80000U)
#define GALR_GADDR220_BITMASK         (0x100000U)
#define GALR_GADDR221_BITMASK         (0x200000U)
#define GALR_GADDR222_BITMASK         (0x400000U)
#define GALR_GADDR223_BITMASK         (0x800000U)
#define GALR_GADDR224_BITMASK         (0x1000000U)
#define GALR_GADDR225_BITMASK         (0x2000000U)
#define GALR_GADDR226_BITMASK         (0x4000000U)
#define GALR_GADDR227_BITMASK         (0x8000000U)
#define GALR_GADDR228_BITMASK         (0x10000000U)
#define GALR_GADDR229_BITMASK         (0x20000000U)
#define GALR_GADDR230_BITMASK         (0x40000000U)
#define GALR_GADDR231_BITMASK         (0x80000000U)
#define GALR_GADDR2_GRPMASK           (0xFFFFFFFFU)
#define GALR_GADDR2_GRPPOS            (0U)

/*** TFWR - FIFO Transmit FIFO Watermark Register.; 0x00001144 ***/
#define TFWR                          (*((volatile uint32 *)(&__IPSBAR[0x00001144UL])))
#define TFWR_X_WMRK0_BITMASK          (0x1U)
#define TFWR_X_WMRK1_BITMASK          (0x2U)
#define TFWR_X_WMRK_GRPMASK           (0x3U)
#define TFWR_X_WMRK_GRPPOS            (0U)

/*** FRBR - FIFO Receive Bound Register.; 0x0000114C ***/
#define FRBR                          (*((volatile uint32 *)(&__IPSBAR[0x0000114CUL])))
#define FRBR_R_BOUND0_BITMASK         (0x4U)
#define FRBR_R_BOUND1_BITMASK         (0x8U)
#define FRBR_R_BOUND2_BITMASK         (0x10U)
#define FRBR_R_BOUND3_BITMASK         (0x20U)
#define FRBR_R_BOUND4_BITMASK         (0x40U)
#define FRBR_R_BOUND5_BITMASK         (0x80U)
#define FRBR_R_BOUND6_BITMASK         (0x100U)
#define FRBR_R_BOUND7_BITMASK         (0x200U)
#define FRBR_R_BOUND_GRPMASK          (0x3FCU)
#define FRBR_R_BOUND_GRPPOS           (0x2U)

/*** FRSR - FIFO Receive Start Register.; 0x00001150 ***/
#define FRSR                          (*((volatile uint32 *)(&__IPSBAR[0x00001150UL])))
#define FRSR_R_FSTART0_BITMASK        (0x4U)
#define FRSR_R_FSTART1_BITMASK        (0x8U)
#define FRSR_R_FSTART2_BITMASK        (0x10U)
#define FRSR_R_FSTART3_BITMASK        (0x20U)
#define FRSR_R_FSTART4_BITMASK        (0x40U)
#define FRSR_R_FSTART5_BITMASK        (0x80U)
#define FRSR_R_FSTART6_BITMASK        (0x100U)
#define FRSR_R_FSTART7_BITMASK        (0x200U)
#define FRSR_R_FSTART_GRPMASK         (0x3FCU)
#define FRSR_R_FSTART_GRPPOS          (0x2U)

/*** ERDSR - Receive Descriptor Ring Start Register.; 0x00001180 ***/
#define ERDSR                         (*((volatile uint32 *)(&__IPSBAR[0x00001180UL])))
#define ERDSR_R_DES_START0_BITMASK    (0x4U)
#define ERDSR_R_DES_START1_BITMASK    (0x8U)
#define ERDSR_R_DES_START2_BITMASK    (0x10U)
#define ERDSR_R_DES_START3_BITMASK    (0x20U)
#define ERDSR_R_DES_START4_BITMASK    (0x40U)
#define ERDSR_R_DES_START5_BITMASK    (0x80U)
#define ERDSR_R_DES_START6_BITMASK    (0x100U)
#define ERDSR_R_DES_START7_BITMASK    (0x200U)
#define ERDSR_R_DES_START8_BITMASK    (0x400U)
#define ERDSR_R_DES_START9_BITMASK    (0x800U)
#define ERDSR_R_DES_START10_BITMASK   (0x1000U)
#define ERDSR_R_DES_START11_BITMASK   (0x2000U)
#define ERDSR_R_DES_START12_BITMASK   (0x4000U)
#define ERDSR_R_DES_START13_BITMASK   (0x8000U)
#define ERDSR_R_DES_START14_BITMASK   (0x10000U)
#define ERDSR_R_DES_START15_BITMASK   (0x20000U)
#define ERDSR_R_DES_START16_BITMASK   (0x40000U)
#define ERDSR_R_DES_START17_BITMASK   (0x80000U)
#define ERDSR_R_DES_START18_BITMASK   (0x100000U)
#define ERDSR_R_DES_START19_BITMASK   (0x200000U)
#define ERDSR_R_DES_START20_BITMASK   (0x400000U)
#define ERDSR_R_DES_START21_BITMASK   (0x800000U)
#define ERDSR_R_DES_START22_BITMASK   (0x1000000U)
#define ERDSR_R_DES_START23_BITMASK   (0x2000000U)
#define ERDSR_R_DES_START24_BITMASK   (0x4000000U)
#define ERDSR_R_DES_START25_BITMASK   (0x8000000U)
#define ERDSR_R_DES_START26_BITMASK   (0x10000000U)
#define ERDSR_R_DES_START27_BITMASK   (0x20000000U)
#define ERDSR_R_DES_START28_BITMASK   (0x40000000U)
#define ERDSR_R_DES_START29_BITMASK   (0x80000000U)
#define ERDSR_R_DES_START_GRPMASK     (0xFFFFFFFCU)
#define ERDSR_R_DES_START_GRPPOS      (0x2U)

/*** ETSDR - Transmit Buffer Descriptor Ring Start Register.; 0x00001184 ***/
#define ETSDR                         (*((volatile uint32 *)(&__IPSBAR[0x00001184UL])))
#define ETSDR_X_DES_START0_BITMASK    (0x4U)
#define ETSDR_X_DES_START1_BITMASK    (0x8U)
#define ETSDR_X_DES_START2_BITMASK    (0x10U)
#define ETSDR_X_DES_START3_BITMASK    (0x20U)
#define ETSDR_X_DES_START4_BITMASK    (0x40U)
#define ETSDR_X_DES_START5_BITMASK    (0x80U)
#define ETSDR_X_DES_START6_BITMASK    (0x100U)
#define ETSDR_X_DES_START7_BITMASK    (0x200U)
#define ETSDR_X_DES_START8_BITMASK    (0x400U)
#define ETSDR_X_DES_START9_BITMASK    (0x800U)
#define ETSDR_X_DES_START10_BITMASK   (0x1000U)
#define ETSDR_X_DES_START11_BITMASK   (0x2000U)
#define ETSDR_X_DES_START12_BITMASK   (0x4000U)
#define ETSDR_X_DES_START13_BITMASK   (0x8000U)
#define ETSDR_X_DES_START14_BITMASK   (0x10000U)
#define ETSDR_X_DES_START15_BITMASK   (0x20000U)
#define ETSDR_X_DES_START16_BITMASK   (0x40000U)
#define ETSDR_X_DES_START17_BITMASK   (0x80000U)
#define ETSDR_X_DES_START18_BITMASK   (0x100000U)
#define ETSDR_X_DES_START19_BITMASK   (0x200000U)
#define ETSDR_X_DES_START20_BITMASK   (0x400000U)
#define ETSDR_X_DES_START21_BITMASK   (0x800000U)
#define ETSDR_X_DES_START22_BITMASK   (0x1000000U)
#define ETSDR_X_DES_START23_BITMASK   (0x2000000U)
#define ETSDR_X_DES_START24_BITMASK   (0x4000000U)
#define ETSDR_X_DES_START25_BITMASK   (0x8000000U)
#define ETSDR_X_DES_START26_BITMASK   (0x10000000U)
#define ETSDR_X_DES_START27_BITMASK   (0x20000000U)
#define ETSDR_X_DES_START28_BITMASK   (0x40000000U)
#define ETSDR_X_DES_START29_BITMASK   (0x80000000U)
#define ETSDR_X_DES_START_GRPMASK     (0xFFFFFFFCU)
#define ETSDR_X_DES_START_GRPPOS      (0x2U)

/*** EMRBR - Receive Buffer Size Register.; 0x00001188 ***/
#define EMRBR                         (*((volatile uint32 *)(&__IPSBAR[0x00001188UL])))
#define EMRBR_R_BUF_SIZE0_BITMASK     (0x10U)
#define EMRBR_R_BUF_SIZE1_BITMASK     (0x20U)
#define EMRBR_R_BUF_SIZE2_BITMASK     (0x40U)
#define EMRBR_R_BUF_SIZE3_BITMASK     (0x80U)
#define EMRBR_R_BUF_SIZE4_BITMASK     (0x100U)
#define EMRBR_R_BUF_SIZE5_BITMASK     (0x200U)
#define EMRBR_R_BUF_SIZE6_BITMASK     (0x400U)
#define EMRBR_R_BUF_SIZE_GRPMASK      (0x7F0U)
#define EMRBR_R_BUF_SIZE_GRPPOS       (0x4U)

/*** RMON_T_DROP - Count of frames not counted correctly.; 0x00001200 ***/
#define RMON_T_DROP                   (*((volatile uint32 *)(&__IPSBAR[0x00001200UL])))
#define RMON_T_DROP_Value0_BITMASK    (0x1U)
#define RMON_T_DROP_Value1_BITMASK    (0x2U)
#define RMON_T_DROP_Value2_BITMASK    (0x4U)
#define RMON_T_DROP_Value3_BITMASK    (0x8U)
#define RMON_T_DROP_Value4_BITMASK    (0x10U)
#define RMON_T_DROP_Value5_BITMASK    (0x20U)
#define RMON_T_DROP_Value6_BITMASK    (0x40U)
#define RMON_T_DROP_Value7_BITMASK    (0x80U)
#define RMON_T_DROP_Value8_BITMASK    (0x100U)
#define RMON_T_DROP_Value9_BITMASK    (0x200U)
#define RMON_T_DROP_Value10_BITMASK   (0x400U)
#define RMON_T_DROP_Value11_BITMASK   (0x800U)
#define RMON_T_DROP_Value12_BITMASK   (0x1000U)
#define RMON_T_DROP_Value13_BITMASK   (0x2000U)
#define RMON_T_DROP_Value14_BITMASK   (0x4000U)
#define RMON_T_DROP_Value15_BITMASK   (0x8000U)
#define RMON_T_DROP_Value16_BITMASK   (0x10000U)
#define RMON_T_DROP_Value17_BITMASK   (0x20000U)
#define RMON_T_DROP_Value18_BITMASK   (0x40000U)
#define RMON_T_DROP_Value19_BITMASK   (0x80000U)
#define RMON_T_DROP_Value20_BITMASK   (0x100000U)
#define RMON_T_DROP_Value21_BITMASK   (0x200000U)
#define RMON_T_DROP_Value22_BITMASK   (0x400000U)
#define RMON_T_DROP_Value23_BITMASK   (0x800000U)
#define RMON_T_DROP_Value24_BITMASK   (0x1000000U)
#define RMON_T_DROP_Value25_BITMASK   (0x2000000U)
#define RMON_T_DROP_Value26_BITMASK   (0x4000000U)
#define RMON_T_DROP_Value27_BITMASK   (0x8000000U)
#define RMON_T_DROP_Value28_BITMASK   (0x10000000U)
#define RMON_T_DROP_Value29_BITMASK   (0x20000000U)
#define RMON_T_DROP_Value30_BITMASK   (0x40000000U)
#define RMON_T_DROP_Value31_BITMASK   (0x80000000U)
#define RMON_T_DROP_Value_GRPMASK     (0xFFFFFFFFU)
#define RMON_T_DROP_Value_GRPPOS      (0U)

/*** RMON_T_PACKETS - RMON Tx packet count.; 0x00001204 ***/
#define RMON_T_PACKETS                (*((volatile uint32 *)(&__IPSBAR[0x00001204UL])))
#define RMON_T_PACKETS_Value0_BITMASK (0x1U)
#define RMON_T_PACKETS_Value1_BITMASK (0x2U)
#define RMON_T_PACKETS_Value2_BITMASK (0x4U)
#define RMON_T_PACKETS_Value3_BITMASK (0x8U)
#define RMON_T_PACKETS_Value4_BITMASK (0x10U)
#define RMON_T_PACKETS_Value5_BITMASK (0x20U)
#define RMON_T_PACKETS_Value6_BITMASK (0x40U)
#define RMON_T_PACKETS_Value7_BITMASK (0x80U)
#define RMON_T_PACKETS_Value8_BITMASK (0x100U)
#define RMON_T_PACKETS_Value9_BITMASK (0x200U)
#define RMON_T_PACKETS_Value10_BITMASK (0x400U)
#define RMON_T_PACKETS_Value11_BITMASK (0x800U)
#define RMON_T_PACKETS_Value12_BITMASK (0x1000U)
#define RMON_T_PACKETS_Value13_BITMASK (0x2000U)
#define RMON_T_PACKETS_Value14_BITMASK (0x4000U)
#define RMON_T_PACKETS_Value15_BITMASK (0x8000U)
#define RMON_T_PACKETS_Value16_BITMASK (0x10000U)
#define RMON_T_PACKETS_Value17_BITMASK (0x20000U)
#define RMON_T_PACKETS_Value18_BITMASK (0x40000U)
#define RMON_T_PACKETS_Value19_BITMASK (0x80000U)
#define RMON_T_PACKETS_Value20_BITMASK (0x100000U)
#define RMON_T_PACKETS_Value21_BITMASK (0x200000U)
#define RMON_T_PACKETS_Value22_BITMASK (0x400000U)
#define RMON_T_PACKETS_Value23_BITMASK (0x800000U)
#define RMON_T_PACKETS_Value24_BITMASK (0x1000000U)
#define RMON_T_PACKETS_Value25_BITMASK (0x2000000U)
#define RMON_T_PACKETS_Value26_BITMASK (0x4000000U)
#define RMON_T_PACKETS_Value27_BITMASK (0x8000000U)
#define RMON_T_PACKETS_Value28_BITMASK (0x10000000U)
#define RMON_T_PACKETS_Value29_BITMASK (0x20000000U)
#define RMON_T_PACKETS_Value30_BITMASK (0x40000000U)
#define RMON_T_PACKETS_Value31_BITMASK (0x80000000U)
#define RMON_T_PACKETS_Value_GRPMASK  (0xFFFFFFFFU)
#define RMON_T_PACKETS_Value_GRPPOS   (0U)

/*** RMON_T_BC_PKT - RMON Tx Broadcast Packets.; 0x00001208 ***/
#define RMON_T_BC_PKT                 (*((volatile uint32 *)(&__IPSBAR[0x00001208UL])))
#define RMON_T_BC_PKT_Value0_BITMASK  (0x1U)
#define RMON_T_BC_PKT_Value1_BITMASK  (0x2U)
#define RMON_T_BC_PKT_Value2_BITMASK  (0x4U)
#define RMON_T_BC_PKT_Value3_BITMASK  (0x8U)
#define RMON_T_BC_PKT_Value4_BITMASK  (0x10U)
#define RMON_T_BC_PKT_Value5_BITMASK  (0x20U)
#define RMON_T_BC_PKT_Value6_BITMASK  (0x40U)
#define RMON_T_BC_PKT_Value7_BITMASK  (0x80U)
#define RMON_T_BC_PKT_Value8_BITMASK  (0x100U)
#define RMON_T_BC_PKT_Value9_BITMASK  (0x200U)
#define RMON_T_BC_PKT_Value10_BITMASK (0x400U)
#define RMON_T_BC_PKT_Value11_BITMASK (0x800U)
#define RMON_T_BC_PKT_Value12_BITMASK (0x1000U)
#define RMON_T_BC_PKT_Value13_BITMASK (0x2000U)
#define RMON_T_BC_PKT_Value14_BITMASK (0x4000U)
#define RMON_T_BC_PKT_Value15_BITMASK (0x8000U)
#define RMON_T_BC_PKT_Value16_BITMASK (0x10000U)
#define RMON_T_BC_PKT_Value17_BITMASK (0x20000U)
#define RMON_T_BC_PKT_Value18_BITMASK (0x40000U)
#define RMON_T_BC_PKT_Value19_BITMASK (0x80000U)
#define RMON_T_BC_PKT_Value20_BITMASK (0x100000U)
#define RMON_T_BC_PKT_Value21_BITMASK (0x200000U)
#define RMON_T_BC_PKT_Value22_BITMASK (0x400000U)
#define RMON_T_BC_PKT_Value23_BITMASK (0x800000U)
#define RMON_T_BC_PKT_Value24_BITMASK (0x1000000U)
#define RMON_T_BC_PKT_Value25_BITMASK (0x2000000U)
#define RMON_T_BC_PKT_Value26_BITMASK (0x4000000U)
#define RMON_T_BC_PKT_Value27_BITMASK (0x8000000U)
#define RMON_T_BC_PKT_Value28_BITMASK (0x10000000U)
#define RMON_T_BC_PKT_Value29_BITMASK (0x20000000U)
#define RMON_T_BC_PKT_Value30_BITMASK (0x40000000U)
#define RMON_T_BC_PKT_Value31_BITMASK (0x80000000U)
#define RMON_T_BC_PKT_Value_GRPMASK   (0xFFFFFFFFU)
#define RMON_T_BC_PKT_Value_GRPPOS    (0U)

/*** RMON_T_MC_PKT - RMON Tx Multicast Packets.; 0x0000120C ***/
#define RMON_T_MC_PKT                 (*((volatile uint32 *)(&__IPSBAR[0x0000120CUL])))
#define RMON_T_MC_PKT_Value0_BITMASK  (0x1U)
#define RMON_T_MC_PKT_Value1_BITMASK  (0x2U)
#define RMON_T_MC_PKT_Value2_BITMASK  (0x4U)
#define RMON_T_MC_PKT_Value3_BITMASK  (0x8U)
#define RMON_T_MC_PKT_Value4_BITMASK  (0x10U)
#define RMON_T_MC_PKT_Value5_BITMASK  (0x20U)
#define RMON_T_MC_PKT_Value6_BITMASK  (0x40U)
#define RMON_T_MC_PKT_Value7_BITMASK  (0x80U)
#define RMON_T_MC_PKT_Value8_BITMASK  (0x100U)
#define RMON_T_MC_PKT_Value9_BITMASK  (0x200U)
#define RMON_T_MC_PKT_Value10_BITMASK (0x400U)
#define RMON_T_MC_PKT_Value11_BITMASK (0x800U)
#define RMON_T_MC_PKT_Value12_BITMASK (0x1000U)
#define RMON_T_MC_PKT_Value13_BITMASK (0x2000U)
#define RMON_T_MC_PKT_Value14_BITMASK (0x4000U)
#define RMON_T_MC_PKT_Value15_BITMASK (0x8000U)
#define RMON_T_MC_PKT_Value16_BITMASK (0x10000U)
#define RMON_T_MC_PKT_Value17_BITMASK (0x20000U)
#define RMON_T_MC_PKT_Value18_BITMASK (0x40000U)
#define RMON_T_MC_PKT_Value19_BITMASK (0x80000U)
#define RMON_T_MC_PKT_Value20_BITMASK (0x100000U)
#define RMON_T_MC_PKT_Value21_BITMASK (0x200000U)
#define RMON_T_MC_PKT_Value22_BITMASK (0x400000U)
#define RMON_T_MC_PKT_Value23_BITMASK (0x800000U)
#define RMON_T_MC_PKT_Value24_BITMASK (0x1000000U)
#define RMON_T_MC_PKT_Value25_BITMASK (0x2000000U)
#define RMON_T_MC_PKT_Value26_BITMASK (0x4000000U)
#define RMON_T_MC_PKT_Value27_BITMASK (0x8000000U)
#define RMON_T_MC_PKT_Value28_BITMASK (0x10000000U)
#define RMON_T_MC_PKT_Value29_BITMASK (0x20000000U)
#define RMON_T_MC_PKT_Value30_BITMASK (0x40000000U)
#define RMON_T_MC_PKT_Value31_BITMASK (0x80000000U)
#define RMON_T_MC_PKT_Value_GRPMASK   (0xFFFFFFFFU)
#define RMON_T_MC_PKT_Value_GRPPOS    (0U)

/*** RMON_T_CRC_ALIGN - RMON Tx Packets w CRC/Align error.; 0x00001210 ***/
#define RMON_T_CRC_ALIGN              (*((volatile uint32 *)(&__IPSBAR[0x00001210UL])))
#define RMON_T_CRC_ALIGN_Value0_BITMASK (0x1U)
#define RMON_T_CRC_ALIGN_Value1_BITMASK (0x2U)
#define RMON_T_CRC_ALIGN_Value2_BITMASK (0x4U)
#define RMON_T_CRC_ALIGN_Value3_BITMASK (0x8U)
#define RMON_T_CRC_ALIGN_Value4_BITMASK (0x10U)
#define RMON_T_CRC_ALIGN_Value5_BITMASK (0x20U)
#define RMON_T_CRC_ALIGN_Value6_BITMASK (0x40U)
#define RMON_T_CRC_ALIGN_Value7_BITMASK (0x80U)
#define RMON_T_CRC_ALIGN_Value8_BITMASK (0x100U)
#define RMON_T_CRC_ALIGN_Value9_BITMASK (0x200U)
#define RMON_T_CRC_ALIGN_Value10_BITMASK (0x400U)
#define RMON_T_CRC_ALIGN_Value11_BITMASK (0x800U)
#define RMON_T_CRC_ALIGN_Value12_BITMASK (0x1000U)
#define RMON_T_CRC_ALIGN_Value13_BITMASK (0x2000U)
#define RMON_T_CRC_ALIGN_Value14_BITMASK (0x4000U)
#define RMON_T_CRC_ALIGN_Value15_BITMASK (0x8000U)
#define RMON_T_CRC_ALIGN_Value16_BITMASK (0x10000U)
#define RMON_T_CRC_ALIGN_Value17_BITMASK (0x20000U)
#define RMON_T_CRC_ALIGN_Value18_BITMASK (0x40000U)
#define RMON_T_CRC_ALIGN_Value19_BITMASK (0x80000U)
#define RMON_T_CRC_ALIGN_Value20_BITMASK (0x100000U)
#define RMON_T_CRC_ALIGN_Value21_BITMASK (0x200000U)
#define RMON_T_CRC_ALIGN_Value22_BITMASK (0x400000U)
#define RMON_T_CRC_ALIGN_Value23_BITMASK (0x800000U)
#define RMON_T_CRC_ALIGN_Value24_BITMASK (0x1000000U)
#define RMON_T_CRC_ALIGN_Value25_BITMASK (0x2000000U)
#define RMON_T_CRC_ALIGN_Value26_BITMASK (0x4000000U)
#define RMON_T_CRC_ALIGN_Value27_BITMASK (0x8000000U)
#define RMON_T_CRC_ALIGN_Value28_BITMASK (0x10000000U)
#define RMON_T_CRC_ALIGN_Value29_BITMASK (0x20000000U)
#define RMON_T_CRC_ALIGN_Value30_BITMASK (0x40000000U)
#define RMON_T_CRC_ALIGN_Value31_BITMASK (0x80000000U)
#define RMON_T_CRC_ALIGN_Value_GRPMASK (0xFFFFFFFFU)
#define RMON_T_CRC_ALIGN_Value_GRPPOS (0U)

/*** RMON_T_UNDERSIZE - RMON Tx Packets < 64 bytes, good crc.; 0x00001214 ***/
#define RMON_T_UNDERSIZE              (*((volatile uint32 *)(&__IPSBAR[0x00001214UL])))
#define RMON_T_UNDERSIZE_Value0_BITMASK (0x1U)
#define RMON_T_UNDERSIZE_Value1_BITMASK (0x2U)
#define RMON_T_UNDERSIZE_Value2_BITMASK (0x4U)
#define RMON_T_UNDERSIZE_Value3_BITMASK (0x8U)
#define RMON_T_UNDERSIZE_Value4_BITMASK (0x10U)
#define RMON_T_UNDERSIZE_Value5_BITMASK (0x20U)
#define RMON_T_UNDERSIZE_Value6_BITMASK (0x40U)
#define RMON_T_UNDERSIZE_Value7_BITMASK (0x80U)
#define RMON_T_UNDERSIZE_Value8_BITMASK (0x100U)
#define RMON_T_UNDERSIZE_Value9_BITMASK (0x200U)
#define RMON_T_UNDERSIZE_Value10_BITMASK (0x400U)
#define RMON_T_UNDERSIZE_Value11_BITMASK (0x800U)
#define RMON_T_UNDERSIZE_Value12_BITMASK (0x1000U)
#define RMON_T_UNDERSIZE_Value13_BITMASK (0x2000U)
#define RMON_T_UNDERSIZE_Value14_BITMASK (0x4000U)
#define RMON_T_UNDERSIZE_Value15_BITMASK (0x8000U)
#define RMON_T_UNDERSIZE_Value16_BITMASK (0x10000U)
#define RMON_T_UNDERSIZE_Value17_BITMASK (0x20000U)
#define RMON_T_UNDERSIZE_Value18_BITMASK (0x40000U)
#define RMON_T_UNDERSIZE_Value19_BITMASK (0x80000U)
#define RMON_T_UNDERSIZE_Value20_BITMASK (0x100000U)
#define RMON_T_UNDERSIZE_Value21_BITMASK (0x200000U)
#define RMON_T_UNDERSIZE_Value22_BITMASK (0x400000U)
#define RMON_T_UNDERSIZE_Value23_BITMASK (0x800000U)
#define RMON_T_UNDERSIZE_Value24_BITMASK (0x1000000U)
#define RMON_T_UNDERSIZE_Value25_BITMASK (0x2000000U)
#define RMON_T_UNDERSIZE_Value26_BITMASK (0x4000000U)
#define RMON_T_UNDERSIZE_Value27_BITMASK (0x8000000U)
#define RMON_T_UNDERSIZE_Value28_BITMASK (0x10000000U)
#define RMON_T_UNDERSIZE_Value29_BITMASK (0x20000000U)
#define RMON_T_UNDERSIZE_Value30_BITMASK (0x40000000U)
#define RMON_T_UNDERSIZE_Value31_BITMASK (0x80000000U)
#define RMON_T_UNDERSIZE_Value_GRPMASK (0xFFFFFFFFU)
#define RMON_T_UNDERSIZE_Value_GRPPOS (0U)

/*** RMON_T_OVERSIZE - RMON Tx Packets > MAX_FL bytes, good crc.; 0x00001218 ***/
#define RMON_T_OVERSIZE               (*((volatile uint32 *)(&__IPSBAR[0x00001218UL])))
#define RMON_T_OVERSIZE_Value0_BITMASK (0x1U)
#define RMON_T_OVERSIZE_Value1_BITMASK (0x2U)
#define RMON_T_OVERSIZE_Value2_BITMASK (0x4U)
#define RMON_T_OVERSIZE_Value3_BITMASK (0x8U)
#define RMON_T_OVERSIZE_Value4_BITMASK (0x10U)
#define RMON_T_OVERSIZE_Value5_BITMASK (0x20U)
#define RMON_T_OVERSIZE_Value6_BITMASK (0x40U)
#define RMON_T_OVERSIZE_Value7_BITMASK (0x80U)
#define RMON_T_OVERSIZE_Value8_BITMASK (0x100U)
#define RMON_T_OVERSIZE_Value9_BITMASK (0x200U)
#define RMON_T_OVERSIZE_Value10_BITMASK (0x400U)
#define RMON_T_OVERSIZE_Value11_BITMASK (0x800U)
#define RMON_T_OVERSIZE_Value12_BITMASK (0x1000U)
#define RMON_T_OVERSIZE_Value13_BITMASK (0x2000U)
#define RMON_T_OVERSIZE_Value14_BITMASK (0x4000U)
#define RMON_T_OVERSIZE_Value15_BITMASK (0x8000U)
#define RMON_T_OVERSIZE_Value16_BITMASK (0x10000U)
#define RMON_T_OVERSIZE_Value17_BITMASK (0x20000U)
#define RMON_T_OVERSIZE_Value18_BITMASK (0x40000U)
#define RMON_T_OVERSIZE_Value19_BITMASK (0x80000U)
#define RMON_T_OVERSIZE_Value20_BITMASK (0x100000U)
#define RMON_T_OVERSIZE_Value21_BITMASK (0x200000U)
#define RMON_T_OVERSIZE_Value22_BITMASK (0x400000U)
#define RMON_T_OVERSIZE_Value23_BITMASK (0x800000U)
#define RMON_T_OVERSIZE_Value24_BITMASK (0x1000000U)
#define RMON_T_OVERSIZE_Value25_BITMASK (0x2000000U)
#define RMON_T_OVERSIZE_Value26_BITMASK (0x4000000U)
#define RMON_T_OVERSIZE_Value27_BITMASK (0x8000000U)
#define RMON_T_OVERSIZE_Value28_BITMASK (0x10000000U)
#define RMON_T_OVERSIZE_Value29_BITMASK (0x20000000U)
#define RMON_T_OVERSIZE_Value30_BITMASK (0x40000000U)
#define RMON_T_OVERSIZE_Value31_BITMASK (0x80000000U)
#define RMON_T_OVERSIZE_Value_GRPMASK (0xFFFFFFFFU)
#define RMON_T_OVERSIZE_Value_GRPPOS  (0U)

/*** RMON_T_FRAG - RMON Tx Packets < 64 bytes, bad crc.; 0x0000121C ***/
#define RMON_T_FRAG                   (*((volatile uint32 *)(&__IPSBAR[0x0000121CUL])))
#define RMON_T_FRAG_Value0_BITMASK    (0x1U)
#define RMON_T_FRAG_Value1_BITMASK    (0x2U)
#define RMON_T_FRAG_Value2_BITMASK    (0x4U)
#define RMON_T_FRAG_Value3_BITMASK    (0x8U)
#define RMON_T_FRAG_Value4_BITMASK    (0x10U)
#define RMON_T_FRAG_Value5_BITMASK    (0x20U)
#define RMON_T_FRAG_Value6_BITMASK    (0x40U)
#define RMON_T_FRAG_Value7_BITMASK    (0x80U)
#define RMON_T_FRAG_Value8_BITMASK    (0x100U)
#define RMON_T_FRAG_Value9_BITMASK    (0x200U)
#define RMON_T_FRAG_Value10_BITMASK   (0x400U)
#define RMON_T_FRAG_Value11_BITMASK   (0x800U)
#define RMON_T_FRAG_Value12_BITMASK   (0x1000U)
#define RMON_T_FRAG_Value13_BITMASK   (0x2000U)
#define RMON_T_FRAG_Value14_BITMASK   (0x4000U)
#define RMON_T_FRAG_Value15_BITMASK   (0x8000U)
#define RMON_T_FRAG_Value16_BITMASK   (0x10000U)
#define RMON_T_FRAG_Value17_BITMASK   (0x20000U)
#define RMON_T_FRAG_Value18_BITMASK   (0x40000U)
#define RMON_T_FRAG_Value19_BITMASK   (0x80000U)
#define RMON_T_FRAG_Value20_BITMASK   (0x100000U)
#define RMON_T_FRAG_Value21_BITMASK   (0x200000U)
#define RMON_T_FRAG_Value22_BITMASK   (0x400000U)
#define RMON_T_FRAG_Value23_BITMASK   (0x800000U)
#define RMON_T_FRAG_Value24_BITMASK   (0x1000000U)
#define RMON_T_FRAG_Value25_BITMASK   (0x2000000U)
#define RMON_T_FRAG_Value26_BITMASK   (0x4000000U)
#define RMON_T_FRAG_Value27_BITMASK   (0x8000000U)
#define RMON_T_FRAG_Value28_BITMASK   (0x10000000U)
#define RMON_T_FRAG_Value29_BITMASK   (0x20000000U)
#define RMON_T_FRAG_Value30_BITMASK   (0x40000000U)
#define RMON_T_FRAG_Value31_BITMASK   (0x80000000U)
#define RMON_T_FRAG_Value_GRPMASK     (0xFFFFFFFFU)
#define RMON_T_FRAG_Value_GRPPOS      (0U)

/*** RMON_T_JAB - RMON Tx Packets > MAX_FL bytes, bad crc.; 0x00001220 ***/
#define RMON_T_JAB                    (*((volatile uint32 *)(&__IPSBAR[0x00001220UL])))
#define RMON_T_JAB_Value0_BITMASK     (0x1U)
#define RMON_T_JAB_Value1_BITMASK     (0x2U)
#define RMON_T_JAB_Value2_BITMASK     (0x4U)
#define RMON_T_JAB_Value3_BITMASK     (0x8U)
#define RMON_T_JAB_Value4_BITMASK     (0x10U)
#define RMON_T_JAB_Value5_BITMASK     (0x20U)
#define RMON_T_JAB_Value6_BITMASK     (0x40U)
#define RMON_T_JAB_Value7_BITMASK     (0x80U)
#define RMON_T_JAB_Value8_BITMASK     (0x100U)
#define RMON_T_JAB_Value9_BITMASK     (0x200U)
#define RMON_T_JAB_Value10_BITMASK    (0x400U)
#define RMON_T_JAB_Value11_BITMASK    (0x800U)
#define RMON_T_JAB_Value12_BITMASK    (0x1000U)
#define RMON_T_JAB_Value13_BITMASK    (0x2000U)
#define RMON_T_JAB_Value14_BITMASK    (0x4000U)
#define RMON_T_JAB_Value15_BITMASK    (0x8000U)
#define RMON_T_JAB_Value16_BITMASK    (0x10000U)
#define RMON_T_JAB_Value17_BITMASK    (0x20000U)
#define RMON_T_JAB_Value18_BITMASK    (0x40000U)
#define RMON_T_JAB_Value19_BITMASK    (0x80000U)
#define RMON_T_JAB_Value20_BITMASK    (0x100000U)
#define RMON_T_JAB_Value21_BITMASK    (0x200000U)
#define RMON_T_JAB_Value22_BITMASK    (0x400000U)
#define RMON_T_JAB_Value23_BITMASK    (0x800000U)
#define RMON_T_JAB_Value24_BITMASK    (0x1000000U)
#define RMON_T_JAB_Value25_BITMASK    (0x2000000U)
#define RMON_T_JAB_Value26_BITMASK    (0x4000000U)
#define RMON_T_JAB_Value27_BITMASK    (0x8000000U)
#define RMON_T_JAB_Value28_BITMASK    (0x10000000U)
#define RMON_T_JAB_Value29_BITMASK    (0x20000000U)
#define RMON_T_JAB_Value30_BITMASK    (0x40000000U)
#define RMON_T_JAB_Value31_BITMASK    (0x80000000U)
#define RMON_T_JAB_Value_GRPMASK      (0xFFFFFFFFU)
#define RMON_T_JAB_Value_GRPPOS       (0U)

/*** RMON_T_COL - RMON Tx collision count.; 0x00001224 ***/
#define RMON_T_COL                    (*((volatile uint32 *)(&__IPSBAR[0x00001224UL])))
#define RMON_T_COL_Value0_BITMASK     (0x1U)
#define RMON_T_COL_Value1_BITMASK     (0x2U)
#define RMON_T_COL_Value2_BITMASK     (0x4U)
#define RMON_T_COL_Value3_BITMASK     (0x8U)
#define RMON_T_COL_Value4_BITMASK     (0x10U)
#define RMON_T_COL_Value5_BITMASK     (0x20U)
#define RMON_T_COL_Value6_BITMASK     (0x40U)
#define RMON_T_COL_Value7_BITMASK     (0x80U)
#define RMON_T_COL_Value8_BITMASK     (0x100U)
#define RMON_T_COL_Value9_BITMASK     (0x200U)
#define RMON_T_COL_Value10_BITMASK    (0x400U)
#define RMON_T_COL_Value11_BITMASK    (0x800U)
#define RMON_T_COL_Value12_BITMASK    (0x1000U)
#define RMON_T_COL_Value13_BITMASK    (0x2000U)
#define RMON_T_COL_Value14_BITMASK    (0x4000U)
#define RMON_T_COL_Value15_BITMASK    (0x8000U)
#define RMON_T_COL_Value16_BITMASK    (0x10000U)
#define RMON_T_COL_Value17_BITMASK    (0x20000U)
#define RMON_T_COL_Value18_BITMASK    (0x40000U)
#define RMON_T_COL_Value19_BITMASK    (0x80000U)
#define RMON_T_COL_Value20_BITMASK    (0x100000U)
#define RMON_T_COL_Value21_BITMASK    (0x200000U)
#define RMON_T_COL_Value22_BITMASK    (0x400000U)
#define RMON_T_COL_Value23_BITMASK    (0x800000U)
#define RMON_T_COL_Value24_BITMASK    (0x1000000U)
#define RMON_T_COL_Value25_BITMASK    (0x2000000U)
#define RMON_T_COL_Value26_BITMASK    (0x4000000U)
#define RMON_T_COL_Value27_BITMASK    (0x8000000U)
#define RMON_T_COL_Value28_BITMASK    (0x10000000U)
#define RMON_T_COL_Value29_BITMASK    (0x20000000U)
#define RMON_T_COL_Value30_BITMASK    (0x40000000U)
#define RMON_T_COL_Value31_BITMASK    (0x80000000U)
#define RMON_T_COL_Value_GRPMASK      (0xFFFFFFFFU)
#define RMON_T_COL_Value_GRPPOS       (0U)

/*** RMON_T_P64 - RMON Tx 64 byte packets.; 0x00001228 ***/
#define RMON_T_P64                    (*((volatile uint32 *)(&__IPSBAR[0x00001228UL])))
#define RMON_T_P64_Value0_BITMASK     (0x1U)
#define RMON_T_P64_Value1_BITMASK     (0x2U)
#define RMON_T_P64_Value2_BITMASK     (0x4U)
#define RMON_T_P64_Value3_BITMASK     (0x8U)
#define RMON_T_P64_Value4_BITMASK     (0x10U)
#define RMON_T_P64_Value5_BITMASK     (0x20U)
#define RMON_T_P64_Value6_BITMASK     (0x40U)
#define RMON_T_P64_Value7_BITMASK     (0x80U)
#define RMON_T_P64_Value8_BITMASK     (0x100U)
#define RMON_T_P64_Value9_BITMASK     (0x200U)
#define RMON_T_P64_Value10_BITMASK    (0x400U)
#define RMON_T_P64_Value11_BITMASK    (0x800U)
#define RMON_T_P64_Value12_BITMASK    (0x1000U)
#define RMON_T_P64_Value13_BITMASK    (0x2000U)
#define RMON_T_P64_Value14_BITMASK    (0x4000U)
#define RMON_T_P64_Value15_BITMASK    (0x8000U)
#define RMON_T_P64_Value16_BITMASK    (0x10000U)
#define RMON_T_P64_Value17_BITMASK    (0x20000U)
#define RMON_T_P64_Value18_BITMASK    (0x40000U)
#define RMON_T_P64_Value19_BITMASK    (0x80000U)
#define RMON_T_P64_Value20_BITMASK    (0x100000U)
#define RMON_T_P64_Value21_BITMASK    (0x200000U)
#define RMON_T_P64_Value22_BITMASK    (0x400000U)
#define RMON_T_P64_Value23_BITMASK    (0x800000U)
#define RMON_T_P64_Value24_BITMASK    (0x1000000U)
#define RMON_T_P64_Value25_BITMASK    (0x2000000U)
#define RMON_T_P64_Value26_BITMASK    (0x4000000U)
#define RMON_T_P64_Value27_BITMASK    (0x8000000U)
#define RMON_T_P64_Value28_BITMASK    (0x10000000U)
#define RMON_T_P64_Value29_BITMASK    (0x20000000U)
#define RMON_T_P64_Value30_BITMASK    (0x40000000U)
#define RMON_T_P64_Value31_BITMASK    (0x80000000U)
#define RMON_T_P64_Value_GRPMASK      (0xFFFFFFFFU)
#define RMON_T_P64_Value_GRPPOS       (0U)

/*** RMON_T_P65TO127 - RMON Tx 65 to 127 byte packets.; 0x0000122C ***/
#define RMON_T_P65TO127               (*((volatile uint32 *)(&__IPSBAR[0x0000122CUL])))
#define RMON_T_P65TO127_Value0_BITMASK (0x1U)
#define RMON_T_P65TO127_Value1_BITMASK (0x2U)
#define RMON_T_P65TO127_Value2_BITMASK (0x4U)
#define RMON_T_P65TO127_Value3_BITMASK (0x8U)
#define RMON_T_P65TO127_Value4_BITMASK (0x10U)
#define RMON_T_P65TO127_Value5_BITMASK (0x20U)
#define RMON_T_P65TO127_Value6_BITMASK (0x40U)
#define RMON_T_P65TO127_Value7_BITMASK (0x80U)
#define RMON_T_P65TO127_Value8_BITMASK (0x100U)
#define RMON_T_P65TO127_Value9_BITMASK (0x200U)
#define RMON_T_P65TO127_Value10_BITMASK (0x400U)
#define RMON_T_P65TO127_Value11_BITMASK (0x800U)
#define RMON_T_P65TO127_Value12_BITMASK (0x1000U)
#define RMON_T_P65TO127_Value13_BITMASK (0x2000U)
#define RMON_T_P65TO127_Value14_BITMASK (0x4000U)
#define RMON_T_P65TO127_Value15_BITMASK (0x8000U)
#define RMON_T_P65TO127_Value16_BITMASK (0x10000U)
#define RMON_T_P65TO127_Value17_BITMASK (0x20000U)
#define RMON_T_P65TO127_Value18_BITMASK (0x40000U)
#define RMON_T_P65TO127_Value19_BITMASK (0x80000U)
#define RMON_T_P65TO127_Value20_BITMASK (0x100000U)
#define RMON_T_P65TO127_Value21_BITMASK (0x200000U)
#define RMON_T_P65TO127_Value22_BITMASK (0x400000U)
#define RMON_T_P65TO127_Value23_BITMASK (0x800000U)
#define RMON_T_P65TO127_Value24_BITMASK (0x1000000U)
#define RMON_T_P65TO127_Value25_BITMASK (0x2000000U)
#define RMON_T_P65TO127_Value26_BITMASK (0x4000000U)
#define RMON_T_P65TO127_Value27_BITMASK (0x8000000U)
#define RMON_T_P65TO127_Value28_BITMASK (0x10000000U)
#define RMON_T_P65TO127_Value29_BITMASK (0x20000000U)
#define RMON_T_P65TO127_Value30_BITMASK (0x40000000U)
#define RMON_T_P65TO127_Value31_BITMASK (0x80000000U)
#define RMON_T_P65TO127_Value_GRPMASK (0xFFFFFFFFU)
#define RMON_T_P65TO127_Value_GRPPOS  (0U)

/*** RMON_T_P128TO255 - RMON Tx 128 to 255 byte packets.; 0x00001230 ***/
#define RMON_T_P128TO255              (*((volatile uint32 *)(&__IPSBAR[0x00001230UL])))
#define RMON_T_P128TO255_Value0_BITMASK (0x1U)
#define RMON_T_P128TO255_Value1_BITMASK (0x2U)
#define RMON_T_P128TO255_Value2_BITMASK (0x4U)
#define RMON_T_P128TO255_Value3_BITMASK (0x8U)
#define RMON_T_P128TO255_Value4_BITMASK (0x10U)
#define RMON_T_P128TO255_Value5_BITMASK (0x20U)
#define RMON_T_P128TO255_Value6_BITMASK (0x40U)
#define RMON_T_P128TO255_Value7_BITMASK (0x80U)
#define RMON_T_P128TO255_Value8_BITMASK (0x100U)
#define RMON_T_P128TO255_Value9_BITMASK (0x200U)
#define RMON_T_P128TO255_Value10_BITMASK (0x400U)
#define RMON_T_P128TO255_Value11_BITMASK (0x800U)
#define RMON_T_P128TO255_Value12_BITMASK (0x1000U)
#define RMON_T_P128TO255_Value13_BITMASK (0x2000U)
#define RMON_T_P128TO255_Value14_BITMASK (0x4000U)
#define RMON_T_P128TO255_Value15_BITMASK (0x8000U)
#define RMON_T_P128TO255_Value16_BITMASK (0x10000U)
#define RMON_T_P128TO255_Value17_BITMASK (0x20000U)
#define RMON_T_P128TO255_Value18_BITMASK (0x40000U)
#define RMON_T_P128TO255_Value19_BITMASK (0x80000U)
#define RMON_T_P128TO255_Value20_BITMASK (0x100000U)
#define RMON_T_P128TO255_Value21_BITMASK (0x200000U)
#define RMON_T_P128TO255_Value22_BITMASK (0x400000U)
#define RMON_T_P128TO255_Value23_BITMASK (0x800000U)
#define RMON_T_P128TO255_Value24_BITMASK (0x1000000U)
#define RMON_T_P128TO255_Value25_BITMASK (0x2000000U)
#define RMON_T_P128TO255_Value26_BITMASK (0x4000000U)
#define RMON_T_P128TO255_Value27_BITMASK (0x8000000U)
#define RMON_T_P128TO255_Value28_BITMASK (0x10000000U)
#define RMON_T_P128TO255_Value29_BITMASK (0x20000000U)
#define RMON_T_P128TO255_Value30_BITMASK (0x40000000U)
#define RMON_T_P128TO255_Value31_BITMASK (0x80000000U)
#define RMON_T_P128TO255_Value_GRPMASK (0xFFFFFFFFU)
#define RMON_T_P128TO255_Value_GRPPOS (0U)

/*** RMON_T_P256TO511 - RMON Tx 256 to 511 byte packets.; 0x00001234 ***/
#define RMON_T_P256TO511              (*((volatile uint32 *)(&__IPSBAR[0x00001234UL])))
#define RMON_T_P256TO511_Value0_BITMASK (0x1U)
#define RMON_T_P256TO511_Value1_BITMASK (0x2U)
#define RMON_T_P256TO511_Value2_BITMASK (0x4U)
#define RMON_T_P256TO511_Value3_BITMASK (0x8U)
#define RMON_T_P256TO511_Value4_BITMASK (0x10U)
#define RMON_T_P256TO511_Value5_BITMASK (0x20U)
#define RMON_T_P256TO511_Value6_BITMASK (0x40U)
#define RMON_T_P256TO511_Value7_BITMASK (0x80U)
#define RMON_T_P256TO511_Value8_BITMASK (0x100U)
#define RMON_T_P256TO511_Value9_BITMASK (0x200U)
#define RMON_T_P256TO511_Value10_BITMASK (0x400U)
#define RMON_T_P256TO511_Value11_BITMASK (0x800U)
#define RMON_T_P256TO511_Value12_BITMASK (0x1000U)
#define RMON_T_P256TO511_Value13_BITMASK (0x2000U)
#define RMON_T_P256TO511_Value14_BITMASK (0x4000U)
#define RMON_T_P256TO511_Value15_BITMASK (0x8000U)
#define RMON_T_P256TO511_Value16_BITMASK (0x10000U)
#define RMON_T_P256TO511_Value17_BITMASK (0x20000U)
#define RMON_T_P256TO511_Value18_BITMASK (0x40000U)
#define RMON_T_P256TO511_Value19_BITMASK (0x80000U)
#define RMON_T_P256TO511_Value20_BITMASK (0x100000U)
#define RMON_T_P256TO511_Value21_BITMASK (0x200000U)
#define RMON_T_P256TO511_Value22_BITMASK (0x400000U)
#define RMON_T_P256TO511_Value23_BITMASK (0x800000U)
#define RMON_T_P256TO511_Value24_BITMASK (0x1000000U)
#define RMON_T_P256TO511_Value25_BITMASK (0x2000000U)
#define RMON_T_P256TO511_Value26_BITMASK (0x4000000U)
#define RMON_T_P256TO511_Value27_BITMASK (0x8000000U)
#define RMON_T_P256TO511_Value28_BITMASK (0x10000000U)
#define RMON_T_P256TO511_Value29_BITMASK (0x20000000U)
#define RMON_T_P256TO511_Value30_BITMASK (0x40000000U)
#define RMON_T_P256TO511_Value31_BITMASK (0x80000000U)
#define RMON_T_P256TO511_Value_GRPMASK (0xFFFFFFFFU)
#define RMON_T_P256TO511_Value_GRPPOS (0U)

/*** RMON_T_P512TO1023 - RMON Tx 512 to 1023 byte packets.; 0x00001238 ***/
#define RMON_T_P512TO1023             (*((volatile uint32 *)(&__IPSBAR[0x00001238UL])))
#define RMON_T_P512TO1023_Value0_BITMASK (0x1U)
#define RMON_T_P512TO1023_Value1_BITMASK (0x2U)
#define RMON_T_P512TO1023_Value2_BITMASK (0x4U)
#define RMON_T_P512TO1023_Value3_BITMASK (0x8U)
#define RMON_T_P512TO1023_Value4_BITMASK (0x10U)
#define RMON_T_P512TO1023_Value5_BITMASK (0x20U)
#define RMON_T_P512TO1023_Value6_BITMASK (0x40U)
#define RMON_T_P512TO1023_Value7_BITMASK (0x80U)
#define RMON_T_P512TO1023_Value8_BITMASK (0x100U)
#define RMON_T_P512TO1023_Value9_BITMASK (0x200U)
#define RMON_T_P512TO1023_Value10_BITMASK (0x400U)
#define RMON_T_P512TO1023_Value11_BITMASK (0x800U)
#define RMON_T_P512TO1023_Value12_BITMASK (0x1000U)
#define RMON_T_P512TO1023_Value13_BITMASK (0x2000U)
#define RMON_T_P512TO1023_Value14_BITMASK (0x4000U)
#define RMON_T_P512TO1023_Value15_BITMASK (0x8000U)
#define RMON_T_P512TO1023_Value16_BITMASK (0x10000U)
#define RMON_T_P512TO1023_Value17_BITMASK (0x20000U)
#define RMON_T_P512TO1023_Value18_BITMASK (0x40000U)
#define RMON_T_P512TO1023_Value19_BITMASK (0x80000U)
#define RMON_T_P512TO1023_Value20_BITMASK (0x100000U)
#define RMON_T_P512TO1023_Value21_BITMASK (0x200000U)
#define RMON_T_P512TO1023_Value22_BITMASK (0x400000U)
#define RMON_T_P512TO1023_Value23_BITMASK (0x800000U)
#define RMON_T_P512TO1023_Value24_BITMASK (0x1000000U)
#define RMON_T_P512TO1023_Value25_BITMASK (0x2000000U)
#define RMON_T_P512TO1023_Value26_BITMASK (0x4000000U)
#define RMON_T_P512TO1023_Value27_BITMASK (0x8000000U)
#define RMON_T_P512TO1023_Value28_BITMASK (0x10000000U)
#define RMON_T_P512TO1023_Value29_BITMASK (0x20000000U)
#define RMON_T_P512TO1023_Value30_BITMASK (0x40000000U)
#define RMON_T_P512TO1023_Value31_BITMASK (0x80000000U)
#define RMON_T_P512TO1023_Value_GRPMASK (0xFFFFFFFFU)
#define RMON_T_P512TO1023_Value_GRPPOS (0U)

/*** RMON_T_P1024TO2047 - RMON Tx 1024 to 2047 byte packets.; 0x0000123C ***/
#define RMON_T_P1024TO2047            (*((volatile uint32 *)(&__IPSBAR[0x0000123CUL])))
#define RMON_T_P1024TO2047_Value0_BITMASK (0x1U)
#define RMON_T_P1024TO2047_Value1_BITMASK (0x2U)
#define RMON_T_P1024TO2047_Value2_BITMASK (0x4U)
#define RMON_T_P1024TO2047_Value3_BITMASK (0x8U)
#define RMON_T_P1024TO2047_Value4_BITMASK (0x10U)
#define RMON_T_P1024TO2047_Value5_BITMASK (0x20U)
#define RMON_T_P1024TO2047_Value6_BITMASK (0x40U)
#define RMON_T_P1024TO2047_Value7_BITMASK (0x80U)
#define RMON_T_P1024TO2047_Value8_BITMASK (0x100U)
#define RMON_T_P1024TO2047_Value9_BITMASK (0x200U)
#define RMON_T_P1024TO2047_Value10_BITMASK (0x400U)
#define RMON_T_P1024TO2047_Value11_BITMASK (0x800U)
#define RMON_T_P1024TO2047_Value12_BITMASK (0x1000U)
#define RMON_T_P1024TO2047_Value13_BITMASK (0x2000U)
#define RMON_T_P1024TO2047_Value14_BITMASK (0x4000U)
#define RMON_T_P1024TO2047_Value15_BITMASK (0x8000U)
#define RMON_T_P1024TO2047_Value16_BITMASK (0x10000U)
#define RMON_T_P1024TO2047_Value17_BITMASK (0x20000U)
#define RMON_T_P1024TO2047_Value18_BITMASK (0x40000U)
#define RMON_T_P1024TO2047_Value19_BITMASK (0x80000U)
#define RMON_T_P1024TO2047_Value20_BITMASK (0x100000U)
#define RMON_T_P1024TO2047_Value21_BITMASK (0x200000U)
#define RMON_T_P1024TO2047_Value22_BITMASK (0x400000U)
#define RMON_T_P1024TO2047_Value23_BITMASK (0x800000U)
#define RMON_T_P1024TO2047_Value24_BITMASK (0x1000000U)
#define RMON_T_P1024TO2047_Value25_BITMASK (0x2000000U)
#define RMON_T_P1024TO2047_Value26_BITMASK (0x4000000U)
#define RMON_T_P1024TO2047_Value27_BITMASK (0x8000000U)
#define RMON_T_P1024TO2047_Value28_BITMASK (0x10000000U)
#define RMON_T_P1024TO2047_Value29_BITMASK (0x20000000U)
#define RMON_T_P1024TO2047_Value30_BITMASK (0x40000000U)
#define RMON_T_P1024TO2047_Value31_BITMASK (0x80000000U)
#define RMON_T_P1024TO2047_Value_GRPMASK (0xFFFFFFFFU)
#define RMON_T_P1024TO2047_Value_GRPPOS (0U)

/*** RMON_T_P_GTE2048 - RMON Tx packets w > 2048 bytes.; 0x00001240 ***/
#define RMON_T_P_GTE2048              (*((volatile uint32 *)(&__IPSBAR[0x00001240UL])))
#define RMON_T_P_GTE2048_Value0_BITMASK (0x1U)
#define RMON_T_P_GTE2048_Value1_BITMASK (0x2U)
#define RMON_T_P_GTE2048_Value2_BITMASK (0x4U)
#define RMON_T_P_GTE2048_Value3_BITMASK (0x8U)
#define RMON_T_P_GTE2048_Value4_BITMASK (0x10U)
#define RMON_T_P_GTE2048_Value5_BITMASK (0x20U)
#define RMON_T_P_GTE2048_Value6_BITMASK (0x40U)
#define RMON_T_P_GTE2048_Value7_BITMASK (0x80U)
#define RMON_T_P_GTE2048_Value8_BITMASK (0x100U)
#define RMON_T_P_GTE2048_Value9_BITMASK (0x200U)
#define RMON_T_P_GTE2048_Value10_BITMASK (0x400U)
#define RMON_T_P_GTE2048_Value11_BITMASK (0x800U)
#define RMON_T_P_GTE2048_Value12_BITMASK (0x1000U)
#define RMON_T_P_GTE2048_Value13_BITMASK (0x2000U)
#define RMON_T_P_GTE2048_Value14_BITMASK (0x4000U)
#define RMON_T_P_GTE2048_Value15_BITMASK (0x8000U)
#define RMON_T_P_GTE2048_Value16_BITMASK (0x10000U)
#define RMON_T_P_GTE2048_Value17_BITMASK (0x20000U)
#define RMON_T_P_GTE2048_Value18_BITMASK (0x40000U)
#define RMON_T_P_GTE2048_Value19_BITMASK (0x80000U)
#define RMON_T_P_GTE2048_Value20_BITMASK (0x100000U)
#define RMON_T_P_GTE2048_Value21_BITMASK (0x200000U)
#define RMON_T_P_GTE2048_Value22_BITMASK (0x400000U)
#define RMON_T_P_GTE2048_Value23_BITMASK (0x800000U)
#define RMON_T_P_GTE2048_Value24_BITMASK (0x1000000U)
#define RMON_T_P_GTE2048_Value25_BITMASK (0x2000000U)
#define RMON_T_P_GTE2048_Value26_BITMASK (0x4000000U)
#define RMON_T_P_GTE2048_Value27_BITMASK (0x8000000U)
#define RMON_T_P_GTE2048_Value28_BITMASK (0x10000000U)
#define RMON_T_P_GTE2048_Value29_BITMASK (0x20000000U)
#define RMON_T_P_GTE2048_Value30_BITMASK (0x40000000U)
#define RMON_T_P_GTE2048_Value31_BITMASK (0x80000000U)
#define RMON_T_P_GTE2048_Value_GRPMASK (0xFFFFFFFFU)
#define RMON_T_P_GTE2048_Value_GRPPOS (0U)

/*** RMON_T_OCTETS - RMON Tx Octets.; 0x00001244 ***/
#define RMON_T_OCTETS                 (*((volatile uint32 *)(&__IPSBAR[0x00001244UL])))
#define RMON_T_OCTETS_Value0_BITMASK  (0x1U)
#define RMON_T_OCTETS_Value1_BITMASK  (0x2U)
#define RMON_T_OCTETS_Value2_BITMASK  (0x4U)
#define RMON_T_OCTETS_Value3_BITMASK  (0x8U)
#define RMON_T_OCTETS_Value4_BITMASK  (0x10U)
#define RMON_T_OCTETS_Value5_BITMASK  (0x20U)
#define RMON_T_OCTETS_Value6_BITMASK  (0x40U)
#define RMON_T_OCTETS_Value7_BITMASK  (0x80U)
#define RMON_T_OCTETS_Value8_BITMASK  (0x100U)
#define RMON_T_OCTETS_Value9_BITMASK  (0x200U)
#define RMON_T_OCTETS_Value10_BITMASK (0x400U)
#define RMON_T_OCTETS_Value11_BITMASK (0x800U)
#define RMON_T_OCTETS_Value12_BITMASK (0x1000U)
#define RMON_T_OCTETS_Value13_BITMASK (0x2000U)
#define RMON_T_OCTETS_Value14_BITMASK (0x4000U)
#define RMON_T_OCTETS_Value15_BITMASK (0x8000U)
#define RMON_T_OCTETS_Value16_BITMASK (0x10000U)
#define RMON_T_OCTETS_Value17_BITMASK (0x20000U)
#define RMON_T_OCTETS_Value18_BITMASK (0x40000U)
#define RMON_T_OCTETS_Value19_BITMASK (0x80000U)
#define RMON_T_OCTETS_Value20_BITMASK (0x100000U)
#define RMON_T_OCTETS_Value21_BITMASK (0x200000U)
#define RMON_T_OCTETS_Value22_BITMASK (0x400000U)
#define RMON_T_OCTETS_Value23_BITMASK (0x800000U)
#define RMON_T_OCTETS_Value24_BITMASK (0x1000000U)
#define RMON_T_OCTETS_Value25_BITMASK (0x2000000U)
#define RMON_T_OCTETS_Value26_BITMASK (0x4000000U)
#define RMON_T_OCTETS_Value27_BITMASK (0x8000000U)
#define RMON_T_OCTETS_Value28_BITMASK (0x10000000U)
#define RMON_T_OCTETS_Value29_BITMASK (0x20000000U)
#define RMON_T_OCTETS_Value30_BITMASK (0x40000000U)
#define RMON_T_OCTETS_Value31_BITMASK (0x80000000U)
#define RMON_T_OCTETS_Value_GRPMASK   (0xFFFFFFFFU)
#define RMON_T_OCTETS_Value_GRPPOS    (0U)

/*** IEEE_T_DROP - Count of frames not counted correctly.; 0x00001248 ***/
#define IEEE_T_DROP                   (*((volatile uint32 *)(&__IPSBAR[0x00001248UL])))
#define IEEE_T_DROP_Value0_BITMASK    (0x1U)
#define IEEE_T_DROP_Value1_BITMASK    (0x2U)
#define IEEE_T_DROP_Value2_BITMASK    (0x4U)
#define IEEE_T_DROP_Value3_BITMASK    (0x8U)
#define IEEE_T_DROP_Value4_BITMASK    (0x10U)
#define IEEE_T_DROP_Value5_BITMASK    (0x20U)
#define IEEE_T_DROP_Value6_BITMASK    (0x40U)
#define IEEE_T_DROP_Value7_BITMASK    (0x80U)
#define IEEE_T_DROP_Value8_BITMASK    (0x100U)
#define IEEE_T_DROP_Value9_BITMASK    (0x200U)
#define IEEE_T_DROP_Value10_BITMASK   (0x400U)
#define IEEE_T_DROP_Value11_BITMASK   (0x800U)
#define IEEE_T_DROP_Value12_BITMASK   (0x1000U)
#define IEEE_T_DROP_Value13_BITMASK   (0x2000U)
#define IEEE_T_DROP_Value14_BITMASK   (0x4000U)
#define IEEE_T_DROP_Value15_BITMASK   (0x8000U)
#define IEEE_T_DROP_Value16_BITMASK   (0x10000U)
#define IEEE_T_DROP_Value17_BITMASK   (0x20000U)
#define IEEE_T_DROP_Value18_BITMASK   (0x40000U)
#define IEEE_T_DROP_Value19_BITMASK   (0x80000U)
#define IEEE_T_DROP_Value20_BITMASK   (0x100000U)
#define IEEE_T_DROP_Value21_BITMASK   (0x200000U)
#define IEEE_T_DROP_Value22_BITMASK   (0x400000U)
#define IEEE_T_DROP_Value23_BITMASK   (0x800000U)
#define IEEE_T_DROP_Value24_BITMASK   (0x1000000U)
#define IEEE_T_DROP_Value25_BITMASK   (0x2000000U)
#define IEEE_T_DROP_Value26_BITMASK   (0x4000000U)
#define IEEE_T_DROP_Value27_BITMASK   (0x8000000U)
#define IEEE_T_DROP_Value28_BITMASK   (0x10000000U)
#define IEEE_T_DROP_Value29_BITMASK   (0x20000000U)
#define IEEE_T_DROP_Value30_BITMASK   (0x40000000U)
#define IEEE_T_DROP_Value31_BITMASK   (0x80000000U)
#define IEEE_T_DROP_Value_GRPMASK     (0xFFFFFFFFU)
#define IEEE_T_DROP_Value_GRPPOS      (0U)

/*** IEEE_T_FRAME_OK - Frames Transmitted OK.; 0x0000124C ***/
#define IEEE_T_FRAME_OK               (*((volatile uint32 *)(&__IPSBAR[0x0000124CUL])))
#define IEEE_T_FRAME_OK_Value0_BITMASK (0x1U)
#define IEEE_T_FRAME_OK_Value1_BITMASK (0x2U)
#define IEEE_T_FRAME_OK_Value2_BITMASK (0x4U)
#define IEEE_T_FRAME_OK_Value3_BITMASK (0x8U)
#define IEEE_T_FRAME_OK_Value4_BITMASK (0x10U)
#define IEEE_T_FRAME_OK_Value5_BITMASK (0x20U)
#define IEEE_T_FRAME_OK_Value6_BITMASK (0x40U)
#define IEEE_T_FRAME_OK_Value7_BITMASK (0x80U)
#define IEEE_T_FRAME_OK_Value8_BITMASK (0x100U)
#define IEEE_T_FRAME_OK_Value9_BITMASK (0x200U)
#define IEEE_T_FRAME_OK_Value10_BITMASK (0x400U)
#define IEEE_T_FRAME_OK_Value11_BITMASK (0x800U)
#define IEEE_T_FRAME_OK_Value12_BITMASK (0x1000U)
#define IEEE_T_FRAME_OK_Value13_BITMASK (0x2000U)
#define IEEE_T_FRAME_OK_Value14_BITMASK (0x4000U)
#define IEEE_T_FRAME_OK_Value15_BITMASK (0x8000U)
#define IEEE_T_FRAME_OK_Value16_BITMASK (0x10000U)
#define IEEE_T_FRAME_OK_Value17_BITMASK (0x20000U)
#define IEEE_T_FRAME_OK_Value18_BITMASK (0x40000U)
#define IEEE_T_FRAME_OK_Value19_BITMASK (0x80000U)
#define IEEE_T_FRAME_OK_Value20_BITMASK (0x100000U)
#define IEEE_T_FRAME_OK_Value21_BITMASK (0x200000U)
#define IEEE_T_FRAME_OK_Value22_BITMASK (0x400000U)
#define IEEE_T_FRAME_OK_Value23_BITMASK (0x800000U)
#define IEEE_T_FRAME_OK_Value24_BITMASK (0x1000000U)
#define IEEE_T_FRAME_OK_Value25_BITMASK (0x2000000U)
#define IEEE_T_FRAME_OK_Value26_BITMASK (0x4000000U)
#define IEEE_T_FRAME_OK_Value27_BITMASK (0x8000000U)
#define IEEE_T_FRAME_OK_Value28_BITMASK (0x10000000U)
#define IEEE_T_FRAME_OK_Value29_BITMASK (0x20000000U)
#define IEEE_T_FRAME_OK_Value30_BITMASK (0x40000000U)
#define IEEE_T_FRAME_OK_Value31_BITMASK (0x80000000U)
#define IEEE_T_FRAME_OK_Value_GRPMASK (0xFFFFFFFFU)
#define IEEE_T_FRAME_OK_Value_GRPPOS  (0U)

/*** IEEE_T_1COL - Frames Transmitted with Single Collision.; 0x00001250 ***/
#define IEEE_T_1COL                   (*((volatile uint32 *)(&__IPSBAR[0x00001250UL])))
#define IEEE_T_1COL_Value0_BITMASK    (0x1U)
#define IEEE_T_1COL_Value1_BITMASK    (0x2U)
#define IEEE_T_1COL_Value2_BITMASK    (0x4U)
#define IEEE_T_1COL_Value3_BITMASK    (0x8U)
#define IEEE_T_1COL_Value4_BITMASK    (0x10U)
#define IEEE_T_1COL_Value5_BITMASK    (0x20U)
#define IEEE_T_1COL_Value6_BITMASK    (0x40U)
#define IEEE_T_1COL_Value7_BITMASK    (0x80U)
#define IEEE_T_1COL_Value8_BITMASK    (0x100U)
#define IEEE_T_1COL_Value9_BITMASK    (0x200U)
#define IEEE_T_1COL_Value10_BITMASK   (0x400U)
#define IEEE_T_1COL_Value11_BITMASK   (0x800U)
#define IEEE_T_1COL_Value12_BITMASK   (0x1000U)
#define IEEE_T_1COL_Value13_BITMASK   (0x2000U)
#define IEEE_T_1COL_Value14_BITMASK   (0x4000U)
#define IEEE_T_1COL_Value15_BITMASK   (0x8000U)
#define IEEE_T_1COL_Value16_BITMASK   (0x10000U)
#define IEEE_T_1COL_Value17_BITMASK   (0x20000U)
#define IEEE_T_1COL_Value18_BITMASK   (0x40000U)
#define IEEE_T_1COL_Value19_BITMASK   (0x80000U)
#define IEEE_T_1COL_Value20_BITMASK   (0x100000U)
#define IEEE_T_1COL_Value21_BITMASK   (0x200000U)
#define IEEE_T_1COL_Value22_BITMASK   (0x400000U)
#define IEEE_T_1COL_Value23_BITMASK   (0x800000U)
#define IEEE_T_1COL_Value24_BITMASK   (0x1000000U)
#define IEEE_T_1COL_Value25_BITMASK   (0x2000000U)
#define IEEE_T_1COL_Value26_BITMASK   (0x4000000U)
#define IEEE_T_1COL_Value27_BITMASK   (0x8000000U)
#define IEEE_T_1COL_Value28_BITMASK   (0x10000000U)
#define IEEE_T_1COL_Value29_BITMASK   (0x20000000U)
#define IEEE_T_1COL_Value30_BITMASK   (0x40000000U)
#define IEEE_T_1COL_Value31_BITMASK   (0x80000000U)
#define IEEE_T_1COL_Value_GRPMASK     (0xFFFFFFFFU)
#define IEEE_T_1COL_Value_GRPPOS      (0U)

/*** IEEE_T_MCOL - Frames Transmitted with Multiple Collisions.; 0x00001254 ***/
#define IEEE_T_MCOL                   (*((volatile uint32 *)(&__IPSBAR[0x00001254UL])))
#define IEEE_T_MCOL_Value0_BITMASK    (0x1U)
#define IEEE_T_MCOL_Value1_BITMASK    (0x2U)
#define IEEE_T_MCOL_Value2_BITMASK    (0x4U)
#define IEEE_T_MCOL_Value3_BITMASK    (0x8U)
#define IEEE_T_MCOL_Value4_BITMASK    (0x10U)
#define IEEE_T_MCOL_Value5_BITMASK    (0x20U)
#define IEEE_T_MCOL_Value6_BITMASK    (0x40U)
#define IEEE_T_MCOL_Value7_BITMASK    (0x80U)
#define IEEE_T_MCOL_Value8_BITMASK    (0x100U)
#define IEEE_T_MCOL_Value9_BITMASK    (0x200U)
#define IEEE_T_MCOL_Value10_BITMASK   (0x400U)
#define IEEE_T_MCOL_Value11_BITMASK   (0x800U)
#define IEEE_T_MCOL_Value12_BITMASK   (0x1000U)
#define IEEE_T_MCOL_Value13_BITMASK   (0x2000U)
#define IEEE_T_MCOL_Value14_BITMASK   (0x4000U)
#define IEEE_T_MCOL_Value15_BITMASK   (0x8000U)
#define IEEE_T_MCOL_Value16_BITMASK   (0x10000U)
#define IEEE_T_MCOL_Value17_BITMASK   (0x20000U)
#define IEEE_T_MCOL_Value18_BITMASK   (0x40000U)
#define IEEE_T_MCOL_Value19_BITMASK   (0x80000U)
#define IEEE_T_MCOL_Value20_BITMASK   (0x100000U)
#define IEEE_T_MCOL_Value21_BITMASK   (0x200000U)
#define IEEE_T_MCOL_Value22_BITMASK   (0x400000U)
#define IEEE_T_MCOL_Value23_BITMASK   (0x800000U)
#define IEEE_T_MCOL_Value24_BITMASK   (0x1000000U)
#define IEEE_T_MCOL_Value25_BITMASK   (0x2000000U)
#define IEEE_T_MCOL_Value26_BITMASK   (0x4000000U)
#define IEEE_T_MCOL_Value27_BITMASK   (0x8000000U)
#define IEEE_T_MCOL_Value28_BITMASK   (0x10000000U)
#define IEEE_T_MCOL_Value29_BITMASK   (0x20000000U)
#define IEEE_T_MCOL_Value30_BITMASK   (0x40000000U)
#define IEEE_T_MCOL_Value31_BITMASK   (0x80000000U)
#define IEEE_T_MCOL_Value_GRPMASK     (0xFFFFFFFFU)
#define IEEE_T_MCOL_Value_GRPPOS      (0U)

/*** IEEE_T_DEF - Frames Transmitted after Deferral Delay.; 0x00001258 ***/
#define IEEE_T_DEF                    (*((volatile uint32 *)(&__IPSBAR[0x00001258UL])))
#define IEEE_T_DEF_Value0_BITMASK     (0x1U)
#define IEEE_T_DEF_Value1_BITMASK     (0x2U)
#define IEEE_T_DEF_Value2_BITMASK     (0x4U)
#define IEEE_T_DEF_Value3_BITMASK     (0x8U)
#define IEEE_T_DEF_Value4_BITMASK     (0x10U)
#define IEEE_T_DEF_Value5_BITMASK     (0x20U)
#define IEEE_T_DEF_Value6_BITMASK     (0x40U)
#define IEEE_T_DEF_Value7_BITMASK     (0x80U)
#define IEEE_T_DEF_Value8_BITMASK     (0x100U)
#define IEEE_T_DEF_Value9_BITMASK     (0x200U)
#define IEEE_T_DEF_Value10_BITMASK    (0x400U)
#define IEEE_T_DEF_Value11_BITMASK    (0x800U)
#define IEEE_T_DEF_Value12_BITMASK    (0x1000U)
#define IEEE_T_DEF_Value13_BITMASK    (0x2000U)
#define IEEE_T_DEF_Value14_BITMASK    (0x4000U)
#define IEEE_T_DEF_Value15_BITMASK    (0x8000U)
#define IEEE_T_DEF_Value16_BITMASK    (0x10000U)
#define IEEE_T_DEF_Value17_BITMASK    (0x20000U)
#define IEEE_T_DEF_Value18_BITMASK    (0x40000U)
#define IEEE_T_DEF_Value19_BITMASK    (0x80000U)
#define IEEE_T_DEF_Value20_BITMASK    (0x100000U)
#define IEEE_T_DEF_Value21_BITMASK    (0x200000U)
#define IEEE_T_DEF_Value22_BITMASK    (0x400000U)
#define IEEE_T_DEF_Value23_BITMASK    (0x800000U)
#define IEEE_T_DEF_Value24_BITMASK    (0x1000000U)
#define IEEE_T_DEF_Value25_BITMASK    (0x2000000U)
#define IEEE_T_DEF_Value26_BITMASK    (0x4000000U)
#define IEEE_T_DEF_Value27_BITMASK    (0x8000000U)
#define IEEE_T_DEF_Value28_BITMASK    (0x10000000U)
#define IEEE_T_DEF_Value29_BITMASK    (0x20000000U)
#define IEEE_T_DEF_Value30_BITMASK    (0x40000000U)
#define IEEE_T_DEF_Value31_BITMASK    (0x80000000U)
#define IEEE_T_DEF_Value_GRPMASK      (0xFFFFFFFFU)
#define IEEE_T_DEF_Value_GRPPOS       (0U)

/*** IEEE_T_LCOL - Frames Transmitted with Late Collision.; 0x0000125C ***/
#define IEEE_T_LCOL                   (*((volatile uint32 *)(&__IPSBAR[0x0000125CUL])))
#define IEEE_T_LCOL_Value0_BITMASK    (0x1U)
#define IEEE_T_LCOL_Value1_BITMASK    (0x2U)
#define IEEE_T_LCOL_Value2_BITMASK    (0x4U)
#define IEEE_T_LCOL_Value3_BITMASK    (0x8U)
#define IEEE_T_LCOL_Value4_BITMASK    (0x10U)
#define IEEE_T_LCOL_Value5_BITMASK    (0x20U)
#define IEEE_T_LCOL_Value6_BITMASK    (0x40U)
#define IEEE_T_LCOL_Value7_BITMASK    (0x80U)
#define IEEE_T_LCOL_Value8_BITMASK    (0x100U)
#define IEEE_T_LCOL_Value9_BITMASK    (0x200U)
#define IEEE_T_LCOL_Value10_BITMASK   (0x400U)
#define IEEE_T_LCOL_Value11_BITMASK   (0x800U)
#define IEEE_T_LCOL_Value12_BITMASK   (0x1000U)
#define IEEE_T_LCOL_Value13_BITMASK   (0x2000U)
#define IEEE_T_LCOL_Value14_BITMASK   (0x4000U)
#define IEEE_T_LCOL_Value15_BITMASK   (0x8000U)
#define IEEE_T_LCOL_Value16_BITMASK   (0x10000U)
#define IEEE_T_LCOL_Value17_BITMASK   (0x20000U)
#define IEEE_T_LCOL_Value18_BITMASK   (0x40000U)
#define IEEE_T_LCOL_Value19_BITMASK   (0x80000U)
#define IEEE_T_LCOL_Value20_BITMASK   (0x100000U)
#define IEEE_T_LCOL_Value21_BITMASK   (0x200000U)
#define IEEE_T_LCOL_Value22_BITMASK   (0x400000U)
#define IEEE_T_LCOL_Value23_BITMASK   (0x800000U)
#define IEEE_T_LCOL_Value24_BITMASK   (0x1000000U)
#define IEEE_T_LCOL_Value25_BITMASK   (0x2000000U)
#define IEEE_T_LCOL_Value26_BITMASK   (0x4000000U)
#define IEEE_T_LCOL_Value27_BITMASK   (0x8000000U)
#define IEEE_T_LCOL_Value28_BITMASK   (0x10000000U)
#define IEEE_T_LCOL_Value29_BITMASK   (0x20000000U)
#define IEEE_T_LCOL_Value30_BITMASK   (0x40000000U)
#define IEEE_T_LCOL_Value31_BITMASK   (0x80000000U)
#define IEEE_T_LCOL_Value_GRPMASK     (0xFFFFFFFFU)
#define IEEE_T_LCOL_Value_GRPPOS      (0U)

/*** IEEE_T_EXCOL - Frames Transmitted with Excessive Collisions.; 0x00001260 ***/
#define IEEE_T_EXCOL                  (*((volatile uint32 *)(&__IPSBAR[0x00001260UL])))
#define IEEE_T_EXCOL_Value0_BITMASK   (0x1U)
#define IEEE_T_EXCOL_Value1_BITMASK   (0x2U)
#define IEEE_T_EXCOL_Value2_BITMASK   (0x4U)
#define IEEE_T_EXCOL_Value3_BITMASK   (0x8U)
#define IEEE_T_EXCOL_Value4_BITMASK   (0x10U)
#define IEEE_T_EXCOL_Value5_BITMASK   (0x20U)
#define IEEE_T_EXCOL_Value6_BITMASK   (0x40U)
#define IEEE_T_EXCOL_Value7_BITMASK   (0x80U)
#define IEEE_T_EXCOL_Value8_BITMASK   (0x100U)
#define IEEE_T_EXCOL_Value9_BITMASK   (0x200U)
#define IEEE_T_EXCOL_Value10_BITMASK  (0x400U)
#define IEEE_T_EXCOL_Value11_BITMASK  (0x800U)
#define IEEE_T_EXCOL_Value12_BITMASK  (0x1000U)
#define IEEE_T_EXCOL_Value13_BITMASK  (0x2000U)
#define IEEE_T_EXCOL_Value14_BITMASK  (0x4000U)
#define IEEE_T_EXCOL_Value15_BITMASK  (0x8000U)
#define IEEE_T_EXCOL_Value16_BITMASK  (0x10000U)
#define IEEE_T_EXCOL_Value17_BITMASK  (0x20000U)
#define IEEE_T_EXCOL_Value18_BITMASK  (0x40000U)
#define IEEE_T_EXCOL_Value19_BITMASK  (0x80000U)
#define IEEE_T_EXCOL_Value20_BITMASK  (0x100000U)
#define IEEE_T_EXCOL_Value21_BITMASK  (0x200000U)
#define IEEE_T_EXCOL_Value22_BITMASK  (0x400000U)
#define IEEE_T_EXCOL_Value23_BITMASK  (0x800000U)
#define IEEE_T_EXCOL_Value24_BITMASK  (0x1000000U)
#define IEEE_T_EXCOL_Value25_BITMASK  (0x2000000U)
#define IEEE_T_EXCOL_Value26_BITMASK  (0x4000000U)
#define IEEE_T_EXCOL_Value27_BITMASK  (0x8000000U)
#define IEEE_T_EXCOL_Value28_BITMASK  (0x10000000U)
#define IEEE_T_EXCOL_Value29_BITMASK  (0x20000000U)
#define IEEE_T_EXCOL_Value30_BITMASK  (0x40000000U)
#define IEEE_T_EXCOL_Value31_BITMASK  (0x80000000U)
#define IEEE_T_EXCOL_Value_GRPMASK    (0xFFFFFFFFU)
#define IEEE_T_EXCOL_Value_GRPPOS     (0U)

/*** IEEE_T_MACERR - Frames Transmitted with Tx FIFO Underrun.; 0x00001264 ***/
#define IEEE_T_MACERR                 (*((volatile uint32 *)(&__IPSBAR[0x00001264UL])))
#define IEEE_T_MACERR_Value0_BITMASK  (0x1U)
#define IEEE_T_MACERR_Value1_BITMASK  (0x2U)
#define IEEE_T_MACERR_Value2_BITMASK  (0x4U)
#define IEEE_T_MACERR_Value3_BITMASK  (0x8U)
#define IEEE_T_MACERR_Value4_BITMASK  (0x10U)
#define IEEE_T_MACERR_Value5_BITMASK  (0x20U)
#define IEEE_T_MACERR_Value6_BITMASK  (0x40U)
#define IEEE_T_MACERR_Value7_BITMASK  (0x80U)
#define IEEE_T_MACERR_Value8_BITMASK  (0x100U)
#define IEEE_T_MACERR_Value9_BITMASK  (0x200U)
#define IEEE_T_MACERR_Value10_BITMASK (0x400U)
#define IEEE_T_MACERR_Value11_BITMASK (0x800U)
#define IEEE_T_MACERR_Value12_BITMASK (0x1000U)
#define IEEE_T_MACERR_Value13_BITMASK (0x2000U)
#define IEEE_T_MACERR_Value14_BITMASK (0x4000U)
#define IEEE_T_MACERR_Value15_BITMASK (0x8000U)
#define IEEE_T_MACERR_Value16_BITMASK (0x10000U)
#define IEEE_T_MACERR_Value17_BITMASK (0x20000U)
#define IEEE_T_MACERR_Value18_BITMASK (0x40000U)
#define IEEE_T_MACERR_Value19_BITMASK (0x80000U)
#define IEEE_T_MACERR_Value20_BITMASK (0x100000U)
#define IEEE_T_MACERR_Value21_BITMASK (0x200000U)
#define IEEE_T_MACERR_Value22_BITMASK (0x400000U)
#define IEEE_T_MACERR_Value23_BITMASK (0x800000U)
#define IEEE_T_MACERR_Value24_BITMASK (0x1000000U)
#define IEEE_T_MACERR_Value25_BITMASK (0x2000000U)
#define IEEE_T_MACERR_Value26_BITMASK (0x4000000U)
#define IEEE_T_MACERR_Value27_BITMASK (0x8000000U)
#define IEEE_T_MACERR_Value28_BITMASK (0x10000000U)
#define IEEE_T_MACERR_Value29_BITMASK (0x20000000U)
#define IEEE_T_MACERR_Value30_BITMASK (0x40000000U)
#define IEEE_T_MACERR_Value31_BITMASK (0x80000000U)
#define IEEE_T_MACERR_Value_GRPMASK   (0xFFFFFFFFU)
#define IEEE_T_MACERR_Value_GRPPOS    (0U)

/*** IEEE_T_CSERR - Frames Transmitted with Carrier Sense Error.; 0x00001268 ***/
#define IEEE_T_CSERR                  (*((volatile uint32 *)(&__IPSBAR[0x00001268UL])))
#define IEEE_T_CSERR_Value0_BITMASK   (0x1U)
#define IEEE_T_CSERR_Value1_BITMASK   (0x2U)
#define IEEE_T_CSERR_Value2_BITMASK   (0x4U)
#define IEEE_T_CSERR_Value3_BITMASK   (0x8U)
#define IEEE_T_CSERR_Value4_BITMASK   (0x10U)
#define IEEE_T_CSERR_Value5_BITMASK   (0x20U)
#define IEEE_T_CSERR_Value6_BITMASK   (0x40U)
#define IEEE_T_CSERR_Value7_BITMASK   (0x80U)
#define IEEE_T_CSERR_Value8_BITMASK   (0x100U)
#define IEEE_T_CSERR_Value9_BITMASK   (0x200U)
#define IEEE_T_CSERR_Value10_BITMASK  (0x400U)
#define IEEE_T_CSERR_Value11_BITMASK  (0x800U)
#define IEEE_T_CSERR_Value12_BITMASK  (0x1000U)
#define IEEE_T_CSERR_Value13_BITMASK  (0x2000U)
#define IEEE_T_CSERR_Value14_BITMASK  (0x4000U)
#define IEEE_T_CSERR_Value15_BITMASK  (0x8000U)
#define IEEE_T_CSERR_Value16_BITMASK  (0x10000U)
#define IEEE_T_CSERR_Value17_BITMASK  (0x20000U)
#define IEEE_T_CSERR_Value18_BITMASK  (0x40000U)
#define IEEE_T_CSERR_Value19_BITMASK  (0x80000U)
#define IEEE_T_CSERR_Value20_BITMASK  (0x100000U)
#define IEEE_T_CSERR_Value21_BITMASK  (0x200000U)
#define IEEE_T_CSERR_Value22_BITMASK  (0x400000U)
#define IEEE_T_CSERR_Value23_BITMASK  (0x800000U)
#define IEEE_T_CSERR_Value24_BITMASK  (0x1000000U)
#define IEEE_T_CSERR_Value25_BITMASK  (0x2000000U)
#define IEEE_T_CSERR_Value26_BITMASK  (0x4000000U)
#define IEEE_T_CSERR_Value27_BITMASK  (0x8000000U)
#define IEEE_T_CSERR_Value28_BITMASK  (0x10000000U)
#define IEEE_T_CSERR_Value29_BITMASK  (0x20000000U)
#define IEEE_T_CSERR_Value30_BITMASK  (0x40000000U)
#define IEEE_T_CSERR_Value31_BITMASK  (0x80000000U)
#define IEEE_T_CSERR_Value_GRPMASK    (0xFFFFFFFFU)
#define IEEE_T_CSERR_Value_GRPPOS     (0U)

/*** IEEE_T_SQE - Frames Transmitted with SQE Error.; 0x0000126C ***/
#define IEEE_T_SQE                    (*((volatile uint32 *)(&__IPSBAR[0x0000126CUL])))
#define IEEE_T_SQE_Value0_BITMASK     (0x1U)
#define IEEE_T_SQE_Value1_BITMASK     (0x2U)
#define IEEE_T_SQE_Value2_BITMASK     (0x4U)
#define IEEE_T_SQE_Value3_BITMASK     (0x8U)
#define IEEE_T_SQE_Value4_BITMASK     (0x10U)
#define IEEE_T_SQE_Value5_BITMASK     (0x20U)
#define IEEE_T_SQE_Value6_BITMASK     (0x40U)
#define IEEE_T_SQE_Value7_BITMASK     (0x80U)
#define IEEE_T_SQE_Value8_BITMASK     (0x100U)
#define IEEE_T_SQE_Value9_BITMASK     (0x200U)
#define IEEE_T_SQE_Value10_BITMASK    (0x400U)
#define IEEE_T_SQE_Value11_BITMASK    (0x800U)
#define IEEE_T_SQE_Value12_BITMASK    (0x1000U)
#define IEEE_T_SQE_Value13_BITMASK    (0x2000U)
#define IEEE_T_SQE_Value14_BITMASK    (0x4000U)
#define IEEE_T_SQE_Value15_BITMASK    (0x8000U)
#define IEEE_T_SQE_Value16_BITMASK    (0x10000U)
#define IEEE_T_SQE_Value17_BITMASK    (0x20000U)
#define IEEE_T_SQE_Value18_BITMASK    (0x40000U)
#define IEEE_T_SQE_Value19_BITMASK    (0x80000U)
#define IEEE_T_SQE_Value20_BITMASK    (0x100000U)
#define IEEE_T_SQE_Value21_BITMASK    (0x200000U)
#define IEEE_T_SQE_Value22_BITMASK    (0x400000U)
#define IEEE_T_SQE_Value23_BITMASK    (0x800000U)
#define IEEE_T_SQE_Value24_BITMASK    (0x1000000U)
#define IEEE_T_SQE_Value25_BITMASK    (0x2000000U)
#define IEEE_T_SQE_Value26_BITMASK    (0x4000000U)
#define IEEE_T_SQE_Value27_BITMASK    (0x8000000U)
#define IEEE_T_SQE_Value28_BITMASK    (0x10000000U)
#define IEEE_T_SQE_Value29_BITMASK    (0x20000000U)
#define IEEE_T_SQE_Value30_BITMASK    (0x40000000U)
#define IEEE_T_SQE_Value31_BITMASK    (0x80000000U)
#define IEEE_T_SQE_Value_GRPMASK      (0xFFFFFFFFU)
#define IEEE_T_SQE_Value_GRPPOS       (0U)

/*** IEEE_T_FDXFC - Flow Control Pause frames transmitted.; 0x00001270 ***/
#define IEEE_T_FDXFC                  (*((volatile uint32 *)(&__IPSBAR[0x00001270UL])))
#define IEEE_T_FDXFC_Value0_BITMASK   (0x1U)
#define IEEE_T_FDXFC_Value1_BITMASK   (0x2U)
#define IEEE_T_FDXFC_Value2_BITMASK   (0x4U)
#define IEEE_T_FDXFC_Value3_BITMASK   (0x8U)
#define IEEE_T_FDXFC_Value4_BITMASK   (0x10U)
#define IEEE_T_FDXFC_Value5_BITMASK   (0x20U)
#define IEEE_T_FDXFC_Value6_BITMASK   (0x40U)
#define IEEE_T_FDXFC_Value7_BITMASK   (0x80U)
#define IEEE_T_FDXFC_Value8_BITMASK   (0x100U)
#define IEEE_T_FDXFC_Value9_BITMASK   (0x200U)
#define IEEE_T_FDXFC_Value10_BITMASK  (0x400U)
#define IEEE_T_FDXFC_Value11_BITMASK  (0x800U)
#define IEEE_T_FDXFC_Value12_BITMASK  (0x1000U)
#define IEEE_T_FDXFC_Value13_BITMASK  (0x2000U)
#define IEEE_T_FDXFC_Value14_BITMASK  (0x4000U)
#define IEEE_T_FDXFC_Value15_BITMASK  (0x8000U)
#define IEEE_T_FDXFC_Value16_BITMASK  (0x10000U)
#define IEEE_T_FDXFC_Value17_BITMASK  (0x20000U)
#define IEEE_T_FDXFC_Value18_BITMASK  (0x40000U)
#define IEEE_T_FDXFC_Value19_BITMASK  (0x80000U)
#define IEEE_T_FDXFC_Value20_BITMASK  (0x100000U)
#define IEEE_T_FDXFC_Value21_BITMASK  (0x200000U)
#define IEEE_T_FDXFC_Value22_BITMASK  (0x400000U)
#define IEEE_T_FDXFC_Value23_BITMASK  (0x800000U)
#define IEEE_T_FDXFC_Value24_BITMASK  (0x1000000U)
#define IEEE_T_FDXFC_Value25_BITMASK  (0x2000000U)
#define IEEE_T_FDXFC_Value26_BITMASK  (0x4000000U)
#define IEEE_T_FDXFC_Value27_BITMASK  (0x8000000U)
#define IEEE_T_FDXFC_Value28_BITMASK  (0x10000000U)
#define IEEE_T_FDXFC_Value29_BITMASK  (0x20000000U)
#define IEEE_T_FDXFC_Value30_BITMASK  (0x40000000U)
#define IEEE_T_FDXFC_Value31_BITMASK  (0x80000000U)
#define IEEE_T_FDXFC_Value_GRPMASK    (0xFFFFFFFFU)
#define IEEE_T_FDXFC_Value_GRPPOS     (0U)

/*** IEEE_T_OCTETS_OK - Octet count for Frames Transmitted w/o Error.; 0x00001274 ***/
#define IEEE_T_OCTETS_OK              (*((volatile uint32 *)(&__IPSBAR[0x00001274UL])))
#define IEEE_T_OCTETS_OK_Value0_BITMASK (0x1U)
#define IEEE_T_OCTETS_OK_Value1_BITMASK (0x2U)
#define IEEE_T_OCTETS_OK_Value2_BITMASK (0x4U)
#define IEEE_T_OCTETS_OK_Value3_BITMASK (0x8U)
#define IEEE_T_OCTETS_OK_Value4_BITMASK (0x10U)
#define IEEE_T_OCTETS_OK_Value5_BITMASK (0x20U)
#define IEEE_T_OCTETS_OK_Value6_BITMASK (0x40U)
#define IEEE_T_OCTETS_OK_Value7_BITMASK (0x80U)
#define IEEE_T_OCTETS_OK_Value8_BITMASK (0x100U)
#define IEEE_T_OCTETS_OK_Value9_BITMASK (0x200U)
#define IEEE_T_OCTETS_OK_Value10_BITMASK (0x400U)
#define IEEE_T_OCTETS_OK_Value11_BITMASK (0x800U)
#define IEEE_T_OCTETS_OK_Value12_BITMASK (0x1000U)
#define IEEE_T_OCTETS_OK_Value13_BITMASK (0x2000U)
#define IEEE_T_OCTETS_OK_Value14_BITMASK (0x4000U)
#define IEEE_T_OCTETS_OK_Value15_BITMASK (0x8000U)
#define IEEE_T_OCTETS_OK_Value16_BITMASK (0x10000U)
#define IEEE_T_OCTETS_OK_Value17_BITMASK (0x20000U)
#define IEEE_T_OCTETS_OK_Value18_BITMASK (0x40000U)
#define IEEE_T_OCTETS_OK_Value19_BITMASK (0x80000U)
#define IEEE_T_OCTETS_OK_Value20_BITMASK (0x100000U)
#define IEEE_T_OCTETS_OK_Value21_BITMASK (0x200000U)
#define IEEE_T_OCTETS_OK_Value22_BITMASK (0x400000U)
#define IEEE_T_OCTETS_OK_Value23_BITMASK (0x800000U)
#define IEEE_T_OCTETS_OK_Value24_BITMASK (0x1000000U)
#define IEEE_T_OCTETS_OK_Value25_BITMASK (0x2000000U)
#define IEEE_T_OCTETS_OK_Value26_BITMASK (0x4000000U)
#define IEEE_T_OCTETS_OK_Value27_BITMASK (0x8000000U)
#define IEEE_T_OCTETS_OK_Value28_BITMASK (0x10000000U)
#define IEEE_T_OCTETS_OK_Value29_BITMASK (0x20000000U)
#define IEEE_T_OCTETS_OK_Value30_BITMASK (0x40000000U)
#define IEEE_T_OCTETS_OK_Value31_BITMASK (0x80000000U)
#define IEEE_T_OCTETS_OK_Value_GRPMASK (0xFFFFFFFFU)
#define IEEE_T_OCTETS_OK_Value_GRPPOS (0U)

/*** RMON_R_DROP - Count of frames not counted correctly.; 0x00001280 ***/
#define RMON_R_DROP                   (*((volatile uint32 *)(&__IPSBAR[0x00001280UL])))
#define RMON_R_DROP_Value0_BITMASK    (0x1U)
#define RMON_R_DROP_Value1_BITMASK    (0x2U)
#define RMON_R_DROP_Value2_BITMASK    (0x4U)
#define RMON_R_DROP_Value3_BITMASK    (0x8U)
#define RMON_R_DROP_Value4_BITMASK    (0x10U)
#define RMON_R_DROP_Value5_BITMASK    (0x20U)
#define RMON_R_DROP_Value6_BITMASK    (0x40U)
#define RMON_R_DROP_Value7_BITMASK    (0x80U)
#define RMON_R_DROP_Value8_BITMASK    (0x100U)
#define RMON_R_DROP_Value9_BITMASK    (0x200U)
#define RMON_R_DROP_Value10_BITMASK   (0x400U)
#define RMON_R_DROP_Value11_BITMASK   (0x800U)
#define RMON_R_DROP_Value12_BITMASK   (0x1000U)
#define RMON_R_DROP_Value13_BITMASK   (0x2000U)
#define RMON_R_DROP_Value14_BITMASK   (0x4000U)
#define RMON_R_DROP_Value15_BITMASK   (0x8000U)
#define RMON_R_DROP_Value16_BITMASK   (0x10000U)
#define RMON_R_DROP_Value17_BITMASK   (0x20000U)
#define RMON_R_DROP_Value18_BITMASK   (0x40000U)
#define RMON_R_DROP_Value19_BITMASK   (0x80000U)
#define RMON_R_DROP_Value20_BITMASK   (0x100000U)
#define RMON_R_DROP_Value21_BITMASK   (0x200000U)
#define RMON_R_DROP_Value22_BITMASK   (0x400000U)
#define RMON_R_DROP_Value23_BITMASK   (0x800000U)
#define RMON_R_DROP_Value24_BITMASK   (0x1000000U)
#define RMON_R_DROP_Value25_BITMASK   (0x2000000U)
#define RMON_R_DROP_Value26_BITMASK   (0x4000000U)
#define RMON_R_DROP_Value27_BITMASK   (0x8000000U)
#define RMON_R_DROP_Value28_BITMASK   (0x10000000U)
#define RMON_R_DROP_Value29_BITMASK   (0x20000000U)
#define RMON_R_DROP_Value30_BITMASK   (0x40000000U)
#define RMON_R_DROP_Value31_BITMASK   (0x80000000U)
#define RMON_R_DROP_Value_GRPMASK     (0xFFFFFFFFU)
#define RMON_R_DROP_Value_GRPPOS      (0U)

/*** RMON_R_PACKETS - RMON Rx packet count.; 0x00001284 ***/
#define RMON_R_PACKETS                (*((volatile uint32 *)(&__IPSBAR[0x00001284UL])))
#define RMON_R_PACKETS_Value0_BITMASK (0x1U)
#define RMON_R_PACKETS_Value1_BITMASK (0x2U)
#define RMON_R_PACKETS_Value2_BITMASK (0x4U)
#define RMON_R_PACKETS_Value3_BITMASK (0x8U)
#define RMON_R_PACKETS_Value4_BITMASK (0x10U)
#define RMON_R_PACKETS_Value5_BITMASK (0x20U)
#define RMON_R_PACKETS_Value6_BITMASK (0x40U)
#define RMON_R_PACKETS_Value7_BITMASK (0x80U)
#define RMON_R_PACKETS_Value8_BITMASK (0x100U)
#define RMON_R_PACKETS_Value9_BITMASK (0x200U)
#define RMON_R_PACKETS_Value10_BITMASK (0x400U)
#define RMON_R_PACKETS_Value11_BITMASK (0x800U)
#define RMON_R_PACKETS_Value12_BITMASK (0x1000U)
#define RMON_R_PACKETS_Value13_BITMASK (0x2000U)
#define RMON_R_PACKETS_Value14_BITMASK (0x4000U)
#define RMON_R_PACKETS_Value15_BITMASK (0x8000U)
#define RMON_R_PACKETS_Value16_BITMASK (0x10000U)
#define RMON_R_PACKETS_Value17_BITMASK (0x20000U)
#define RMON_R_PACKETS_Value18_BITMASK (0x40000U)
#define RMON_R_PACKETS_Value19_BITMASK (0x80000U)
#define RMON_R_PACKETS_Value20_BITMASK (0x100000U)
#define RMON_R_PACKETS_Value21_BITMASK (0x200000U)
#define RMON_R_PACKETS_Value22_BITMASK (0x400000U)
#define RMON_R_PACKETS_Value23_BITMASK (0x800000U)
#define RMON_R_PACKETS_Value24_BITMASK (0x1000000U)
#define RMON_R_PACKETS_Value25_BITMASK (0x2000000U)
#define RMON_R_PACKETS_Value26_BITMASK (0x4000000U)
#define RMON_R_PACKETS_Value27_BITMASK (0x8000000U)
#define RMON_R_PACKETS_Value28_BITMASK (0x10000000U)
#define RMON_R_PACKETS_Value29_BITMASK (0x20000000U)
#define RMON_R_PACKETS_Value30_BITMASK (0x40000000U)
#define RMON_R_PACKETS_Value31_BITMASK (0x80000000U)
#define RMON_R_PACKETS_Value_GRPMASK  (0xFFFFFFFFU)
#define RMON_R_PACKETS_Value_GRPPOS   (0U)

/*** RMON_R_BC_PKT - RMON Rx Broadcast Packets.; 0x00001288 ***/
#define RMON_R_BC_PKT                 (*((volatile uint32 *)(&__IPSBAR[0x00001288UL])))
#define RMON_R_BC_PKT_Value0_BITMASK  (0x1U)
#define RMON_R_BC_PKT_Value1_BITMASK  (0x2U)
#define RMON_R_BC_PKT_Value2_BITMASK  (0x4U)
#define RMON_R_BC_PKT_Value3_BITMASK  (0x8U)
#define RMON_R_BC_PKT_Value4_BITMASK  (0x10U)
#define RMON_R_BC_PKT_Value5_BITMASK  (0x20U)
#define RMON_R_BC_PKT_Value6_BITMASK  (0x40U)
#define RMON_R_BC_PKT_Value7_BITMASK  (0x80U)
#define RMON_R_BC_PKT_Value8_BITMASK  (0x100U)
#define RMON_R_BC_PKT_Value9_BITMASK  (0x200U)
#define RMON_R_BC_PKT_Value10_BITMASK (0x400U)
#define RMON_R_BC_PKT_Value11_BITMASK (0x800U)
#define RMON_R_BC_PKT_Value12_BITMASK (0x1000U)
#define RMON_R_BC_PKT_Value13_BITMASK (0x2000U)
#define RMON_R_BC_PKT_Value14_BITMASK (0x4000U)
#define RMON_R_BC_PKT_Value15_BITMASK (0x8000U)
#define RMON_R_BC_PKT_Value16_BITMASK (0x10000U)
#define RMON_R_BC_PKT_Value17_BITMASK (0x20000U)
#define RMON_R_BC_PKT_Value18_BITMASK (0x40000U)
#define RMON_R_BC_PKT_Value19_BITMASK (0x80000U)
#define RMON_R_BC_PKT_Value20_BITMASK (0x100000U)
#define RMON_R_BC_PKT_Value21_BITMASK (0x200000U)
#define RMON_R_BC_PKT_Value22_BITMASK (0x400000U)
#define RMON_R_BC_PKT_Value23_BITMASK (0x800000U)
#define RMON_R_BC_PKT_Value24_BITMASK (0x1000000U)
#define RMON_R_BC_PKT_Value25_BITMASK (0x2000000U)
#define RMON_R_BC_PKT_Value26_BITMASK (0x4000000U)
#define RMON_R_BC_PKT_Value27_BITMASK (0x8000000U)
#define RMON_R_BC_PKT_Value28_BITMASK (0x10000000U)
#define RMON_R_BC_PKT_Value29_BITMASK (0x20000000U)
#define RMON_R_BC_PKT_Value30_BITMASK (0x40000000U)
#define RMON_R_BC_PKT_Value31_BITMASK (0x80000000U)
#define RMON_R_BC_PKT_Value_GRPMASK   (0xFFFFFFFFU)
#define RMON_R_BC_PKT_Value_GRPPOS    (0U)

/*** RMON_R_MC_PKT - RMON Rx Multicast Packets.; 0x0000128C ***/
#define RMON_R_MC_PKT                 (*((volatile uint32 *)(&__IPSBAR[0x0000128CUL])))
#define RMON_R_MC_PKT_Value0_BITMASK  (0x1U)
#define RMON_R_MC_PKT_Value1_BITMASK  (0x2U)
#define RMON_R_MC_PKT_Value2_BITMASK  (0x4U)
#define RMON_R_MC_PKT_Value3_BITMASK  (0x8U)
#define RMON_R_MC_PKT_Value4_BITMASK  (0x10U)
#define RMON_R_MC_PKT_Value5_BITMASK  (0x20U)
#define RMON_R_MC_PKT_Value6_BITMASK  (0x40U)
#define RMON_R_MC_PKT_Value7_BITMASK  (0x80U)
#define RMON_R_MC_PKT_Value8_BITMASK  (0x100U)
#define RMON_R_MC_PKT_Value9_BITMASK  (0x200U)
#define RMON_R_MC_PKT_Value10_BITMASK (0x400U)
#define RMON_R_MC_PKT_Value11_BITMASK (0x800U)
#define RMON_R_MC_PKT_Value12_BITMASK (0x1000U)
#define RMON_R_MC_PKT_Value13_BITMASK (0x2000U)
#define RMON_R_MC_PKT_Value14_BITMASK (0x4000U)
#define RMON_R_MC_PKT_Value15_BITMASK (0x8000U)
#define RMON_R_MC_PKT_Value16_BITMASK (0x10000U)
#define RMON_R_MC_PKT_Value17_BITMASK (0x20000U)
#define RMON_R_MC_PKT_Value18_BITMASK (0x40000U)
#define RMON_R_MC_PKT_Value19_BITMASK (0x80000U)
#define RMON_R_MC_PKT_Value20_BITMASK (0x100000U)
#define RMON_R_MC_PKT_Value21_BITMASK (0x200000U)
#define RMON_R_MC_PKT_Value22_BITMASK (0x400000U)
#define RMON_R_MC_PKT_Value23_BITMASK (0x800000U)
#define RMON_R_MC_PKT_Value24_BITMASK (0x1000000U)
#define RMON_R_MC_PKT_Value25_BITMASK (0x2000000U)
#define RMON_R_MC_PKT_Value26_BITMASK (0x4000000U)
#define RMON_R_MC_PKT_Value27_BITMASK (0x8000000U)
#define RMON_R_MC_PKT_Value28_BITMASK (0x10000000U)
#define RMON_R_MC_PKT_Value29_BITMASK (0x20000000U)
#define RMON_R_MC_PKT_Value30_BITMASK (0x40000000U)
#define RMON_R_MC_PKT_Value31_BITMASK (0x80000000U)
#define RMON_R_MC_PKT_Value_GRPMASK   (0xFFFFFFFFU)
#define RMON_R_MC_PKT_Value_GRPPOS    (0U)

/*** RMON_R_CRC_ALIGN - RMON Rx Packets w CRC/Align error.; 0x00001290 ***/
#define RMON_R_CRC_ALIGN              (*((volatile uint32 *)(&__IPSBAR[0x00001290UL])))
#define RMON_R_CRC_ALIGN_Value0_BITMASK (0x1U)
#define RMON_R_CRC_ALIGN_Value1_BITMASK (0x2U)
#define RMON_R_CRC_ALIGN_Value2_BITMASK (0x4U)
#define RMON_R_CRC_ALIGN_Value3_BITMASK (0x8U)
#define RMON_R_CRC_ALIGN_Value4_BITMASK (0x10U)
#define RMON_R_CRC_ALIGN_Value5_BITMASK (0x20U)
#define RMON_R_CRC_ALIGN_Value6_BITMASK (0x40U)
#define RMON_R_CRC_ALIGN_Value7_BITMASK (0x80U)
#define RMON_R_CRC_ALIGN_Value8_BITMASK (0x100U)
#define RMON_R_CRC_ALIGN_Value9_BITMASK (0x200U)
#define RMON_R_CRC_ALIGN_Value10_BITMASK (0x400U)
#define RMON_R_CRC_ALIGN_Value11_BITMASK (0x800U)
#define RMON_R_CRC_ALIGN_Value12_BITMASK (0x1000U)
#define RMON_R_CRC_ALIGN_Value13_BITMASK (0x2000U)
#define RMON_R_CRC_ALIGN_Value14_BITMASK (0x4000U)
#define RMON_R_CRC_ALIGN_Value15_BITMASK (0x8000U)
#define RMON_R_CRC_ALIGN_Value16_BITMASK (0x10000U)
#define RMON_R_CRC_ALIGN_Value17_BITMASK (0x20000U)
#define RMON_R_CRC_ALIGN_Value18_BITMASK (0x40000U)
#define RMON_R_CRC_ALIGN_Value19_BITMASK (0x80000U)
#define RMON_R_CRC_ALIGN_Value20_BITMASK (0x100000U)
#define RMON_R_CRC_ALIGN_Value21_BITMASK (0x200000U)
#define RMON_R_CRC_ALIGN_Value22_BITMASK (0x400000U)
#define RMON_R_CRC_ALIGN_Value23_BITMASK (0x800000U)
#define RMON_R_CRC_ALIGN_Value24_BITMASK (0x1000000U)
#define RMON_R_CRC_ALIGN_Value25_BITMASK (0x2000000U)
#define RMON_R_CRC_ALIGN_Value26_BITMASK (0x4000000U)
#define RMON_R_CRC_ALIGN_Value27_BITMASK (0x8000000U)
#define RMON_R_CRC_ALIGN_Value28_BITMASK (0x10000000U)
#define RMON_R_CRC_ALIGN_Value29_BITMASK (0x20000000U)
#define RMON_R_CRC_ALIGN_Value30_BITMASK (0x40000000U)
#define RMON_R_CRC_ALIGN_Value31_BITMASK (0x80000000U)
#define RMON_R_CRC_ALIGN_Value_GRPMASK (0xFFFFFFFFU)
#define RMON_R_CRC_ALIGN_Value_GRPPOS (0U)

/*** RMON_R_UNDERSIZE - RMON Rx Packets < 64 bytes, good crc.; 0x00001294 ***/
#define RMON_R_UNDERSIZE              (*((volatile uint32 *)(&__IPSBAR[0x00001294UL])))
#define RMON_R_UNDERSIZE_Value0_BITMASK (0x1U)
#define RMON_R_UNDERSIZE_Value1_BITMASK (0x2U)
#define RMON_R_UNDERSIZE_Value2_BITMASK (0x4U)
#define RMON_R_UNDERSIZE_Value3_BITMASK (0x8U)
#define RMON_R_UNDERSIZE_Value4_BITMASK (0x10U)
#define RMON_R_UNDERSIZE_Value5_BITMASK (0x20U)
#define RMON_R_UNDERSIZE_Value6_BITMASK (0x40U)
#define RMON_R_UNDERSIZE_Value7_BITMASK (0x80U)
#define RMON_R_UNDERSIZE_Value8_BITMASK (0x100U)
#define RMON_R_UNDERSIZE_Value9_BITMASK (0x200U)
#define RMON_R_UNDERSIZE_Value10_BITMASK (0x400U)
#define RMON_R_UNDERSIZE_Value11_BITMASK (0x800U)
#define RMON_R_UNDERSIZE_Value12_BITMASK (0x1000U)
#define RMON_R_UNDERSIZE_Value13_BITMASK (0x2000U)
#define RMON_R_UNDERSIZE_Value14_BITMASK (0x4000U)
#define RMON_R_UNDERSIZE_Value15_BITMASK (0x8000U)
#define RMON_R_UNDERSIZE_Value16_BITMASK (0x10000U)
#define RMON_R_UNDERSIZE_Value17_BITMASK (0x20000U)
#define RMON_R_UNDERSIZE_Value18_BITMASK (0x40000U)
#define RMON_R_UNDERSIZE_Value19_BITMASK (0x80000U)
#define RMON_R_UNDERSIZE_Value20_BITMASK (0x100000U)
#define RMON_R_UNDERSIZE_Value21_BITMASK (0x200000U)
#define RMON_R_UNDERSIZE_Value22_BITMASK (0x400000U)
#define RMON_R_UNDERSIZE_Value23_BITMASK (0x800000U)
#define RMON_R_UNDERSIZE_Value24_BITMASK (0x1000000U)
#define RMON_R_UNDERSIZE_Value25_BITMASK (0x2000000U)
#define RMON_R_UNDERSIZE_Value26_BITMASK (0x4000000U)
#define RMON_R_UNDERSIZE_Value27_BITMASK (0x8000000U)
#define RMON_R_UNDERSIZE_Value28_BITMASK (0x10000000U)
#define RMON_R_UNDERSIZE_Value29_BITMASK (0x20000000U)
#define RMON_R_UNDERSIZE_Value30_BITMASK (0x40000000U)
#define RMON_R_UNDERSIZE_Value31_BITMASK (0x80000000U)
#define RMON_R_UNDERSIZE_Value_GRPMASK (0xFFFFFFFFU)
#define RMON_R_UNDERSIZE_Value_GRPPOS (0U)

/*** RMON_R_OVERSIZE - RMON Rx Packets > MAX_FL bytes, good crc.; 0x00001298 ***/
#define RMON_R_OVERSIZE               (*((volatile uint32 *)(&__IPSBAR[0x00001298UL])))
#define RMON_R_OVERSIZE_Value0_BITMASK (0x1U)
#define RMON_R_OVERSIZE_Value1_BITMASK (0x2U)
#define RMON_R_OVERSIZE_Value2_BITMASK (0x4U)
#define RMON_R_OVERSIZE_Value3_BITMASK (0x8U)
#define RMON_R_OVERSIZE_Value4_BITMASK (0x10U)
#define RMON_R_OVERSIZE_Value5_BITMASK (0x20U)
#define RMON_R_OVERSIZE_Value6_BITMASK (0x40U)
#define RMON_R_OVERSIZE_Value7_BITMASK (0x80U)
#define RMON_R_OVERSIZE_Value8_BITMASK (0x100U)
#define RMON_R_OVERSIZE_Value9_BITMASK (0x200U)
#define RMON_R_OVERSIZE_Value10_BITMASK (0x400U)
#define RMON_R_OVERSIZE_Value11_BITMASK (0x800U)
#define RMON_R_OVERSIZE_Value12_BITMASK (0x1000U)
#define RMON_R_OVERSIZE_Value13_BITMASK (0x2000U)
#define RMON_R_OVERSIZE_Value14_BITMASK (0x4000U)
#define RMON_R_OVERSIZE_Value15_BITMASK (0x8000U)
#define RMON_R_OVERSIZE_Value16_BITMASK (0x10000U)
#define RMON_R_OVERSIZE_Value17_BITMASK (0x20000U)
#define RMON_R_OVERSIZE_Value18_BITMASK (0x40000U)
#define RMON_R_OVERSIZE_Value19_BITMASK (0x80000U)
#define RMON_R_OVERSIZE_Value20_BITMASK (0x100000U)
#define RMON_R_OVERSIZE_Value21_BITMASK (0x200000U)
#define RMON_R_OVERSIZE_Value22_BITMASK (0x400000U)
#define RMON_R_OVERSIZE_Value23_BITMASK (0x800000U)
#define RMON_R_OVERSIZE_Value24_BITMASK (0x1000000U)
#define RMON_R_OVERSIZE_Value25_BITMASK (0x2000000U)
#define RMON_R_OVERSIZE_Value26_BITMASK (0x4000000U)
#define RMON_R_OVERSIZE_Value27_BITMASK (0x8000000U)
#define RMON_R_OVERSIZE_Value28_BITMASK (0x10000000U)
#define RMON_R_OVERSIZE_Value29_BITMASK (0x20000000U)
#define RMON_R_OVERSIZE_Value30_BITMASK (0x40000000U)
#define RMON_R_OVERSIZE_Value31_BITMASK (0x80000000U)
#define RMON_R_OVERSIZE_Value_GRPMASK (0xFFFFFFFFU)
#define RMON_R_OVERSIZE_Value_GRPPOS  (0U)

/*** RMON_R_FRAG - RMON Rx Packets < 64 bytes, bad crc.; 0x0000129C ***/
#define RMON_R_FRAG                   (*((volatile uint32 *)(&__IPSBAR[0x0000129CUL])))
#define RMON_R_FRAG_Value0_BITMASK    (0x1U)
#define RMON_R_FRAG_Value1_BITMASK    (0x2U)
#define RMON_R_FRAG_Value2_BITMASK    (0x4U)
#define RMON_R_FRAG_Value3_BITMASK    (0x8U)
#define RMON_R_FRAG_Value4_BITMASK    (0x10U)
#define RMON_R_FRAG_Value5_BITMASK    (0x20U)
#define RMON_R_FRAG_Value6_BITMASK    (0x40U)
#define RMON_R_FRAG_Value7_BITMASK    (0x80U)
#define RMON_R_FRAG_Value8_BITMASK    (0x100U)
#define RMON_R_FRAG_Value9_BITMASK    (0x200U)
#define RMON_R_FRAG_Value10_BITMASK   (0x400U)
#define RMON_R_FRAG_Value11_BITMASK   (0x800U)
#define RMON_R_FRAG_Value12_BITMASK   (0x1000U)
#define RMON_R_FRAG_Value13_BITMASK   (0x2000U)
#define RMON_R_FRAG_Value14_BITMASK   (0x4000U)
#define RMON_R_FRAG_Value15_BITMASK   (0x8000U)
#define RMON_R_FRAG_Value16_BITMASK   (0x10000U)
#define RMON_R_FRAG_Value17_BITMASK   (0x20000U)
#define RMON_R_FRAG_Value18_BITMASK   (0x40000U)
#define RMON_R_FRAG_Value19_BITMASK   (0x80000U)
#define RMON_R_FRAG_Value20_BITMASK   (0x100000U)
#define RMON_R_FRAG_Value21_BITMASK   (0x200000U)
#define RMON_R_FRAG_Value22_BITMASK   (0x400000U)
#define RMON_R_FRAG_Value23_BITMASK   (0x800000U)
#define RMON_R_FRAG_Value24_BITMASK   (0x1000000U)
#define RMON_R_FRAG_Value25_BITMASK   (0x2000000U)
#define RMON_R_FRAG_Value26_BITMASK   (0x4000000U)
#define RMON_R_FRAG_Value27_BITMASK   (0x8000000U)
#define RMON_R_FRAG_Value28_BITMASK   (0x10000000U)
#define RMON_R_FRAG_Value29_BITMASK   (0x20000000U)
#define RMON_R_FRAG_Value30_BITMASK   (0x40000000U)
#define RMON_R_FRAG_Value31_BITMASK   (0x80000000U)
#define RMON_R_FRAG_Value_GRPMASK     (0xFFFFFFFFU)
#define RMON_R_FRAG_Value_GRPPOS      (0U)

/*** RMON_R_JAB - RMON Rx Packets > MAX_FL bytes, bad crc.; 0x000012A0 ***/
#define RMON_R_JAB                    (*((volatile uint32 *)(&__IPSBAR[0x000012A0UL])))
#define RMON_R_JAB_Value0_BITMASK     (0x1U)
#define RMON_R_JAB_Value1_BITMASK     (0x2U)
#define RMON_R_JAB_Value2_BITMASK     (0x4U)
#define RMON_R_JAB_Value3_BITMASK     (0x8U)
#define RMON_R_JAB_Value4_BITMASK     (0x10U)
#define RMON_R_JAB_Value5_BITMASK     (0x20U)
#define RMON_R_JAB_Value6_BITMASK     (0x40U)
#define RMON_R_JAB_Value7_BITMASK     (0x80U)
#define RMON_R_JAB_Value8_BITMASK     (0x100U)
#define RMON_R_JAB_Value9_BITMASK     (0x200U)
#define RMON_R_JAB_Value10_BITMASK    (0x400U)
#define RMON_R_JAB_Value11_BITMASK    (0x800U)
#define RMON_R_JAB_Value12_BITMASK    (0x1000U)
#define RMON_R_JAB_Value13_BITMASK    (0x2000U)
#define RMON_R_JAB_Value14_BITMASK    (0x4000U)
#define RMON_R_JAB_Value15_BITMASK    (0x8000U)
#define RMON_R_JAB_Value16_BITMASK    (0x10000U)
#define RMON_R_JAB_Value17_BITMASK    (0x20000U)
#define RMON_R_JAB_Value18_BITMASK    (0x40000U)
#define RMON_R_JAB_Value19_BITMASK    (0x80000U)
#define RMON_R_JAB_Value20_BITMASK    (0x100000U)
#define RMON_R_JAB_Value21_BITMASK    (0x200000U)
#define RMON_R_JAB_Value22_BITMASK    (0x400000U)
#define RMON_R_JAB_Value23_BITMASK    (0x800000U)
#define RMON_R_JAB_Value24_BITMASK    (0x1000000U)
#define RMON_R_JAB_Value25_BITMASK    (0x2000000U)
#define RMON_R_JAB_Value26_BITMASK    (0x4000000U)
#define RMON_R_JAB_Value27_BITMASK    (0x8000000U)
#define RMON_R_JAB_Value28_BITMASK    (0x10000000U)
#define RMON_R_JAB_Value29_BITMASK    (0x20000000U)
#define RMON_R_JAB_Value30_BITMASK    (0x40000000U)
#define RMON_R_JAB_Value31_BITMASK    (0x80000000U)
#define RMON_R_JAB_Value_GRPMASK      (0xFFFFFFFFU)
#define RMON_R_JAB_Value_GRPPOS       (0U)

/*** RMON_R_RESVD_0 - Reserved.; 0x000012A4 ***/
#define RMON_R_RESVD_0                (*((volatile uint32 *)(&__IPSBAR[0x000012A4UL])))
#define RMON_R_RESVD_0_Value0_BITMASK (0x1U)
#define RMON_R_RESVD_0_Value1_BITMASK (0x2U)
#define RMON_R_RESVD_0_Value2_BITMASK (0x4U)
#define RMON_R_RESVD_0_Value3_BITMASK (0x8U)
#define RMON_R_RESVD_0_Value4_BITMASK (0x10U)
#define RMON_R_RESVD_0_Value5_BITMASK (0x20U)
#define RMON_R_RESVD_0_Value6_BITMASK (0x40U)
#define RMON_R_RESVD_0_Value7_BITMASK (0x80U)
#define RMON_R_RESVD_0_Value8_BITMASK (0x100U)
#define RMON_R_RESVD_0_Value9_BITMASK (0x200U)
#define RMON_R_RESVD_0_Value10_BITMASK (0x400U)
#define RMON_R_RESVD_0_Value11_BITMASK (0x800U)
#define RMON_R_RESVD_0_Value12_BITMASK (0x1000U)
#define RMON_R_RESVD_0_Value13_BITMASK (0x2000U)
#define RMON_R_RESVD_0_Value14_BITMASK (0x4000U)
#define RMON_R_RESVD_0_Value15_BITMASK (0x8000U)
#define RMON_R_RESVD_0_Value16_BITMASK (0x10000U)
#define RMON_R_RESVD_0_Value17_BITMASK (0x20000U)
#define RMON_R_RESVD_0_Value18_BITMASK (0x40000U)
#define RMON_R_RESVD_0_Value19_BITMASK (0x80000U)
#define RMON_R_RESVD_0_Value20_BITMASK (0x100000U)
#define RMON_R_RESVD_0_Value21_BITMASK (0x200000U)
#define RMON_R_RESVD_0_Value22_BITMASK (0x400000U)
#define RMON_R_RESVD_0_Value23_BITMASK (0x800000U)
#define RMON_R_RESVD_0_Value24_BITMASK (0x1000000U)
#define RMON_R_RESVD_0_Value25_BITMASK (0x2000000U)
#define RMON_R_RESVD_0_Value26_BITMASK (0x4000000U)
#define RMON_R_RESVD_0_Value27_BITMASK (0x8000000U)
#define RMON_R_RESVD_0_Value28_BITMASK (0x10000000U)
#define RMON_R_RESVD_0_Value29_BITMASK (0x20000000U)
#define RMON_R_RESVD_0_Value30_BITMASK (0x40000000U)
#define RMON_R_RESVD_0_Value31_BITMASK (0x80000000U)
#define RMON_R_RESVD_0_Value_GRPMASK  (0xFFFFFFFFU)
#define RMON_R_RESVD_0_Value_GRPPOS   (0U)

/*** RMON_R_P64 - RMON Rx 64 byte packets.; 0x000012A8 ***/
#define RMON_R_P64                    (*((volatile uint32 *)(&__IPSBAR[0x000012A8UL])))
#define RMON_R_P64_Value0_BITMASK     (0x1U)
#define RMON_R_P64_Value1_BITMASK     (0x2U)
#define RMON_R_P64_Value2_BITMASK     (0x4U)
#define RMON_R_P64_Value3_BITMASK     (0x8U)
#define RMON_R_P64_Value4_BITMASK     (0x10U)
#define RMON_R_P64_Value5_BITMASK     (0x20U)
#define RMON_R_P64_Value6_BITMASK     (0x40U)
#define RMON_R_P64_Value7_BITMASK     (0x80U)
#define RMON_R_P64_Value8_BITMASK     (0x100U)
#define RMON_R_P64_Value9_BITMASK     (0x200U)
#define RMON_R_P64_Value10_BITMASK    (0x400U)
#define RMON_R_P64_Value11_BITMASK    (0x800U)
#define RMON_R_P64_Value12_BITMASK    (0x1000U)
#define RMON_R_P64_Value13_BITMASK    (0x2000U)
#define RMON_R_P64_Value14_BITMASK    (0x4000U)
#define RMON_R_P64_Value15_BITMASK    (0x8000U)
#define RMON_R_P64_Value16_BITMASK    (0x10000U)
#define RMON_R_P64_Value17_BITMASK    (0x20000U)
#define RMON_R_P64_Value18_BITMASK    (0x40000U)
#define RMON_R_P64_Value19_BITMASK    (0x80000U)
#define RMON_R_P64_Value20_BITMASK    (0x100000U)
#define RMON_R_P64_Value21_BITMASK    (0x200000U)
#define RMON_R_P64_Value22_BITMASK    (0x400000U)
#define RMON_R_P64_Value23_BITMASK    (0x800000U)
#define RMON_R_P64_Value24_BITMASK    (0x1000000U)
#define RMON_R_P64_Value25_BITMASK    (0x2000000U)
#define RMON_R_P64_Value26_BITMASK    (0x4000000U)
#define RMON_R_P64_Value27_BITMASK    (0x8000000U)
#define RMON_R_P64_Value28_BITMASK    (0x10000000U)
#define RMON_R_P64_Value29_BITMASK    (0x20000000U)
#define RMON_R_P64_Value30_BITMASK    (0x40000000U)
#define RMON_R_P64_Value31_BITMASK    (0x80000000U)
#define RMON_R_P64_Value_GRPMASK      (0xFFFFFFFFU)
#define RMON_R_P64_Value_GRPPOS       (0U)

/*** RMON_R_P65TO127 - RMON Rx 65 to 127 byte packets.; 0x000012AC ***/
#define RMON_R_P65TO127               (*((volatile uint32 *)(&__IPSBAR[0x000012ACUL])))
#define RMON_R_P65TO127_Value0_BITMASK (0x1U)
#define RMON_R_P65TO127_Value1_BITMASK (0x2U)
#define RMON_R_P65TO127_Value2_BITMASK (0x4U)
#define RMON_R_P65TO127_Value3_BITMASK (0x8U)
#define RMON_R_P65TO127_Value4_BITMASK (0x10U)
#define RMON_R_P65TO127_Value5_BITMASK (0x20U)
#define RMON_R_P65TO127_Value6_BITMASK (0x40U)
#define RMON_R_P65TO127_Value7_BITMASK (0x80U)
#define RMON_R_P65TO127_Value8_BITMASK (0x100U)
#define RMON_R_P65TO127_Value9_BITMASK (0x200U)
#define RMON_R_P65TO127_Value10_BITMASK (0x400U)
#define RMON_R_P65TO127_Value11_BITMASK (0x800U)
#define RMON_R_P65TO127_Value12_BITMASK (0x1000U)
#define RMON_R_P65TO127_Value13_BITMASK (0x2000U)
#define RMON_R_P65TO127_Value14_BITMASK (0x4000U)
#define RMON_R_P65TO127_Value15_BITMASK (0x8000U)
#define RMON_R_P65TO127_Value16_BITMASK (0x10000U)
#define RMON_R_P65TO127_Value17_BITMASK (0x20000U)
#define RMON_R_P65TO127_Value18_BITMASK (0x40000U)
#define RMON_R_P65TO127_Value19_BITMASK (0x80000U)
#define RMON_R_P65TO127_Value20_BITMASK (0x100000U)
#define RMON_R_P65TO127_Value21_BITMASK (0x200000U)
#define RMON_R_P65TO127_Value22_BITMASK (0x400000U)
#define RMON_R_P65TO127_Value23_BITMASK (0x800000U)
#define RMON_R_P65TO127_Value24_BITMASK (0x1000000U)
#define RMON_R_P65TO127_Value25_BITMASK (0x2000000U)
#define RMON_R_P65TO127_Value26_BITMASK (0x4000000U)
#define RMON_R_P65TO127_Value27_BITMASK (0x8000000U)
#define RMON_R_P65TO127_Value28_BITMASK (0x10000000U)
#define RMON_R_P65TO127_Value29_BITMASK (0x20000000U)
#define RMON_R_P65TO127_Value30_BITMASK (0x40000000U)
#define RMON_R_P65TO127_Value31_BITMASK (0x80000000U)
#define RMON_R_P65TO127_Value_GRPMASK (0xFFFFFFFFU)
#define RMON_R_P65TO127_Value_GRPPOS  (0U)

/*** RMON_R_P128TO255 - RMON Rx 128 to 255 byte packets.; 0x000012B0 ***/
#define RMON_R_P128TO255              (*((volatile uint32 *)(&__IPSBAR[0x000012B0UL])))
#define RMON_R_P128TO255_Value0_BITMASK (0x1U)
#define RMON_R_P128TO255_Value1_BITMASK (0x2U)
#define RMON_R_P128TO255_Value2_BITMASK (0x4U)
#define RMON_R_P128TO255_Value3_BITMASK (0x8U)
#define RMON_R_P128TO255_Value4_BITMASK (0x10U)
#define RMON_R_P128TO255_Value5_BITMASK (0x20U)
#define RMON_R_P128TO255_Value6_BITMASK (0x40U)
#define RMON_R_P128TO255_Value7_BITMASK (0x80U)
#define RMON_R_P128TO255_Value8_BITMASK (0x100U)
#define RMON_R_P128TO255_Value9_BITMASK (0x200U)
#define RMON_R_P128TO255_Value10_BITMASK (0x400U)
#define RMON_R_P128TO255_Value11_BITMASK (0x800U)
#define RMON_R_P128TO255_Value12_BITMASK (0x1000U)
#define RMON_R_P128TO255_Value13_BITMASK (0x2000U)
#define RMON_R_P128TO255_Value14_BITMASK (0x4000U)
#define RMON_R_P128TO255_Value15_BITMASK (0x8000U)
#define RMON_R_P128TO255_Value16_BITMASK (0x10000U)
#define RMON_R_P128TO255_Value17_BITMASK (0x20000U)
#define RMON_R_P128TO255_Value18_BITMASK (0x40000U)
#define RMON_R_P128TO255_Value19_BITMASK (0x80000U)
#define RMON_R_P128TO255_Value20_BITMASK (0x100000U)
#define RMON_R_P128TO255_Value21_BITMASK (0x200000U)
#define RMON_R_P128TO255_Value22_BITMASK (0x400000U)
#define RMON_R_P128TO255_Value23_BITMASK (0x800000U)
#define RMON_R_P128TO255_Value24_BITMASK (0x1000000U)
#define RMON_R_P128TO255_Value25_BITMASK (0x2000000U)
#define RMON_R_P128TO255_Value26_BITMASK (0x4000000U)
#define RMON_R_P128TO255_Value27_BITMASK (0x8000000U)
#define RMON_R_P128TO255_Value28_BITMASK (0x10000000U)
#define RMON_R_P128TO255_Value29_BITMASK (0x20000000U)
#define RMON_R_P128TO255_Value30_BITMASK (0x40000000U)
#define RMON_R_P128TO255_Value31_BITMASK (0x80000000U)
#define RMON_R_P128TO255_Value_GRPMASK (0xFFFFFFFFU)
#define RMON_R_P128TO255_Value_GRPPOS (0U)

/*** RMON_R_P256TO511 - RMON Rx 256 to 511 byte packets.; 0x000012B4 ***/
#define RMON_R_P256TO511              (*((volatile uint32 *)(&__IPSBAR[0x000012B4UL])))
#define RMON_R_P256TO511_Value0_BITMASK (0x1U)
#define RMON_R_P256TO511_Value1_BITMASK (0x2U)
#define RMON_R_P256TO511_Value2_BITMASK (0x4U)
#define RMON_R_P256TO511_Value3_BITMASK (0x8U)
#define RMON_R_P256TO511_Value4_BITMASK (0x10U)
#define RMON_R_P256TO511_Value5_BITMASK (0x20U)
#define RMON_R_P256TO511_Value6_BITMASK (0x40U)
#define RMON_R_P256TO511_Value7_BITMASK (0x80U)
#define RMON_R_P256TO511_Value8_BITMASK (0x100U)
#define RMON_R_P256TO511_Value9_BITMASK (0x200U)
#define RMON_R_P256TO511_Value10_BITMASK (0x400U)
#define RMON_R_P256TO511_Value11_BITMASK (0x800U)
#define RMON_R_P256TO511_Value12_BITMASK (0x1000U)
#define RMON_R_P256TO511_Value13_BITMASK (0x2000U)
#define RMON_R_P256TO511_Value14_BITMASK (0x4000U)
#define RMON_R_P256TO511_Value15_BITMASK (0x8000U)
#define RMON_R_P256TO511_Value16_BITMASK (0x10000U)
#define RMON_R_P256TO511_Value17_BITMASK (0x20000U)
#define RMON_R_P256TO511_Value18_BITMASK (0x40000U)
#define RMON_R_P256TO511_Value19_BITMASK (0x80000U)
#define RMON_R_P256TO511_Value20_BITMASK (0x100000U)
#define RMON_R_P256TO511_Value21_BITMASK (0x200000U)
#define RMON_R_P256TO511_Value22_BITMASK (0x400000U)
#define RMON_R_P256TO511_Value23_BITMASK (0x800000U)
#define RMON_R_P256TO511_Value24_BITMASK (0x1000000U)
#define RMON_R_P256TO511_Value25_BITMASK (0x2000000U)
#define RMON_R_P256TO511_Value26_BITMASK (0x4000000U)
#define RMON_R_P256TO511_Value27_BITMASK (0x8000000U)
#define RMON_R_P256TO511_Value28_BITMASK (0x10000000U)
#define RMON_R_P256TO511_Value29_BITMASK (0x20000000U)
#define RMON_R_P256TO511_Value30_BITMASK (0x40000000U)
#define RMON_R_P256TO511_Value31_BITMASK (0x80000000U)
#define RMON_R_P256TO511_Value_GRPMASK (0xFFFFFFFFU)
#define RMON_R_P256TO511_Value_GRPPOS (0U)

/*** RMON_R_P512TO1023 - RMON Rx 512 to 1023 byte packets.; 0x000012B8 ***/
#define RMON_R_P512TO1023             (*((volatile uint32 *)(&__IPSBAR[0x000012B8UL])))
#define RMON_R_P512TO1023_Value0_BITMASK (0x1U)
#define RMON_R_P512TO1023_Value1_BITMASK (0x2U)
#define RMON_R_P512TO1023_Value2_BITMASK (0x4U)
#define RMON_R_P512TO1023_Value3_BITMASK (0x8U)
#define RMON_R_P512TO1023_Value4_BITMASK (0x10U)
#define RMON_R_P512TO1023_Value5_BITMASK (0x20U)
#define RMON_R_P512TO1023_Value6_BITMASK (0x40U)
#define RMON_R_P512TO1023_Value7_BITMASK (0x80U)
#define RMON_R_P512TO1023_Value8_BITMASK (0x100U)
#define RMON_R_P512TO1023_Value9_BITMASK (0x200U)
#define RMON_R_P512TO1023_Value10_BITMASK (0x400U)
#define RMON_R_P512TO1023_Value11_BITMASK (0x800U)
#define RMON_R_P512TO1023_Value12_BITMASK (0x1000U)
#define RMON_R_P512TO1023_Value13_BITMASK (0x2000U)
#define RMON_R_P512TO1023_Value14_BITMASK (0x4000U)
#define RMON_R_P512TO1023_Value15_BITMASK (0x8000U)
#define RMON_R_P512TO1023_Value16_BITMASK (0x10000U)
#define RMON_R_P512TO1023_Value17_BITMASK (0x20000U)
#define RMON_R_P512TO1023_Value18_BITMASK (0x40000U)
#define RMON_R_P512TO1023_Value19_BITMASK (0x80000U)
#define RMON_R_P512TO1023_Value20_BITMASK (0x100000U)
#define RMON_R_P512TO1023_Value21_BITMASK (0x200000U)
#define RMON_R_P512TO1023_Value22_BITMASK (0x400000U)
#define RMON_R_P512TO1023_Value23_BITMASK (0x800000U)
#define RMON_R_P512TO1023_Value24_BITMASK (0x1000000U)
#define RMON_R_P512TO1023_Value25_BITMASK (0x2000000U)
#define RMON_R_P512TO1023_Value26_BITMASK (0x4000000U)
#define RMON_R_P512TO1023_Value27_BITMASK (0x8000000U)
#define RMON_R_P512TO1023_Value28_BITMASK (0x10000000U)
#define RMON_R_P512TO1023_Value29_BITMASK (0x20000000U)
#define RMON_R_P512TO1023_Value30_BITMASK (0x40000000U)
#define RMON_R_P512TO1023_Value31_BITMASK (0x80000000U)
#define RMON_R_P512TO1023_Value_GRPMASK (0xFFFFFFFFU)
#define RMON_R_P512TO1023_Value_GRPPOS (0U)

/*** RMON_R_P1024TO2047 - RMON Rx 1024 to 2047 byte packets.; 0x000012BC ***/
#define RMON_R_P1024TO2047            (*((volatile uint32 *)(&__IPSBAR[0x000012BCUL])))
#define RMON_R_P1024TO2047_Value0_BITMASK (0x1U)
#define RMON_R_P1024TO2047_Value1_BITMASK (0x2U)
#define RMON_R_P1024TO2047_Value2_BITMASK (0x4U)
#define RMON_R_P1024TO2047_Value3_BITMASK (0x8U)
#define RMON_R_P1024TO2047_Value4_BITMASK (0x10U)
#define RMON_R_P1024TO2047_Value5_BITMASK (0x20U)
#define RMON_R_P1024TO2047_Value6_BITMASK (0x40U)
#define RMON_R_P1024TO2047_Value7_BITMASK (0x80U)
#define RMON_R_P1024TO2047_Value8_BITMASK (0x100U)
#define RMON_R_P1024TO2047_Value9_BITMASK (0x200U)
#define RMON_R_P1024TO2047_Value10_BITMASK (0x400U)
#define RMON_R_P1024TO2047_Value11_BITMASK (0x800U)
#define RMON_R_P1024TO2047_Value12_BITMASK (0x1000U)
#define RMON_R_P1024TO2047_Value13_BITMASK (0x2000U)
#define RMON_R_P1024TO2047_Value14_BITMASK (0x4000U)
#define RMON_R_P1024TO2047_Value15_BITMASK (0x8000U)
#define RMON_R_P1024TO2047_Value16_BITMASK (0x10000U)
#define RMON_R_P1024TO2047_Value17_BITMASK (0x20000U)
#define RMON_R_P1024TO2047_Value18_BITMASK (0x40000U)
#define RMON_R_P1024TO2047_Value19_BITMASK (0x80000U)
#define RMON_R_P1024TO2047_Value20_BITMASK (0x100000U)
#define RMON_R_P1024TO2047_Value21_BITMASK (0x200000U)
#define RMON_R_P1024TO2047_Value22_BITMASK (0x400000U)
#define RMON_R_P1024TO2047_Value23_BITMASK (0x800000U)
#define RMON_R_P1024TO2047_Value24_BITMASK (0x1000000U)
#define RMON_R_P1024TO2047_Value25_BITMASK (0x2000000U)
#define RMON_R_P1024TO2047_Value26_BITMASK (0x4000000U)
#define RMON_R_P1024TO2047_Value27_BITMASK (0x8000000U)
#define RMON_R_P1024TO2047_Value28_BITMASK (0x10000000U)
#define RMON_R_P1024TO2047_Value29_BITMASK (0x20000000U)
#define RMON_R_P1024TO2047_Value30_BITMASK (0x40000000U)
#define RMON_R_P1024TO2047_Value31_BITMASK (0x80000000U)
#define RMON_R_P1024TO2047_Value_GRPMASK (0xFFFFFFFFU)
#define RMON_R_P1024TO2047_Value_GRPPOS (0U)

/*** RMON_R_P_GTE2048 - RMON Rx packets w > 2048 bytes.; 0x000012C0 ***/
#define RMON_R_P_GTE2048              (*((volatile uint32 *)(&__IPSBAR[0x000012C0UL])))
#define RMON_R_P_GTE2048_Value0_BITMASK (0x1U)
#define RMON_R_P_GTE2048_Value1_BITMASK (0x2U)
#define RMON_R_P_GTE2048_Value2_BITMASK (0x4U)
#define RMON_R_P_GTE2048_Value3_BITMASK (0x8U)
#define RMON_R_P_GTE2048_Value4_BITMASK (0x10U)
#define RMON_R_P_GTE2048_Value5_BITMASK (0x20U)
#define RMON_R_P_GTE2048_Value6_BITMASK (0x40U)
#define RMON_R_P_GTE2048_Value7_BITMASK (0x80U)
#define RMON_R_P_GTE2048_Value8_BITMASK (0x100U)
#define RMON_R_P_GTE2048_Value9_BITMASK (0x200U)
#define RMON_R_P_GTE2048_Value10_BITMASK (0x400U)
#define RMON_R_P_GTE2048_Value11_BITMASK (0x800U)
#define RMON_R_P_GTE2048_Value12_BITMASK (0x1000U)
#define RMON_R_P_GTE2048_Value13_BITMASK (0x2000U)
#define RMON_R_P_GTE2048_Value14_BITMASK (0x4000U)
#define RMON_R_P_GTE2048_Value15_BITMASK (0x8000U)
#define RMON_R_P_GTE2048_Value16_BITMASK (0x10000U)
#define RMON_R_P_GTE2048_Value17_BITMASK (0x20000U)
#define RMON_R_P_GTE2048_Value18_BITMASK (0x40000U)
#define RMON_R_P_GTE2048_Value19_BITMASK (0x80000U)
#define RMON_R_P_GTE2048_Value20_BITMASK (0x100000U)
#define RMON_R_P_GTE2048_Value21_BITMASK (0x200000U)
#define RMON_R_P_GTE2048_Value22_BITMASK (0x400000U)
#define RMON_R_P_GTE2048_Value23_BITMASK (0x800000U)
#define RMON_R_P_GTE2048_Value24_BITMASK (0x1000000U)
#define RMON_R_P_GTE2048_Value25_BITMASK (0x2000000U)
#define RMON_R_P_GTE2048_Value26_BITMASK (0x4000000U)
#define RMON_R_P_GTE2048_Value27_BITMASK (0x8000000U)
#define RMON_R_P_GTE2048_Value28_BITMASK (0x10000000U)
#define RMON_R_P_GTE2048_Value29_BITMASK (0x20000000U)
#define RMON_R_P_GTE2048_Value30_BITMASK (0x40000000U)
#define RMON_R_P_GTE2048_Value31_BITMASK (0x80000000U)
#define RMON_R_P_GTE2048_Value_GRPMASK (0xFFFFFFFFU)
#define RMON_R_P_GTE2048_Value_GRPPOS (0U)

/*** RMON_R_OCTETS - RMON Rx Octets.; 0x000012C4 ***/
#define RMON_R_OCTETS                 (*((volatile uint32 *)(&__IPSBAR[0x000012C4UL])))
#define RMON_R_OCTETS_Value0_BITMASK  (0x1U)
#define RMON_R_OCTETS_Value1_BITMASK  (0x2U)
#define RMON_R_OCTETS_Value2_BITMASK  (0x4U)
#define RMON_R_OCTETS_Value3_BITMASK  (0x8U)
#define RMON_R_OCTETS_Value4_BITMASK  (0x10U)
#define RMON_R_OCTETS_Value5_BITMASK  (0x20U)
#define RMON_R_OCTETS_Value6_BITMASK  (0x40U)
#define RMON_R_OCTETS_Value7_BITMASK  (0x80U)
#define RMON_R_OCTETS_Value8_BITMASK  (0x100U)
#define RMON_R_OCTETS_Value9_BITMASK  (0x200U)
#define RMON_R_OCTETS_Value10_BITMASK (0x400U)
#define RMON_R_OCTETS_Value11_BITMASK (0x800U)
#define RMON_R_OCTETS_Value12_BITMASK (0x1000U)
#define RMON_R_OCTETS_Value13_BITMASK (0x2000U)
#define RMON_R_OCTETS_Value14_BITMASK (0x4000U)
#define RMON_R_OCTETS_Value15_BITMASK (0x8000U)
#define RMON_R_OCTETS_Value16_BITMASK (0x10000U)
#define RMON_R_OCTETS_Value17_BITMASK (0x20000U)
#define RMON_R_OCTETS_Value18_BITMASK (0x40000U)
#define RMON_R_OCTETS_Value19_BITMASK (0x80000U)
#define RMON_R_OCTETS_Value20_BITMASK (0x100000U)
#define RMON_R_OCTETS_Value21_BITMASK (0x200000U)
#define RMON_R_OCTETS_Value22_BITMASK (0x400000U)
#define RMON_R_OCTETS_Value23_BITMASK (0x800000U)
#define RMON_R_OCTETS_Value24_BITMASK (0x1000000U)
#define RMON_R_OCTETS_Value25_BITMASK (0x2000000U)
#define RMON_R_OCTETS_Value26_BITMASK (0x4000000U)
#define RMON_R_OCTETS_Value27_BITMASK (0x8000000U)
#define RMON_R_OCTETS_Value28_BITMASK (0x10000000U)
#define RMON_R_OCTETS_Value29_BITMASK (0x20000000U)
#define RMON_R_OCTETS_Value30_BITMASK (0x40000000U)
#define RMON_R_OCTETS_Value31_BITMASK (0x80000000U)
#define RMON_R_OCTETS_Value_GRPMASK   (0xFFFFFFFFU)
#define RMON_R_OCTETS_Value_GRPPOS    (0U)

/*** IEEE_R_DROP - Count of frames not counted correctly.; 0x000012C8 ***/
#define IEEE_R_DROP                   (*((volatile uint32 *)(&__IPSBAR[0x000012C8UL])))
#define IEEE_R_DROP_Value0_BITMASK    (0x1U)
#define IEEE_R_DROP_Value1_BITMASK    (0x2U)
#define IEEE_R_DROP_Value2_BITMASK    (0x4U)
#define IEEE_R_DROP_Value3_BITMASK    (0x8U)
#define IEEE_R_DROP_Value4_BITMASK    (0x10U)
#define IEEE_R_DROP_Value5_BITMASK    (0x20U)
#define IEEE_R_DROP_Value6_BITMASK    (0x40U)
#define IEEE_R_DROP_Value7_BITMASK    (0x80U)
#define IEEE_R_DROP_Value8_BITMASK    (0x100U)
#define IEEE_R_DROP_Value9_BITMASK    (0x200U)
#define IEEE_R_DROP_Value10_BITMASK   (0x400U)
#define IEEE_R_DROP_Value11_BITMASK   (0x800U)
#define IEEE_R_DROP_Value12_BITMASK   (0x1000U)
#define IEEE_R_DROP_Value13_BITMASK   (0x2000U)
#define IEEE_R_DROP_Value14_BITMASK   (0x4000U)
#define IEEE_R_DROP_Value15_BITMASK   (0x8000U)
#define IEEE_R_DROP_Value16_BITMASK   (0x10000U)
#define IEEE_R_DROP_Value17_BITMASK   (0x20000U)
#define IEEE_R_DROP_Value18_BITMASK   (0x40000U)
#define IEEE_R_DROP_Value19_BITMASK   (0x80000U)
#define IEEE_R_DROP_Value20_BITMASK   (0x100000U)
#define IEEE_R_DROP_Value21_BITMASK   (0x200000U)
#define IEEE_R_DROP_Value22_BITMASK   (0x400000U)
#define IEEE_R_DROP_Value23_BITMASK   (0x800000U)
#define IEEE_R_DROP_Value24_BITMASK   (0x1000000U)
#define IEEE_R_DROP_Value25_BITMASK   (0x2000000U)
#define IEEE_R_DROP_Value26_BITMASK   (0x4000000U)
#define IEEE_R_DROP_Value27_BITMASK   (0x8000000U)
#define IEEE_R_DROP_Value28_BITMASK   (0x10000000U)
#define IEEE_R_DROP_Value29_BITMASK   (0x20000000U)
#define IEEE_R_DROP_Value30_BITMASK   (0x40000000U)
#define IEEE_R_DROP_Value31_BITMASK   (0x80000000U)
#define IEEE_R_DROP_Value_GRPMASK     (0xFFFFFFFFU)
#define IEEE_R_DROP_Value_GRPPOS      (0U)

/*** IEEE_R_FRAME_OK - Frames Received OK.; 0x000012CC ***/
#define IEEE_R_FRAME_OK               (*((volatile uint32 *)(&__IPSBAR[0x000012CCUL])))
#define IEEE_R_FRAME_OK_Value0_BITMASK (0x1U)
#define IEEE_R_FRAME_OK_Value1_BITMASK (0x2U)
#define IEEE_R_FRAME_OK_Value2_BITMASK (0x4U)
#define IEEE_R_FRAME_OK_Value3_BITMASK (0x8U)
#define IEEE_R_FRAME_OK_Value4_BITMASK (0x10U)
#define IEEE_R_FRAME_OK_Value5_BITMASK (0x20U)
#define IEEE_R_FRAME_OK_Value6_BITMASK (0x40U)
#define IEEE_R_FRAME_OK_Value7_BITMASK (0x80U)
#define IEEE_R_FRAME_OK_Value8_BITMASK (0x100U)
#define IEEE_R_FRAME_OK_Value9_BITMASK (0x200U)
#define IEEE_R_FRAME_OK_Value10_BITMASK (0x400U)
#define IEEE_R_FRAME_OK_Value11_BITMASK (0x800U)
#define IEEE_R_FRAME_OK_Value12_BITMASK (0x1000U)
#define IEEE_R_FRAME_OK_Value13_BITMASK (0x2000U)
#define IEEE_R_FRAME_OK_Value14_BITMASK (0x4000U)
#define IEEE_R_FRAME_OK_Value15_BITMASK (0x8000U)
#define IEEE_R_FRAME_OK_Value16_BITMASK (0x10000U)
#define IEEE_R_FRAME_OK_Value17_BITMASK (0x20000U)
#define IEEE_R_FRAME_OK_Value18_BITMASK (0x40000U)
#define IEEE_R_FRAME_OK_Value19_BITMASK (0x80000U)
#define IEEE_R_FRAME_OK_Value20_BITMASK (0x100000U)
#define IEEE_R_FRAME_OK_Value21_BITMASK (0x200000U)
#define IEEE_R_FRAME_OK_Value22_BITMASK (0x400000U)
#define IEEE_R_FRAME_OK_Value23_BITMASK (0x800000U)
#define IEEE_R_FRAME_OK_Value24_BITMASK (0x1000000U)
#define IEEE_R_FRAME_OK_Value25_BITMASK (0x2000000U)
#define IEEE_R_FRAME_OK_Value26_BITMASK (0x4000000U)
#define IEEE_R_FRAME_OK_Value27_BITMASK (0x8000000U)
#define IEEE_R_FRAME_OK_Value28_BITMASK (0x10000000U)
#define IEEE_R_FRAME_OK_Value29_BITMASK (0x20000000U)
#define IEEE_R_FRAME_OK_Value30_BITMASK (0x40000000U)
#define IEEE_R_FRAME_OK_Value31_BITMASK (0x80000000U)
#define IEEE_R_FRAME_OK_Value_GRPMASK (0xFFFFFFFFU)
#define IEEE_R_FRAME_OK_Value_GRPPOS  (0U)

/*** IEEE_R_CRC - Frames Received with CRC Error.; 0x000012D0 ***/
#define IEEE_R_CRC                    (*((volatile uint32 *)(&__IPSBAR[0x000012D0UL])))
#define IEEE_R_CRC_Value0_BITMASK     (0x1U)
#define IEEE_R_CRC_Value1_BITMASK     (0x2U)
#define IEEE_R_CRC_Value2_BITMASK     (0x4U)
#define IEEE_R_CRC_Value3_BITMASK     (0x8U)
#define IEEE_R_CRC_Value4_BITMASK     (0x10U)
#define IEEE_R_CRC_Value5_BITMASK     (0x20U)
#define IEEE_R_CRC_Value6_BITMASK     (0x40U)
#define IEEE_R_CRC_Value7_BITMASK     (0x80U)
#define IEEE_R_CRC_Value8_BITMASK     (0x100U)
#define IEEE_R_CRC_Value9_BITMASK     (0x200U)
#define IEEE_R_CRC_Value10_BITMASK    (0x400U)
#define IEEE_R_CRC_Value11_BITMASK    (0x800U)
#define IEEE_R_CRC_Value12_BITMASK    (0x1000U)
#define IEEE_R_CRC_Value13_BITMASK    (0x2000U)
#define IEEE_R_CRC_Value14_BITMASK    (0x4000U)
#define IEEE_R_CRC_Value15_BITMASK    (0x8000U)
#define IEEE_R_CRC_Value16_BITMASK    (0x10000U)
#define IEEE_R_CRC_Value17_BITMASK    (0x20000U)
#define IEEE_R_CRC_Value18_BITMASK    (0x40000U)
#define IEEE_R_CRC_Value19_BITMASK    (0x80000U)
#define IEEE_R_CRC_Value20_BITMASK    (0x100000U)
#define IEEE_R_CRC_Value21_BITMASK    (0x200000U)
#define IEEE_R_CRC_Value22_BITMASK    (0x400000U)
#define IEEE_R_CRC_Value23_BITMASK    (0x800000U)
#define IEEE_R_CRC_Value24_BITMASK    (0x1000000U)
#define IEEE_R_CRC_Value25_BITMASK    (0x2000000U)
#define IEEE_R_CRC_Value26_BITMASK    (0x4000000U)
#define IEEE_R_CRC_Value27_BITMASK    (0x8000000U)
#define IEEE_R_CRC_Value28_BITMASK    (0x10000000U)
#define IEEE_R_CRC_Value29_BITMASK    (0x20000000U)
#define IEEE_R_CRC_Value30_BITMASK    (0x40000000U)
#define IEEE_R_CRC_Value31_BITMASK    (0x80000000U)
#define IEEE_R_CRC_Value_GRPMASK      (0xFFFFFFFFU)
#define IEEE_R_CRC_Value_GRPPOS       (0U)

/*** IEEE_R_ALIGN - Frames Received with Alignment Error.; 0x000012D4 ***/
#define IEEE_R_ALIGN                  (*((volatile uint32 *)(&__IPSBAR[0x000012D4UL])))
#define IEEE_R_ALIGN_Value0_BITMASK   (0x1U)
#define IEEE_R_ALIGN_Value1_BITMASK   (0x2U)
#define IEEE_R_ALIGN_Value2_BITMASK   (0x4U)
#define IEEE_R_ALIGN_Value3_BITMASK   (0x8U)
#define IEEE_R_ALIGN_Value4_BITMASK   (0x10U)
#define IEEE_R_ALIGN_Value5_BITMASK   (0x20U)
#define IEEE_R_ALIGN_Value6_BITMASK   (0x40U)
#define IEEE_R_ALIGN_Value7_BITMASK   (0x80U)
#define IEEE_R_ALIGN_Value8_BITMASK   (0x100U)
#define IEEE_R_ALIGN_Value9_BITMASK   (0x200U)
#define IEEE_R_ALIGN_Value10_BITMASK  (0x400U)
#define IEEE_R_ALIGN_Value11_BITMASK  (0x800U)
#define IEEE_R_ALIGN_Value12_BITMASK  (0x1000U)
#define IEEE_R_ALIGN_Value13_BITMASK  (0x2000U)
#define IEEE_R_ALIGN_Value14_BITMASK  (0x4000U)
#define IEEE_R_ALIGN_Value15_BITMASK  (0x8000U)
#define IEEE_R_ALIGN_Value16_BITMASK  (0x10000U)
#define IEEE_R_ALIGN_Value17_BITMASK  (0x20000U)
#define IEEE_R_ALIGN_Value18_BITMASK  (0x40000U)
#define IEEE_R_ALIGN_Value19_BITMASK  (0x80000U)
#define IEEE_R_ALIGN_Value20_BITMASK  (0x100000U)
#define IEEE_R_ALIGN_Value21_BITMASK  (0x200000U)
#define IEEE_R_ALIGN_Value22_BITMASK  (0x400000U)
#define IEEE_R_ALIGN_Value23_BITMASK  (0x800000U)
#define IEEE_R_ALIGN_Value24_BITMASK  (0x1000000U)
#define IEEE_R_ALIGN_Value25_BITMASK  (0x2000000U)
#define IEEE_R_ALIGN_Value26_BITMASK  (0x4000000U)
#define IEEE_R_ALIGN_Value27_BITMASK  (0x8000000U)
#define IEEE_R_ALIGN_Value28_BITMASK  (0x10000000U)
#define IEEE_R_ALIGN_Value29_BITMASK  (0x20000000U)
#define IEEE_R_ALIGN_Value30_BITMASK  (0x40000000U)
#define IEEE_R_ALIGN_Value31_BITMASK  (0x80000000U)
#define IEEE_R_ALIGN_Value_GRPMASK    (0xFFFFFFFFU)
#define IEEE_R_ALIGN_Value_GRPPOS     (0U)

/*** IEEE_R_MACERR - Receive Fifo Overflow count.; 0x000012D8 ***/
#define IEEE_R_MACERR                 (*((volatile uint32 *)(&__IPSBAR[0x000012D8UL])))
#define IEEE_R_MACERR_Value0_BITMASK  (0x1U)
#define IEEE_R_MACERR_Value1_BITMASK  (0x2U)
#define IEEE_R_MACERR_Value2_BITMASK  (0x4U)
#define IEEE_R_MACERR_Value3_BITMASK  (0x8U)
#define IEEE_R_MACERR_Value4_BITMASK  (0x10U)
#define IEEE_R_MACERR_Value5_BITMASK  (0x20U)
#define IEEE_R_MACERR_Value6_BITMASK  (0x40U)
#define IEEE_R_MACERR_Value7_BITMASK  (0x80U)
#define IEEE_R_MACERR_Value8_BITMASK  (0x100U)
#define IEEE_R_MACERR_Value9_BITMASK  (0x200U)
#define IEEE_R_MACERR_Value10_BITMASK (0x400U)
#define IEEE_R_MACERR_Value11_BITMASK (0x800U)
#define IEEE_R_MACERR_Value12_BITMASK (0x1000U)
#define IEEE_R_MACERR_Value13_BITMASK (0x2000U)
#define IEEE_R_MACERR_Value14_BITMASK (0x4000U)
#define IEEE_R_MACERR_Value15_BITMASK (0x8000U)
#define IEEE_R_MACERR_Value16_BITMASK (0x10000U)
#define IEEE_R_MACERR_Value17_BITMASK (0x20000U)
#define IEEE_R_MACERR_Value18_BITMASK (0x40000U)
#define IEEE_R_MACERR_Value19_BITMASK (0x80000U)
#define IEEE_R_MACERR_Value20_BITMASK (0x100000U)
#define IEEE_R_MACERR_Value21_BITMASK (0x200000U)
#define IEEE_R_MACERR_Value22_BITMASK (0x400000U)
#define IEEE_R_MACERR_Value23_BITMASK (0x800000U)
#define IEEE_R_MACERR_Value24_BITMASK (0x1000000U)
#define IEEE_R_MACERR_Value25_BITMASK (0x2000000U)
#define IEEE_R_MACERR_Value26_BITMASK (0x4000000U)
#define IEEE_R_MACERR_Value27_BITMASK (0x8000000U)
#define IEEE_R_MACERR_Value28_BITMASK (0x10000000U)
#define IEEE_R_MACERR_Value29_BITMASK (0x20000000U)
#define IEEE_R_MACERR_Value30_BITMASK (0x40000000U)
#define IEEE_R_MACERR_Value31_BITMASK (0x80000000U)
#define IEEE_R_MACERR_Value_GRPMASK   (0xFFFFFFFFU)
#define IEEE_R_MACERR_Value_GRPPOS    (0U)

/*** IEEE_R_FDXFC - Flow Control Pause frames received.; 0x000012DC ***/
#define IEEE_R_FDXFC                  (*((volatile uint32 *)(&__IPSBAR[0x000012DCUL])))
#define IEEE_R_FDXFC_Value0_BITMASK   (0x1U)
#define IEEE_R_FDXFC_Value1_BITMASK   (0x2U)
#define IEEE_R_FDXFC_Value2_BITMASK   (0x4U)
#define IEEE_R_FDXFC_Value3_BITMASK   (0x8U)
#define IEEE_R_FDXFC_Value4_BITMASK   (0x10U)
#define IEEE_R_FDXFC_Value5_BITMASK   (0x20U)
#define IEEE_R_FDXFC_Value6_BITMASK   (0x40U)
#define IEEE_R_FDXFC_Value7_BITMASK   (0x80U)
#define IEEE_R_FDXFC_Value8_BITMASK   (0x100U)
#define IEEE_R_FDXFC_Value9_BITMASK   (0x200U)
#define IEEE_R_FDXFC_Value10_BITMASK  (0x400U)
#define IEEE_R_FDXFC_Value11_BITMASK  (0x800U)
#define IEEE_R_FDXFC_Value12_BITMASK  (0x1000U)
#define IEEE_R_FDXFC_Value13_BITMASK  (0x2000U)
#define IEEE_R_FDXFC_Value14_BITMASK  (0x4000U)
#define IEEE_R_FDXFC_Value15_BITMASK  (0x8000U)
#define IEEE_R_FDXFC_Value16_BITMASK  (0x10000U)
#define IEEE_R_FDXFC_Value17_BITMASK  (0x20000U)
#define IEEE_R_FDXFC_Value18_BITMASK  (0x40000U)
#define IEEE_R_FDXFC_Value19_BITMASK  (0x80000U)
#define IEEE_R_FDXFC_Value20_BITMASK  (0x100000U)
#define IEEE_R_FDXFC_Value21_BITMASK  (0x200000U)
#define IEEE_R_FDXFC_Value22_BITMASK  (0x400000U)
#define IEEE_R_FDXFC_Value23_BITMASK  (0x800000U)
#define IEEE_R_FDXFC_Value24_BITMASK  (0x1000000U)
#define IEEE_R_FDXFC_Value25_BITMASK  (0x2000000U)
#define IEEE_R_FDXFC_Value26_BITMASK  (0x4000000U)
#define IEEE_R_FDXFC_Value27_BITMASK  (0x8000000U)
#define IEEE_R_FDXFC_Value28_BITMASK  (0x10000000U)
#define IEEE_R_FDXFC_Value29_BITMASK  (0x20000000U)
#define IEEE_R_FDXFC_Value30_BITMASK  (0x40000000U)
#define IEEE_R_FDXFC_Value31_BITMASK  (0x80000000U)
#define IEEE_R_FDXFC_Value_GRPMASK    (0xFFFFFFFFU)
#define IEEE_R_FDXFC_Value_GRPPOS     (0U)

/*** IEEE_R_OCTETS_OK - Octet count for Frames Rcvd w/o Error.; 0x000012E0 ***/
#define IEEE_R_OCTETS_OK              (*((volatile uint32 *)(&__IPSBAR[0x000012E0UL])))
#define IEEE_R_OCTETS_OK_Value0_BITMASK (0x1U)
#define IEEE_R_OCTETS_OK_Value1_BITMASK (0x2U)
#define IEEE_R_OCTETS_OK_Value2_BITMASK (0x4U)
#define IEEE_R_OCTETS_OK_Value3_BITMASK (0x8U)
#define IEEE_R_OCTETS_OK_Value4_BITMASK (0x10U)
#define IEEE_R_OCTETS_OK_Value5_BITMASK (0x20U)
#define IEEE_R_OCTETS_OK_Value6_BITMASK (0x40U)
#define IEEE_R_OCTETS_OK_Value7_BITMASK (0x80U)
#define IEEE_R_OCTETS_OK_Value8_BITMASK (0x100U)
#define IEEE_R_OCTETS_OK_Value9_BITMASK (0x200U)
#define IEEE_R_OCTETS_OK_Value10_BITMASK (0x400U)
#define IEEE_R_OCTETS_OK_Value11_BITMASK (0x800U)
#define IEEE_R_OCTETS_OK_Value12_BITMASK (0x1000U)
#define IEEE_R_OCTETS_OK_Value13_BITMASK (0x2000U)
#define IEEE_R_OCTETS_OK_Value14_BITMASK (0x4000U)
#define IEEE_R_OCTETS_OK_Value15_BITMASK (0x8000U)
#define IEEE_R_OCTETS_OK_Value16_BITMASK (0x10000U)
#define IEEE_R_OCTETS_OK_Value17_BITMASK (0x20000U)
#define IEEE_R_OCTETS_OK_Value18_BITMASK (0x40000U)
#define IEEE_R_OCTETS_OK_Value19_BITMASK (0x80000U)
#define IEEE_R_OCTETS_OK_Value20_BITMASK (0x100000U)
#define IEEE_R_OCTETS_OK_Value21_BITMASK (0x200000U)
#define IEEE_R_OCTETS_OK_Value22_BITMASK (0x400000U)
#define IEEE_R_OCTETS_OK_Value23_BITMASK (0x800000U)
#define IEEE_R_OCTETS_OK_Value24_BITMASK (0x1000000U)
#define IEEE_R_OCTETS_OK_Value25_BITMASK (0x2000000U)
#define IEEE_R_OCTETS_OK_Value26_BITMASK (0x4000000U)
#define IEEE_R_OCTETS_OK_Value27_BITMASK (0x8000000U)
#define IEEE_R_OCTETS_OK_Value28_BITMASK (0x10000000U)
#define IEEE_R_OCTETS_OK_Value29_BITMASK (0x20000000U)
#define IEEE_R_OCTETS_OK_Value30_BITMASK (0x40000000U)
#define IEEE_R_OCTETS_OK_Value31_BITMASK (0x80000000U)
#define IEEE_R_OCTETS_OK_Value_GRPMASK (0xFFFFFFFFU)
#define IEEE_R_OCTETS_OK_Value_GRPPOS (0U)


/******************************************
*** Peripheral PORTNQ
*******************************************/

/*** PORTNQ - Port Output Data Register.; 0x00100008 ***/
#define PORTNQ                        (*((volatile uint8 *)(&__IPSBAR[0x00100008UL])))
#define PORTNQ_PORTNQ1_BITMASK        (0x2U)
#define PORTNQ_PORTNQ2_BITMASK        (0x4U)
#define PORTNQ_PORTNQ3_BITMASK        (0x8U)
#define PORTNQ_PORTNQ4_BITMASK        (0x10U)
#define PORTNQ_PORTNQ5_BITMASK        (0x20U)
#define PORTNQ_PORTNQ6_BITMASK        (0x40U)
#define PORTNQ_PORTNQ7_BITMASK        (0x80U)

/*** DDRNQ - Port Data Direction Register.; 0x00100020 ***/
#define DDRNQ                         (*((volatile uint8 *)(&__IPSBAR[0x00100020UL])))
#define DDRNQ_DDRNQ1_BITMASK          (0x2U)
#define DDRNQ_DDRNQ2_BITMASK          (0x4U)
#define DDRNQ_DDRNQ3_BITMASK          (0x8U)
#define DDRNQ_DDRNQ4_BITMASK          (0x10U)
#define DDRNQ_DDRNQ5_BITMASK          (0x20U)
#define DDRNQ_DDRNQ6_BITMASK          (0x40U)
#define DDRNQ_DDRNQ7_BITMASK          (0x80U)

/*** SETNQ - Port Pin Data/Set Data Register.; 0x00100038 ***/
#define SETNQ                         (*((volatile uint8 *)(&__IPSBAR[0x00100038UL])))
#define SETNQ_SETNQ1_BITMASK          (0x2U)
#define SETNQ_SETNQ2_BITMASK          (0x4U)
#define SETNQ_SETNQ3_BITMASK          (0x8U)
#define SETNQ_SETNQ4_BITMASK          (0x10U)
#define SETNQ_SETNQ5_BITMASK          (0x20U)
#define SETNQ_SETNQ6_BITMASK          (0x40U)
#define SETNQ_SETNQ7_BITMASK          (0x80U)

/*** CLRNQ - Port Clear Output Data Register.; 0x00100050 ***/
#define CLRNQ                         (*((volatile uint8 *)(&__IPSBAR[0x00100050UL])))
#define CLRNQ_CLRNQ1_BITMASK          (0x2U)
#define CLRNQ_CLRNQ2_BITMASK          (0x4U)
#define CLRNQ_CLRNQ3_BITMASK          (0x8U)
#define CLRNQ_CLRNQ4_BITMASK          (0x10U)
#define CLRNQ_CLRNQ5_BITMASK          (0x20U)
#define CLRNQ_CLRNQ6_BITMASK          (0x40U)
#define CLRNQ_CLRNQ7_BITMASK          (0x80U)

/*** PNQPAR - Quad Function Pin Assignment Register.; 0x00100068 ***/
#define PNQPAR                        (*((volatile uint16 *)(&__IPSBAR[0x00100068UL])))
#define PNQPAR_PNQPAR10_BITMASK       (0x4U)
#define PNQPAR_PNQPAR11_BITMASK       (0x8U)
#define PNQPAR_PNQPAR20_BITMASK       (0x10U)
#define PNQPAR_PNQPAR21_BITMASK       (0x20U)
#define PNQPAR_PNQPAR30_BITMASK       (0x40U)
#define PNQPAR_PNQPAR31_BITMASK       (0x80U)
#define PNQPAR_PNQPAR40_BITMASK       (0x100U)
#define PNQPAR_PNQPAR41_BITMASK       (0x200U)
#define PNQPAR_PNQPAR50_BITMASK       (0x400U)
#define PNQPAR_PNQPAR51_BITMASK       (0x800U)
#define PNQPAR_PNQPAR60_BITMASK       (0x1000U)
#define PNQPAR_PNQPAR61_BITMASK       (0x2000U)
#define PNQPAR_PNQPAR70_BITMASK       (0x4000U)
#define PNQPAR_PNQPAR71_BITMASK       (0x8000U)
#define PNQPAR_PNQPAR1_GRPMASK        (0xCU)
#define PNQPAR_PNQPAR1_GRPPOS         (0x2U)
#define PNQPAR_PNQPAR2_GRPMASK        (0x30U)
#define PNQPAR_PNQPAR2_GRPPOS         (0x4U)
#define PNQPAR_PNQPAR3_GRPMASK        (0xC0U)
#define PNQPAR_PNQPAR3_GRPPOS         (0x6U)
#define PNQPAR_PNQPAR4_GRPMASK        (0x300U)
#define PNQPAR_PNQPAR4_GRPPOS         (0x8U)
#define PNQPAR_PNQPAR5_GRPMASK        (0xC00U)
#define PNQPAR_PNQPAR5_GRPPOS         (0xAU)
#define PNQPAR_PNQPAR6_GRPMASK        (0x3000U)
#define PNQPAR_PNQPAR6_GRPPOS         (0xCU)
#define PNQPAR_PNQPAR7_GRPMASK        (0xC000U)
#define PNQPAR_PNQPAR7_GRPPOS         (0xEU)


/******************************************
*** Peripheral PORTAN
*******************************************/

/*** PORTAN - Port Output Data Register.; 0x0010000A ***/
#define PORTAN                        (*((volatile uint8 *)(&__IPSBAR[0x0010000AUL])))
#define PORTAN_PORTAN0_BITMASK        (0x1U)
#define PORTAN_PORTAN1_BITMASK        (0x2U)
#define PORTAN_PORTAN2_BITMASK        (0x4U)
#define PORTAN_PORTAN3_BITMASK        (0x8U)
#define PORTAN_PORTAN4_BITMASK        (0x10U)
#define PORTAN_PORTAN5_BITMASK        (0x20U)
#define PORTAN_PORTAN6_BITMASK        (0x40U)
#define PORTAN_PORTAN7_BITMASK        (0x80U)

/*** DDRAN - Port Data Direction Register.; 0x00100022 ***/
#define DDRAN                         (*((volatile uint8 *)(&__IPSBAR[0x00100022UL])))
#define DDRAN_DDRAN0_BITMASK          (0x1U)
#define DDRAN_DDRAN1_BITMASK          (0x2U)
#define DDRAN_DDRAN2_BITMASK          (0x4U)
#define DDRAN_DDRAN3_BITMASK          (0x8U)
#define DDRAN_DDRAN4_BITMASK          (0x10U)
#define DDRAN_DDRAN5_BITMASK          (0x20U)
#define DDRAN_DDRAN6_BITMASK          (0x40U)
#define DDRAN_DDRAN7_BITMASK          (0x80U)

/*** SETAN - Port Pin Data/Set Data Register.; 0x0010003A ***/
#define SETAN                         (*((volatile uint8 *)(&__IPSBAR[0x0010003AUL])))
#define SETAN_SETAN0_BITMASK          (0x1U)
#define SETAN_SETAN1_BITMASK          (0x2U)
#define SETAN_SETAN2_BITMASK          (0x4U)
#define SETAN_SETAN3_BITMASK          (0x8U)
#define SETAN_SETAN4_BITMASK          (0x10U)
#define SETAN_SETAN5_BITMASK          (0x20U)
#define SETAN_SETAN6_BITMASK          (0x40U)
#define SETAN_SETAN7_BITMASK          (0x80U)

/*** CLRAN - Port Clear Output Data Register.; 0x00100052 ***/
#define CLRAN                         (*((volatile uint8 *)(&__IPSBAR[0x00100052UL])))
#define CLRAN_CLRAN0_BITMASK          (0x1U)
#define CLRAN_CLRAN1_BITMASK          (0x2U)
#define CLRAN_CLRAN2_BITMASK          (0x4U)
#define CLRAN_CLRAN3_BITMASK          (0x8U)
#define CLRAN_CLRAN4_BITMASK          (0x10U)
#define CLRAN_CLRAN5_BITMASK          (0x20U)
#define CLRAN_CLRAN6_BITMASK          (0x40U)
#define CLRAN_CLRAN7_BITMASK          (0x80U)

/*** PANPAR - Dual Function Pin Assignment Register.; 0x0010006A ***/
#define PANPAR                        (*((volatile uint8 *)(&__IPSBAR[0x0010006AUL])))
#define PANPAR_PANPAR0_BITMASK        (0x1U)
#define PANPAR_PANPAR1_BITMASK        (0x2U)
#define PANPAR_PANPAR2_BITMASK        (0x4U)
#define PANPAR_PANPAR3_BITMASK        (0x8U)
#define PANPAR_PANPAR4_BITMASK        (0x10U)
#define PANPAR_PANPAR5_BITMASK        (0x20U)
#define PANPAR_PANPAR6_BITMASK        (0x40U)
#define PANPAR_PANPAR7_BITMASK        (0x80U)


/******************************************
*** Peripheral PORTAS
*******************************************/

/*** PORTAS - Port Output Data Register.; 0x0010000B ***/
#define PORTAS                        (*((volatile uint8 *)(&__IPSBAR[0x0010000BUL])))
#define PORTAS_PORTAS0_BITMASK        (0x1U)
#define PORTAS_PORTAS1_BITMASK        (0x2U)
#define PORTAS_PORTAS2_BITMASK        (0x4U)
#define PORTAS_PORTAS3_BITMASK        (0x8U)

/*** DDRAS - Port Data Direction Register.; 0x00100023 ***/
#define DDRAS                         (*((volatile uint8 *)(&__IPSBAR[0x00100023UL])))
#define DDRAS_DDRAS0_BITMASK          (0x1U)
#define DDRAS_DDRAS1_BITMASK          (0x2U)
#define DDRAS_DDRAS2_BITMASK          (0x4U)
#define DDRAS_DDRAS3_BITMASK          (0x8U)

/*** SETAS - Port Pin Data/Set Data Register.; 0x0010003B ***/
#define SETAS                         (*((volatile uint8 *)(&__IPSBAR[0x0010003BUL])))
#define SETAS_SETAS0_BITMASK          (0x1U)
#define SETAS_SETAS1_BITMASK          (0x2U)
#define SETAS_SETAS2_BITMASK          (0x4U)
#define SETAS_SETAS3_BITMASK          (0x8U)

/*** CLRAS - Port Clear Output Data Register.; 0x00100053 ***/
#define CLRAS                         (*((volatile uint8 *)(&__IPSBAR[0x00100053UL])))
#define CLRAS_CLRAS0_BITMASK          (0x1U)
#define CLRAS_CLRAS1_BITMASK          (0x2U)
#define CLRAS_CLRAS2_BITMASK          (0x4U)
#define CLRAS_CLRAS3_BITMASK          (0x8U)

/*** PASPAR - Quad Function Pin Assignment Register.; 0x0010006B ***/
#define PASPAR                        (*((volatile uint8 *)(&__IPSBAR[0x0010006BUL])))
#define PASPAR_PASPAR00_BITMASK       (0x1U)
#define PASPAR_PASPAR01_BITMASK       (0x2U)
#define PASPAR_PASPAR10_BITMASK       (0x4U)
#define PASPAR_PASPAR11_BITMASK       (0x8U)
#define PASPAR_PASPAR20_BITMASK       (0x10U)
#define PASPAR_PASPAR21_BITMASK       (0x20U)
#define PASPAR_PASPAR30_BITMASK       (0x40U)
#define PASPAR_PASPAR31_BITMASK       (0x80U)
#define PASPAR_PASPAR0_GRPMASK        (0x3U)
#define PASPAR_PASPAR0_GRPPOS         (0U)
#define PASPAR_PASPAR1_GRPMASK        (0xCU)
#define PASPAR_PASPAR1_GRPPOS         (0x2U)
#define PASPAR_PASPAR2_GRPMASK        (0x30U)
#define PASPAR_PASPAR2_GRPPOS         (0x4U)
#define PASPAR_PASPAR3_GRPMASK        (0xC0U)
#define PASPAR_PASPAR3_GRPPOS         (0x6U)


/******************************************
*** Peripheral PORTQS
*******************************************/

/*** PORTQS - Port Output Data Register.; 0x0010000C ***/
#define PORTQS                        (*((volatile uint8 *)(&__IPSBAR[0x0010000CUL])))
#define PORTQS_PORTQS0_BITMASK        (0x1U)
#define PORTQS_PORTQS1_BITMASK        (0x2U)
#define PORTQS_PORTQS2_BITMASK        (0x4U)
#define PORTQS_PORTQS3_BITMASK        (0x8U)
#define PORTQS_PORTQS4_BITMASK        (0x10U)
#define PORTQS_PORTQS5_BITMASK        (0x20U)
#define PORTQS_PORTQS6_BITMASK        (0x40U)

/*** DDRQS - Port Data Direction Register.; 0x00100024 ***/
#define DDRQS                         (*((volatile uint8 *)(&__IPSBAR[0x00100024UL])))
#define DDRQS_DDRQS0_BITMASK          (0x1U)
#define DDRQS_DDRQS1_BITMASK          (0x2U)
#define DDRQS_DDRQS2_BITMASK          (0x4U)
#define DDRQS_DDRQS3_BITMASK          (0x8U)
#define DDRQS_DDRQS4_BITMASK          (0x10U)
#define DDRQS_DDRQS5_BITMASK          (0x20U)
#define DDRQS_DDRQS6_BITMASK          (0x40U)

/*** SETQS - Port Pin Data/Set Data Register.; 0x0010003C ***/
#define SETQS                         (*((volatile uint8 *)(&__IPSBAR[0x0010003CUL])))
#define SETQS_SETQS0_BITMASK          (0x1U)
#define SETQS_SETQS1_BITMASK          (0x2U)
#define SETQS_SETQS2_BITMASK          (0x4U)
#define SETQS_SETQS3_BITMASK          (0x8U)
#define SETQS_SETQS4_BITMASK          (0x10U)
#define SETQS_SETQS5_BITMASK          (0x20U)
#define SETQS_SETQS6_BITMASK          (0x40U)

/*** CLRQS - Port Clear Output Data Register.; 0x00100054 ***/
#define CLRQS                         (*((volatile uint8 *)(&__IPSBAR[0x00100054UL])))
#define CLRQS_CLRQS0_BITMASK          (0x1U)
#define CLRQS_CLRQS1_BITMASK          (0x2U)
#define CLRQS_CLRQS2_BITMASK          (0x4U)
#define CLRQS_CLRQS3_BITMASK          (0x8U)
#define CLRQS_CLRQS4_BITMASK          (0x10U)
#define CLRQS_CLRQS5_BITMASK          (0x20U)
#define CLRQS_CLRQS6_BITMASK          (0x40U)

/*** PQSPAR - Quad Function Pin Assignment Register.; 0x0010006C ***/
#define PQSPAR                        (*((volatile uint16 *)(&__IPSBAR[0x0010006CUL])))
#define PQSPAR_PQSPAR00_BITMASK       (0x1U)
#define PQSPAR_PQSPAR01_BITMASK       (0x2U)
#define PQSPAR_PQSPAR10_BITMASK       (0x4U)
#define PQSPAR_PQSPAR11_BITMASK       (0x8U)
#define PQSPAR_PQSPAR20_BITMASK       (0x10U)
#define PQSPAR_PQSPAR21_BITMASK       (0x20U)
#define PQSPAR_PQSPAR30_BITMASK       (0x40U)
#define PQSPAR_PQSPAR31_BITMASK       (0x80U)
#define PQSPAR_PQSPAR40_BITMASK       (0x100U)
#define PQSPAR_PQSPAR41_BITMASK       (0x200U)
#define PQSPAR_PQSPAR50_BITMASK       (0x400U)
#define PQSPAR_PQSPAR51_BITMASK       (0x800U)
#define PQSPAR_PQSPAR60_BITMASK       (0x1000U)
#define PQSPAR_PQSPAR61_BITMASK       (0x2000U)
#define PQSPAR_PQSPAR0_GRPMASK        (0x3U)
#define PQSPAR_PQSPAR0_GRPPOS         (0U)
#define PQSPAR_PQSPAR1_GRPMASK        (0xCU)
#define PQSPAR_PQSPAR1_GRPPOS         (0x2U)
#define PQSPAR_PQSPAR2_GRPMASK        (0x30U)
#define PQSPAR_PQSPAR2_GRPPOS         (0x4U)
#define PQSPAR_PQSPAR3_GRPMASK        (0xC0U)
#define PQSPAR_PQSPAR3_GRPPOS         (0x6U)
#define PQSPAR_PQSPAR4_GRPMASK        (0x300U)
#define PQSPAR_PQSPAR4_GRPPOS         (0x8U)
#define PQSPAR_PQSPAR5_GRPMASK        (0xC00U)
#define PQSPAR_PQSPAR5_GRPPOS         (0xAU)
#define PQSPAR_PQSPAR6_GRPMASK        (0x3000U)
#define PQSPAR_PQSPAR6_GRPPOS         (0xCU)


/******************************************
*** Peripheral PORTTA
*******************************************/

/*** PORTTA - Port Output Data Register.; 0x0010000E ***/
#define PORTTA                        (*((volatile uint8 *)(&__IPSBAR[0x0010000EUL])))
#define PORTTA_PORTTA0_BITMASK        (0x1U)
#define PORTTA_PORTTA1_BITMASK        (0x2U)
#define PORTTA_PORTTA2_BITMASK        (0x4U)
#define PORTTA_PORTTA3_BITMASK        (0x8U)

/*** DDRTA - Port Data Direction Register.; 0x00100026 ***/
#define DDRTA                         (*((volatile uint8 *)(&__IPSBAR[0x00100026UL])))
#define DDRTA_DDRTA0_BITMASK          (0x1U)
#define DDRTA_DDRTA1_BITMASK          (0x2U)
#define DDRTA_DDRTA2_BITMASK          (0x4U)
#define DDRTA_DDRTA3_BITMASK          (0x8U)

/*** SETTA - Port Pin Data/Set Data Register.; 0x0010003E ***/
#define SETTA                         (*((volatile uint8 *)(&__IPSBAR[0x0010003EUL])))
#define SETTA_SETTA0_BITMASK          (0x1U)
#define SETTA_SETTA1_BITMASK          (0x2U)
#define SETTA_SETTA2_BITMASK          (0x4U)
#define SETTA_SETTA3_BITMASK          (0x8U)

/*** CLRTA - Port Clear Output Data Register.; 0x00100056 ***/
#define CLRTA                         (*((volatile uint8 *)(&__IPSBAR[0x00100056UL])))
#define CLRTA_CLRTA0_BITMASK          (0x1U)
#define CLRTA_CLRTA1_BITMASK          (0x2U)
#define CLRTA_CLRTA2_BITMASK          (0x4U)
#define CLRTA_CLRTA3_BITMASK          (0x8U)

/*** PTAPAR - Quad Function Pin Assignment Register.; 0x0010006E ***/
#define PTAPAR                        (*((volatile uint8 *)(&__IPSBAR[0x0010006EUL])))
#define PTAPAR_PTAPAR00_BITMASK       (0x1U)
#define PTAPAR_PTAPAR01_BITMASK       (0x2U)
#define PTAPAR_PTAPAR10_BITMASK       (0x4U)
#define PTAPAR_PTAPAR11_BITMASK       (0x8U)
#define PTAPAR_PTAPAR20_BITMASK       (0x10U)
#define PTAPAR_PTAPAR21_BITMASK       (0x20U)
#define PTAPAR_PTAPAR30_BITMASK       (0x40U)
#define PTAPAR_PTAPAR31_BITMASK       (0x80U)
#define PTAPAR_PTAPAR0_GRPMASK        (0x3U)
#define PTAPAR_PTAPAR0_GRPPOS         (0U)
#define PTAPAR_PTAPAR1_GRPMASK        (0xCU)
#define PTAPAR_PTAPAR1_GRPPOS         (0x2U)
#define PTAPAR_PTAPAR2_GRPMASK        (0x30U)
#define PTAPAR_PTAPAR2_GRPPOS         (0x4U)
#define PTAPAR_PTAPAR3_GRPMASK        (0xC0U)
#define PTAPAR_PTAPAR3_GRPPOS         (0x6U)


/******************************************
*** Peripheral PORTTC
*******************************************/

/*** PORTTC - Port Output Data Register.; 0x0010000F ***/
#define PORTTC                        (*((volatile uint8 *)(&__IPSBAR[0x0010000FUL])))
#define PORTTC_PORTTC0_BITMASK        (0x1U)
#define PORTTC_PORTTC1_BITMASK        (0x2U)
#define PORTTC_PORTTC2_BITMASK        (0x4U)
#define PORTTC_PORTTC3_BITMASK        (0x8U)

/*** DDRTC - Port Data Direction Register.; 0x00100027 ***/
#define DDRTC                         (*((volatile uint8 *)(&__IPSBAR[0x00100027UL])))
#define DDRTC_DDRTC0_BITMASK          (0x1U)
#define DDRTC_DDRTC1_BITMASK          (0x2U)
#define DDRTC_DDRTC2_BITMASK          (0x4U)
#define DDRTC_DDRTC3_BITMASK          (0x8U)

/*** SETTC - Port Pin Data/Set Data Register.; 0x0010003F ***/
#define SETTC                         (*((volatile uint8 *)(&__IPSBAR[0x0010003FUL])))
#define SETTC_SETTC0_BITMASK          (0x1U)
#define SETTC_SETTC1_BITMASK          (0x2U)
#define SETTC_SETTC2_BITMASK          (0x4U)
#define SETTC_SETTC3_BITMASK          (0x8U)

/*** CLRTC - Port Clear Output Data Register.; 0x00100057 ***/
#define CLRTC                         (*((volatile uint8 *)(&__IPSBAR[0x00100057UL])))
#define CLRTC_CLRTC0_BITMASK          (0x1U)
#define CLRTC_CLRTC1_BITMASK          (0x2U)
#define CLRTC_CLRTC2_BITMASK          (0x4U)
#define CLRTC_CLRTC3_BITMASK          (0x8U)

/*** PTCPAR - Quad Function Pin Assignment Register.; 0x0010006F ***/
#define PTCPAR                        (*((volatile uint8 *)(&__IPSBAR[0x0010006FUL])))
#define PTCPAR_PTCPAR00_BITMASK       (0x1U)
#define PTCPAR_PTCPAR01_BITMASK       (0x2U)
#define PTCPAR_PTCPAR10_BITMASK       (0x4U)
#define PTCPAR_PTCPAR11_BITMASK       (0x8U)
#define PTCPAR_PTCPAR20_BITMASK       (0x10U)
#define PTCPAR_PTCPAR21_BITMASK       (0x20U)
#define PTCPAR_PTCPAR30_BITMASK       (0x40U)
#define PTCPAR_PTCPAR31_BITMASK       (0x80U)
#define PTCPAR_PTCPAR0_GRPMASK        (0x3U)
#define PTCPAR_PTCPAR0_GRPPOS         (0U)
#define PTCPAR_PTCPAR1_GRPMASK        (0xCU)
#define PTCPAR_PTCPAR1_GRPPOS         (0x2U)
#define PTCPAR_PTCPAR2_GRPMASK        (0x30U)
#define PTCPAR_PTCPAR2_GRPPOS         (0x4U)
#define PTCPAR_PTCPAR3_GRPMASK        (0xC0U)
#define PTCPAR_PTCPAR3_GRPPOS         (0x6U)


/******************************************
*** Peripheral PORTTD
*******************************************/

/*** PORTTD - Port Output Data Register.; 0x00100010 ***/
#define PORTTD                        (*((volatile uint8 *)(&__IPSBAR[0x00100010UL])))
#define PORTTD_PORTTD0_BITMASK        (0x1U)
#define PORTTD_PORTTD1_BITMASK        (0x2U)
#define PORTTD_PORTTD2_BITMASK        (0x4U)
#define PORTTD_PORTTD3_BITMASK        (0x8U)

/*** DDRTD - Port Data Direction Register.; 0x00100028 ***/
#define DDRTD                         (*((volatile uint8 *)(&__IPSBAR[0x00100028UL])))
#define DDRTD_DDRTD0_BITMASK          (0x1U)
#define DDRTD_DDRTD1_BITMASK          (0x2U)
#define DDRTD_DDRTD2_BITMASK          (0x4U)
#define DDRTD_DDRTD3_BITMASK          (0x8U)

/*** SETTD - Port Pin Data/Set Data Register.; 0x00100040 ***/
#define SETTD                         (*((volatile uint8 *)(&__IPSBAR[0x00100040UL])))
#define SETTD_SETTD0_BITMASK          (0x1U)
#define SETTD_SETTD1_BITMASK          (0x2U)
#define SETTD_SETTD2_BITMASK          (0x4U)
#define SETTD_SETTD3_BITMASK          (0x8U)

/*** CLRTD - Port Clear Output Data Register.; 0x00100058 ***/
#define CLRTD                         (*((volatile uint8 *)(&__IPSBAR[0x00100058UL])))
#define CLRTD_CLRTD0_BITMASK          (0x1U)
#define CLRTD_CLRTD1_BITMASK          (0x2U)
#define CLRTD_CLRTD2_BITMASK          (0x4U)
#define CLRTD_CLRTD3_BITMASK          (0x8U)

/*** PTDPAR - Dual Function Pin Assignment Register.; 0x00100070 ***/
#define PTDPAR                        (*((volatile uint8 *)(&__IPSBAR[0x00100070UL])))
#define PTDPAR_PTDPAR0_BITMASK        (0x1U)
#define PTDPAR_PTDPAR1_BITMASK        (0x2U)
#define PTDPAR_PTDPAR2_BITMASK        (0x4U)
#define PTDPAR_PTDPAR3_BITMASK        (0x8U)


/******************************************
*** Peripheral PORTUA
*******************************************/

/*** PORTUA - Port Output Data Register.; 0x00100011 ***/
#define PORTUA                        (*((volatile uint8 *)(&__IPSBAR[0x00100011UL])))
#define PORTUA_PORTUA0_BITMASK        (0x1U)
#define PORTUA_PORTUA1_BITMASK        (0x2U)
#define PORTUA_PORTUA2_BITMASK        (0x4U)
#define PORTUA_PORTUA3_BITMASK        (0x8U)

/*** DDRUA - Port Data Direction Register.; 0x00100029 ***/
#define DDRUA                         (*((volatile uint8 *)(&__IPSBAR[0x00100029UL])))
#define DDRUA_DDRUA0_BITMASK          (0x1U)
#define DDRUA_DDRUA1_BITMASK          (0x2U)
#define DDRUA_DDRUA2_BITMASK          (0x4U)
#define DDRUA_DDRUA3_BITMASK          (0x8U)

/*** SETUA - Port Pin Data/Set Data Register.; 0x00100041 ***/
#define SETUA                         (*((volatile uint8 *)(&__IPSBAR[0x00100041UL])))
#define SETUA_SETUA0_BITMASK          (0x1U)
#define SETUA_SETUA1_BITMASK          (0x2U)
#define SETUA_SETUA2_BITMASK          (0x4U)
#define SETUA_SETUA3_BITMASK          (0x8U)

/*** CLRUA - Port Clear Output Data Register.; 0x00100059 ***/
#define CLRUA                         (*((volatile uint8 *)(&__IPSBAR[0x00100059UL])))
#define CLRUA_CLRUA0_BITMASK          (0x1U)
#define CLRUA_CLRUA1_BITMASK          (0x2U)
#define CLRUA_CLRUA2_BITMASK          (0x4U)
#define CLRUA_CLRUA3_BITMASK          (0x8U)

/*** PUAPAR - Quad Function Pin Assignment Register.; 0x00100071 ***/
#define PUAPAR                        (*((volatile uint8 *)(&__IPSBAR[0x00100071UL])))
#define PUAPAR_PUAPAR00_BITMASK       (0x1U)
#define PUAPAR_PUAPAR01_BITMASK       (0x2U)
#define PUAPAR_PUAPAR10_BITMASK       (0x4U)
#define PUAPAR_PUAPAR11_BITMASK       (0x8U)
#define PUAPAR_PUAPAR20_BITMASK       (0x10U)
#define PUAPAR_PUAPAR21_BITMASK       (0x20U)
#define PUAPAR_PUAPAR30_BITMASK       (0x40U)
#define PUAPAR_PUAPAR31_BITMASK       (0x80U)
#define PUAPAR_PUAPAR0_GRPMASK        (0x3U)
#define PUAPAR_PUAPAR0_GRPPOS         (0U)
#define PUAPAR_PUAPAR1_GRPMASK        (0xCU)
#define PUAPAR_PUAPAR1_GRPPOS         (0x2U)
#define PUAPAR_PUAPAR2_GRPMASK        (0x30U)
#define PUAPAR_PUAPAR2_GRPPOS         (0x4U)
#define PUAPAR_PUAPAR3_GRPMASK        (0xC0U)
#define PUAPAR_PUAPAR3_GRPPOS         (0x6U)


/******************************************
*** Peripheral PORTUB
*******************************************/

/*** PORTUB - Port Output Data Register.; 0x00100012 ***/
#define PORTUB                        (*((volatile uint8 *)(&__IPSBAR[0x00100012UL])))
#define PORTUB_PORTUB0_BITMASK        (0x1U)
#define PORTUB_PORTUB1_BITMASK        (0x2U)
#define PORTUB_PORTUB2_BITMASK        (0x4U)
#define PORTUB_PORTUB3_BITMASK        (0x8U)

/*** DDRUB - Port Data Direction Register.; 0x0010002A ***/
#define DDRUB                         (*((volatile uint8 *)(&__IPSBAR[0x0010002AUL])))
#define DDRUB_DDRUB0_BITMASK          (0x1U)
#define DDRUB_DDRUB1_BITMASK          (0x2U)
#define DDRUB_DDRUB2_BITMASK          (0x4U)
#define DDRUB_DDRUB3_BITMASK          (0x8U)

/*** SETUB - Port Pin Data/Set Data Register.; 0x00100042 ***/
#define SETUB                         (*((volatile uint8 *)(&__IPSBAR[0x00100042UL])))
#define SETUB_SETUB0_BITMASK          (0x1U)
#define SETUB_SETUB1_BITMASK          (0x2U)
#define SETUB_SETUB2_BITMASK          (0x4U)
#define SETUB_SETUB3_BITMASK          (0x8U)

/*** CLRUB - Port Clear Output Data Register.; 0x0010005A ***/
#define CLRUB                         (*((volatile uint8 *)(&__IPSBAR[0x0010005AUL])))
#define CLRUB_CLRUB0_BITMASK          (0x1U)
#define CLRUB_CLRUB1_BITMASK          (0x2U)
#define CLRUB_CLRUB2_BITMASK          (0x4U)
#define CLRUB_CLRUB3_BITMASK          (0x8U)

/*** PUBPAR - Quad Function Pin Assignment Register.; 0x00100072 ***/
#define PUBPAR                        (*((volatile uint8 *)(&__IPSBAR[0x00100072UL])))
#define PUBPAR_PUBPAR00_BITMASK       (0x1U)
#define PUBPAR_PUBPAR01_BITMASK       (0x2U)
#define PUBPAR_PUBPAR10_BITMASK       (0x4U)
#define PUBPAR_PUBPAR11_BITMASK       (0x8U)
#define PUBPAR_PUBPAR20_BITMASK       (0x10U)
#define PUBPAR_PUBPAR21_BITMASK       (0x20U)
#define PUBPAR_PUBPAR30_BITMASK       (0x40U)
#define PUBPAR_PUBPAR31_BITMASK       (0x80U)
#define PUBPAR_PUBPAR0_GRPMASK        (0x3U)
#define PUBPAR_PUBPAR0_GRPPOS         (0U)
#define PUBPAR_PUBPAR1_GRPMASK        (0xCU)
#define PUBPAR_PUBPAR1_GRPPOS         (0x2U)
#define PUBPAR_PUBPAR2_GRPMASK        (0x30U)
#define PUBPAR_PUBPAR2_GRPPOS         (0x4U)
#define PUBPAR_PUBPAR3_GRPMASK        (0xC0U)
#define PUBPAR_PUBPAR3_GRPPOS         (0x6U)


/******************************************
*** Peripheral PORTUC
*******************************************/

/*** PORTUC - Port Output Data Register.; 0x00100013 ***/
#define PORTUC                        (*((volatile uint8 *)(&__IPSBAR[0x00100013UL])))
#define PORTUC_PORTUC0_BITMASK        (0x1U)
#define PORTUC_PORTUC1_BITMASK        (0x2U)
#define PORTUC_PORTUC2_BITMASK        (0x4U)
#define PORTUC_PORTUC3_BITMASK        (0x8U)

/*** DDRUC - Port Data Direction Register.; 0x0010002B ***/
#define DDRUC                         (*((volatile uint8 *)(&__IPSBAR[0x0010002BUL])))
#define DDRUC_DDRUC0_BITMASK          (0x1U)
#define DDRUC_DDRUC1_BITMASK          (0x2U)
#define DDRUC_DDRUC2_BITMASK          (0x4U)
#define DDRUC_DDRUC3_BITMASK          (0x8U)

/*** SETUC - Port Pin Data/Set Data Register.; 0x00100043 ***/
#define SETUC                         (*((volatile uint8 *)(&__IPSBAR[0x00100043UL])))
#define SETUC_SETUC0_BITMASK          (0x1U)
#define SETUC_SETUC1_BITMASK          (0x2U)
#define SETUC_SETUC2_BITMASK          (0x4U)
#define SETUC_SETUC3_BITMASK          (0x8U)

/*** CLRUC - Port Clear Output Data Register.; 0x0010005B ***/
#define CLRUC                         (*((volatile uint8 *)(&__IPSBAR[0x0010005BUL])))
#define CLRUC_CLRUC0_BITMASK          (0x1U)
#define CLRUC_CLRUC1_BITMASK          (0x2U)
#define CLRUC_CLRUC2_BITMASK          (0x4U)
#define CLRUC_CLRUC3_BITMASK          (0x8U)

/*** PUCPAR - Dual Function Pin Assignment Register.; 0x00100073 ***/
#define PUCPAR                        (*((volatile uint8 *)(&__IPSBAR[0x00100073UL])))
#define PUCPAR_PUCPAR0_BITMASK        (0x1U)
#define PUCPAR_PUCPAR1_BITMASK        (0x2U)
#define PUCPAR_PUCPAR2_BITMASK        (0x4U)
#define PUCPAR_PUCPAR3_BITMASK        (0x8U)


/******************************************
*** Peripheral PORTDD
*******************************************/

/*** PORTDD - Port Output Data Register.; 0x00100014 ***/
#define PORTDD                        (*((volatile uint8 *)(&__IPSBAR[0x00100014UL])))
#define PORTDD_PORTDD0_BITMASK        (0x1U)
#define PORTDD_PORTDD1_BITMASK        (0x2U)
#define PORTDD_PORTDD2_BITMASK        (0x4U)
#define PORTDD_PORTDD3_BITMASK        (0x8U)
#define PORTDD_PORTDD4_BITMASK        (0x10U)
#define PORTDD_PORTDD5_BITMASK        (0x20U)
#define PORTDD_PORTDD6_BITMASK        (0x40U)
#define PORTDD_PORTDD7_BITMASK        (0x80U)

/*** DDRDD - Port Data Direction Register.; 0x0010002C ***/
#define DDRDD                         (*((volatile uint8 *)(&__IPSBAR[0x0010002CUL])))
#define DDRDD_DDRDD0_BITMASK          (0x1U)
#define DDRDD_DDRDD1_BITMASK          (0x2U)
#define DDRDD_DDRDD2_BITMASK          (0x4U)
#define DDRDD_DDRDD3_BITMASK          (0x8U)
#define DDRDD_DDRDD4_BITMASK          (0x10U)
#define DDRDD_DDRDD5_BITMASK          (0x20U)
#define DDRDD_DDRDD6_BITMASK          (0x40U)
#define DDRDD_DDRDD7_BITMASK          (0x80U)

/*** SETDD - Port Pin Data/Set Data Register.; 0x00100044 ***/
#define SETDD                         (*((volatile uint8 *)(&__IPSBAR[0x00100044UL])))
#define SETDD_SETDD0_BITMASK          (0x1U)
#define SETDD_SETDD1_BITMASK          (0x2U)
#define SETDD_SETDD2_BITMASK          (0x4U)
#define SETDD_SETDD3_BITMASK          (0x8U)
#define SETDD_SETDD4_BITMASK          (0x10U)
#define SETDD_SETDD5_BITMASK          (0x20U)
#define SETDD_SETDD6_BITMASK          (0x40U)
#define SETDD_SETDD7_BITMASK          (0x80U)

/*** CLRDD - Port Clear Output Data Register.; 0x0010005C ***/
#define CLRDD                         (*((volatile uint8 *)(&__IPSBAR[0x0010005CUL])))
#define CLRDD_CLRDD0_BITMASK          (0x1U)
#define CLRDD_CLRDD1_BITMASK          (0x2U)
#define CLRDD_CLRDD2_BITMASK          (0x4U)
#define CLRDD_CLRDD3_BITMASK          (0x8U)
#define CLRDD_CLRDD4_BITMASK          (0x10U)
#define CLRDD_CLRDD5_BITMASK          (0x20U)
#define CLRDD_CLRDD6_BITMASK          (0x40U)
#define CLRDD_CLRDD7_BITMASK          (0x80U)

/*** PDDPAR - Dual Function Pin Assignment Register.; 0x00100074 ***/
#define PDDPAR                        (*((volatile uint8 *)(&__IPSBAR[0x00100074UL])))
#define PDDPAR_PDDPAR0_BITMASK        (0x1U)
#define PDDPAR_PDDPAR1_BITMASK        (0x2U)
#define PDDPAR_PDDPAR2_BITMASK        (0x4U)
#define PDDPAR_PDDPAR3_BITMASK        (0x8U)
#define PDDPAR_PDDPAR4_BITMASK        (0x10U)
#define PDDPAR_PDDPAR5_BITMASK        (0x20U)
#define PDDPAR_PDDPAR6_BITMASK        (0x40U)
#define PDDPAR_PDDPAR7_BITMASK        (0x80U)


/******************************************
*** Peripheral PORTLD
*******************************************/

/*** PORTLD - Port Output Data Register.; 0x00100015 ***/
#define PORTLD                        (*((volatile uint8 *)(&__IPSBAR[0x00100015UL])))
#define PORTLD_PORTLD0_BITMASK        (0x1U)
#define PORTLD_PORTLD1_BITMASK        (0x2U)
#define PORTLD_PORTLD2_BITMASK        (0x4U)
#define PORTLD_PORTLD3_BITMASK        (0x8U)
#define PORTLD_PORTLD4_BITMASK        (0x10U)
#define PORTLD_PORTLD5_BITMASK        (0x20U)
#define PORTLD_PORTLD6_BITMASK        (0x40U)

/*** DDRLD - Port Data Direction Register.; 0x0010002D ***/
#define DDRLD                         (*((volatile uint8 *)(&__IPSBAR[0x0010002DUL])))
#define DDRLD_DDRLD0_BITMASK          (0x1U)
#define DDRLD_DDRLD1_BITMASK          (0x2U)
#define DDRLD_DDRLD2_BITMASK          (0x4U)
#define DDRLD_DDRLD3_BITMASK          (0x8U)
#define DDRLD_DDRLD4_BITMASK          (0x10U)
#define DDRLD_DDRLD5_BITMASK          (0x20U)
#define DDRLD_DDRLD6_BITMASK          (0x40U)

/*** SETLD - Port Pin Data/Set Data Register.; 0x00100045 ***/
#define SETLD                         (*((volatile uint8 *)(&__IPSBAR[0x00100045UL])))
#define SETLD_SETLD0_BITMASK          (0x1U)
#define SETLD_SETLD1_BITMASK          (0x2U)
#define SETLD_SETLD2_BITMASK          (0x4U)
#define SETLD_SETLD3_BITMASK          (0x8U)
#define SETLD_SETLD4_BITMASK          (0x10U)
#define SETLD_SETLD5_BITMASK          (0x20U)
#define SETLD_SETLD6_BITMASK          (0x40U)

/*** CLRLD - Port Clear Output Data Register.; 0x0010005D ***/
#define CLRLD                         (*((volatile uint8 *)(&__IPSBAR[0x0010005DUL])))
#define CLRLD_CLRLD0_BITMASK          (0x1U)
#define CLRLD_CLRLD1_BITMASK          (0x2U)
#define CLRLD_CLRLD2_BITMASK          (0x4U)
#define CLRLD_CLRLD3_BITMASK          (0x8U)
#define CLRLD_CLRLD4_BITMASK          (0x10U)
#define CLRLD_CLRLD5_BITMASK          (0x20U)
#define CLRLD_CLRLD6_BITMASK          (0x40U)

/*** PLDPAR - Dual Function Pin Assignment Register.; 0x00100075 ***/
#define PLDPAR                        (*((volatile uint8 *)(&__IPSBAR[0x00100075UL])))
#define PLDPAR_PLDPAR0_BITMASK        (0x1U)
#define PLDPAR_PLDPAR1_BITMASK        (0x2U)
#define PLDPAR_PLDPAR2_BITMASK        (0x4U)
#define PLDPAR_PLDPAR3_BITMASK        (0x8U)
#define PLDPAR_PLDPAR4_BITMASK        (0x10U)
#define PLDPAR_PLDPAR5_BITMASK        (0x20U)
#define PLDPAR_PLDPAR6_BITMASK        (0x40U)


/******************************************
*** Peripheral PORTGP
*******************************************/

/*** PORTGP - Port Output Data Register.; 0x00100016 ***/
#define PORTGP                        (*((volatile uint8 *)(&__IPSBAR[0x00100016UL])))
#define PORTGP_PORTGP0_BITMASK        (0x1U)
#define PORTGP_PORTGP1_BITMASK        (0x2U)
#define PORTGP_PORTGP2_BITMASK        (0x4U)
#define PORTGP_PORTGP3_BITMASK        (0x8U)
#define PORTGP_PORTGP4_BITMASK        (0x10U)
#define PORTGP_PORTGP5_BITMASK        (0x20U)
#define PORTGP_PORTGP6_BITMASK        (0x40U)
#define PORTGP_PORTGP7_BITMASK        (0x80U)

/*** DDRGP - Port Data Direction Register.; 0x0010002E ***/
#define DDRGP                         (*((volatile uint8 *)(&__IPSBAR[0x0010002EUL])))
#define DDRGP_DDRGP0_BITMASK          (0x1U)
#define DDRGP_DDRGP1_BITMASK          (0x2U)
#define DDRGP_DDRGP2_BITMASK          (0x4U)
#define DDRGP_DDRGP3_BITMASK          (0x8U)
#define DDRGP_DDRGP4_BITMASK          (0x10U)
#define DDRGP_DDRGP5_BITMASK          (0x20U)
#define DDRGP_DDRGP6_BITMASK          (0x40U)
#define DDRGP_DDRGP7_BITMASK          (0x80U)

/*** SETGP - Port Pin Data/Set Data Register.; 0x00100046 ***/
#define SETGP                         (*((volatile uint8 *)(&__IPSBAR[0x00100046UL])))
#define SETGP_SETGP0_BITMASK          (0x1U)
#define SETGP_SETGP1_BITMASK          (0x2U)
#define SETGP_SETGP2_BITMASK          (0x4U)
#define SETGP_SETGP3_BITMASK          (0x8U)
#define SETGP_SETGP4_BITMASK          (0x10U)
#define SETGP_SETGP5_BITMASK          (0x20U)
#define SETGP_SETGP6_BITMASK          (0x40U)
#define SETGP_SETGP7_BITMASK          (0x80U)

/*** CLRGP - Port Clear Output Data Register.; 0x0010005E ***/
#define CLRGP                         (*((volatile uint8 *)(&__IPSBAR[0x0010005EUL])))
#define CLRGP_CLRGP0_BITMASK          (0x1U)
#define CLRGP_CLRGP1_BITMASK          (0x2U)
#define CLRGP_CLRGP2_BITMASK          (0x4U)
#define CLRGP_CLRGP3_BITMASK          (0x8U)
#define CLRGP_CLRGP4_BITMASK          (0x10U)
#define CLRGP_CLRGP5_BITMASK          (0x20U)
#define CLRGP_CLRGP6_BITMASK          (0x40U)
#define CLRGP_CLRGP7_BITMASK          (0x80U)

/*** PGPPAR - Dual Function Pin Assignment Register.; 0x00100076 ***/
#define PGPPAR                        (*((volatile uint8 *)(&__IPSBAR[0x00100076UL])))
#define PGPPAR_PGPPAR0_BITMASK        (0x1U)
#define PGPPAR_PGPPAR1_BITMASK        (0x2U)
#define PGPPAR_PGPPAR2_BITMASK        (0x4U)
#define PGPPAR_PGPPAR3_BITMASK        (0x8U)
#define PGPPAR_PGPPAR4_BITMASK        (0x10U)
#define PGPPAR_PGPPAR5_BITMASK        (0x20U)
#define PGPPAR_PGPPAR6_BITMASK        (0x40U)
#define PGPPAR_PGPPAR7_BITMASK        (0x80U)


/******************************************
*** Peripheral PAD
*******************************************/

/*** PWOR - Pin Wired OR Register.; 0x00100078 ***/
#define PWOR                          (*((volatile uint16 *)(&__IPSBAR[0x00100078UL])))
#define PWOR_PWOR0_BITMASK            (0x1U)
#define PWOR_PWOR1_BITMASK            (0x2U)
#define PWOR_PWOR2_BITMASK            (0x4U)
#define PWOR_PWOR3_BITMASK            (0x8U)
#define PWOR_PWOR4_BITMASK            (0x10U)
#define PWOR_PWOR5_BITMASK            (0x20U)
#define PWOR_PWOR6_BITMASK            (0x40U)
#define PWOR_PWOR7_BITMASK            (0x80U)
#define PWOR_PWOR8_BITMASK            (0x100U)
#define PWOR_PWOR9_BITMASK            (0x200U)
#define PWOR_PWOR10_BITMASK           (0x400U)
#define PWOR_PWOR11_BITMASK           (0x800U)
#define PWOR_PWOR12_BITMASK           (0x1000U)
#define PWOR_PWOR13_BITMASK           (0x2000U)
#define PWOR_PWOR14_BITMASK           (0x4000U)
#define PWOR_PWOR15_BITMASK           (0x8000U)

/*** PDSR1 - Pin Drive Strength Register 1.; 0x0010007A ***/
#define PDSR1                         (*((volatile uint16 *)(&__IPSBAR[0x0010007AUL])))
#define PDSR1_PDSR32_BITMASK          (0x1U)
#define PDSR1_PDSR33_BITMASK          (0x2U)
#define PDSR1_PDSR34_BITMASK          (0x4U)
#define PDSR1_PDSR35_BITMASK          (0x8U)
#define PDSR1_PDSR36_BITMASK          (0x10U)
#define PDSR1_PDSR37_BITMASK          (0x20U)
#define PDSR1_PDSR38_BITMASK          (0x40U)
#define PDSR1_PDSR39_BITMASK          (0x80U)
#define PDSR1_PDSR40_BITMASK          (0x100U)
#define PDSR1_PDSR41_BITMASK          (0x200U)
#define PDSR1_PDSR42_BITMASK          (0x400U)
#define PDSR1_PDSR43_BITMASK          (0x800U)
#define PDSR1_PDSR44_BITMASK          (0x1000U)
#define PDSR1_PDSR45_BITMASK          (0x2000U)
#define PDSR1_PDSR46_BITMASK          (0x4000U)
#define PDSR1_PDSR47_BITMASK          (0x8000U)

/*** PDSR0 - Pin Drive Strength Register 0.; 0x0010007C ***/
#define PDSR0                         (*((volatile uint32 *)(&__IPSBAR[0x0010007CUL])))
#define PDSR0_PDSR0_BITMASK           (0x1U)
#define PDSR0_PDSR1_BITMASK           (0x2U)
#define PDSR0_PDSR2_BITMASK           (0x4U)
#define PDSR0_PDSR3_BITMASK           (0x8U)
#define PDSR0_PDSR4_BITMASK           (0x10U)
#define PDSR0_PDSR5_BITMASK           (0x20U)
#define PDSR0_PDSR6_BITMASK           (0x40U)
#define PDSR0_PDSR7_BITMASK           (0x80U)
#define PDSR0_PDSR8_BITMASK           (0x100U)
#define PDSR0_PDSR9_BITMASK           (0x200U)
#define PDSR0_PDSR10_BITMASK          (0x400U)
#define PDSR0_PDSR11_BITMASK          (0x800U)
#define PDSR0_PDSR12_BITMASK          (0x1000U)
#define PDSR0_PDSR13_BITMASK          (0x2000U)
#define PDSR0_PDSR14_BITMASK          (0x4000U)
#define PDSR0_PDSR15_BITMASK          (0x8000U)
#define PDSR0_PDSR16_BITMASK          (0x10000U)
#define PDSR0_PDSR17_BITMASK          (0x20000U)
#define PDSR0_PDSR18_BITMASK          (0x40000U)
#define PDSR0_PDSR19_BITMASK          (0x80000U)
#define PDSR0_PDSR20_BITMASK          (0x100000U)
#define PDSR0_PDSR21_BITMASK          (0x200000U)
#define PDSR0_PDSR22_BITMASK          (0x400000U)
#define PDSR0_PDSR23_BITMASK          (0x800000U)
#define PDSR0_PDSR24_BITMASK          (0x1000000U)
#define PDSR0_PDSR25_BITMASK          (0x2000000U)
#define PDSR0_PDSR26_BITMASK          (0x4000000U)
#define PDSR0_PDSR27_BITMASK          (0x8000000U)
#define PDSR0_PDSR28_BITMASK          (0x10000000U)
#define PDSR0_PDSR29_BITMASK          (0x20000000U)
#define PDSR0_PDSR30_BITMASK          (0x40000000U)
#define PDSR0_PDSR31_BITMASK          (0x80000000U)


/******************************************
*** Peripheral ResetController
*******************************************/

/*** ResetController_RCR - Reset Control Register.; 0x00110000 ***/
#define ResetController_RCR           (*((volatile uint8 *)(&__IPSBAR[0x00110000UL])))
#define ResetController_RCR_LVDE_BITMASK (0x1U)
#define ResetController_RCR_LVDRE_BITMASK (0x4U)
#define ResetController_RCR_LVDIE_BITMASK (0x8U)
#define ResetController_RCR_LVDF_BITMASK (0x10U)
#define ResetController_RCR_FRCRSTOUT_BITMASK (0x40U)
#define ResetController_RCR_SOFTRST_BITMASK (0x80U)

/*** RSR - Reset Status Register.; 0x00110001 ***/
#define RSR                           (*((volatile uint8 *)(&__IPSBAR[0x00110001UL])))
#define RSR_LOL_BITMASK               (0x1U)
#define RSR_LOC_BITMASK               (0x2U)
#define RSR_EXT_BITMASK               (0x4U)
#define RSR_POR_BITMASK               (0x8U)
#define RSR_SOFT_BITMASK              (0x20U)
#define RSR_LVD_BITMASK               (0x40U)


/******************************************
*** Peripheral CCM
*******************************************/

/*** CCR - Chip Configuration Register.; 0x00110004 ***/
#define CCR                           (*((volatile uint16 *)(&__IPSBAR[0x00110004UL])))
#define CCR_BMT0_BITMASK              (0x1U)
#define CCR_BMT1_BITMASK              (0x2U)
#define CCR_BMT2_BITMASK              (0x4U)
#define CCR_BME_BITMASK               (0x8U)
#define CCR_PSTEN_BITMASK             (0x20U)
#define CCR_SZEN_BITMASK              (0x40U)
#define CCR_BMT_GRPMASK               (0x7U)
#define CCR_BMT_GRPPOS                (0U)

/*** RCON - Reset Configuration Register.; 0x00110008 ***/
#define RCON                          (*((volatile uint16 *)(&__IPSBAR[0x00110008UL])))
#define RCON_MODE_BITMASK             (0x1U)
#define RCON_RLOAD_BITMASK            (0x20U)

/*** CIR - Chip Identification Register.; 0x0011000A ***/
#define CIR                           (*((volatile uint16 *)(&__IPSBAR[0x0011000AUL])))
#define CIR_PRN0_BITMASK              (0x1U)
#define CIR_PRN1_BITMASK              (0x2U)
#define CIR_PRN2_BITMASK              (0x4U)
#define CIR_PRN3_BITMASK              (0x8U)
#define CIR_PRN4_BITMASK              (0x10U)
#define CIR_PRN5_BITMASK              (0x20U)
#define CIR_PIN0_BITMASK              (0x40U)
#define CIR_PIN1_BITMASK              (0x80U)
#define CIR_PIN2_BITMASK              (0x100U)
#define CIR_PIN3_BITMASK              (0x200U)
#define CIR_PIN4_BITMASK              (0x400U)
#define CIR_PIN5_BITMASK              (0x800U)
#define CIR_PIN6_BITMASK              (0x1000U)
#define CIR_PIN7_BITMASK              (0x2000U)
#define CIR_PIN8_BITMASK              (0x4000U)
#define CIR_PIN9_BITMASK              (0x8000U)
#define CIR_PRN_GRPMASK               (0x3FU)
#define CIR_PRN_GRPPOS                (0U)
#define CIR_PIN_GRPMASK               (0xFFC0U)
#define CIR_PIN_GRPPOS                (0x6U)


/******************************************
*** Peripheral ClockModule
*******************************************/

/*** SYNCR - Synthesizer Control Register.; 0x00120000 ***/
#define SYNCR                         (*((volatile uint16 *)(&__IPSBAR[0x00120000UL])))
#define SYNCR_PLLEN_BITMASK           (0x1U)
#define SYNCR_PLLMODE_BITMASK         (0x2U)
#define SYNCR_CLKSRC_BITMASK          (0x4U)
#define SYNCR_FWKUP_BITMASK           (0x20U)
#define SYNCR_DISCLK_BITMASK          (0x40U)
#define SYNCR_LOCEN_BITMASK           (0x80U)
#define SYNCR_RFD0_BITMASK            (0x100U)
#define SYNCR_RFD1_BITMASK            (0x200U)
#define SYNCR_RFD2_BITMASK            (0x400U)
#define SYNCR_LOCRE_BITMASK           (0x800U)
#define SYNCR_MFD0_BITMASK            (0x1000U)
#define SYNCR_MFD1_BITMASK            (0x2000U)
#define SYNCR_MFD2_BITMASK            (0x4000U)
#define SYNCR_LOLRE_BITMASK           (0x8000U)
#define SYNCR_RFD_GRPMASK             (0x700U)
#define SYNCR_RFD_GRPPOS              (0x8U)
#define SYNCR_MFD_GRPMASK             (0x7000U)
#define SYNCR_MFD_GRPPOS              (0xCU)

/*** SYNSR - Synthesizer Status Register.; 0x00120002 ***/
#define SYNSR                         (*((volatile uint8 *)(&__IPSBAR[0x00120002UL])))
#define SYNSR_LOCS_BITMASK            (0x4U)
#define SYNSR_LOCK_BITMASK            (0x8U)
#define SYNSR_LOCKS_BITMASK           (0x10U)
#define SYNSR_EXTOSC_BITMASK          (0x80U)

/*** ClockModule_LPCR - Low Power Control Register.; 0x00120007 ***/
#define ClockModule_LPCR              (*((volatile uint8 *)(&__IPSBAR[0x00120007UL])))
#define ClockModule_LPCR_LPD0_BITMASK (0x1U)
#define ClockModule_LPCR_LPD1_BITMASK (0x2U)
#define ClockModule_LPCR_LPD2_BITMASK (0x4U)
#define ClockModule_LPCR_LPD3_BITMASK (0x8U)
#define ClockModule_LPCR_LPD_GRPMASK  (0xFU)
#define ClockModule_LPCR_LPD_GRPPOS   (0U)

/*** CCHR - Clock Control High Register.; 0x00120008 ***/
#define CCHR                          (*((volatile uint8 *)(&__IPSBAR[0x00120008UL])))
#define CCHR_CCHR0_BITMASK            (0x1U)
#define CCHR_CCHR1_BITMASK            (0x2U)
#define CCHR_CCHR2_BITMASK            (0x4U)
#define CCHR_CCHR_GRPMASK             (0x7U)
#define CCHR_CCHR_GRPPOS              (0U)

/*** RTCDR - Real Time Clock Divide Register.; 0x0012000C ***/
#define RTCDR                         (*((volatile uint32 *)(&__IPSBAR[0x0012000CUL])))
#define RTCDR_RTCDF0_BITMASK          (0x1U)
#define RTCDR_RTCDF1_BITMASK          (0x2U)
#define RTCDR_RTCDF2_BITMASK          (0x4U)
#define RTCDR_RTCDF3_BITMASK          (0x8U)
#define RTCDR_RTCDF4_BITMASK          (0x10U)
#define RTCDR_RTCDF5_BITMASK          (0x20U)
#define RTCDR_RTCDF6_BITMASK          (0x40U)
#define RTCDR_RTCDF7_BITMASK          (0x80U)
#define RTCDR_RTCDF8_BITMASK          (0x100U)
#define RTCDR_RTCDF9_BITMASK          (0x200U)
#define RTCDR_RTCDF10_BITMASK         (0x400U)
#define RTCDR_RTCDF11_BITMASK         (0x800U)
#define RTCDR_RTCDF12_BITMASK         (0x1000U)
#define RTCDR_RTCDF13_BITMASK         (0x2000U)
#define RTCDR_RTCDF14_BITMASK         (0x4000U)
#define RTCDR_RTCDF15_BITMASK         (0x8000U)
#define RTCDR_RTCDF16_BITMASK         (0x10000U)
#define RTCDR_RTCDF17_BITMASK         (0x20000U)
#define RTCDR_RTCDF18_BITMASK         (0x40000U)
#define RTCDR_RTCDF19_BITMASK         (0x80000U)
#define RTCDR_RTCDF20_BITMASK         (0x100000U)
#define RTCDR_RTCDF21_BITMASK         (0x200000U)
#define RTCDR_RTCDF22_BITMASK         (0x400000U)
#define RTCDR_RTCDF23_BITMASK         (0x800000U)
#define RTCDR_RTCDF24_BITMASK         (0x1000000U)
#define RTCDR_RTCDF25_BITMASK         (0x2000000U)
#define RTCDR_RTCDF26_BITMASK         (0x4000000U)
#define RTCDR_RTCDF27_BITMASK         (0x8000000U)
#define RTCDR_RTCDF28_BITMASK         (0x10000000U)
#define RTCDR_RTCDF29_BITMASK         (0x20000000U)
#define RTCDR_RTCDF30_BITMASK         (0x40000000U)
#define RTCDR_RTCDF31_BITMASK         (0x80000000U)
#define RTCDR_RTCDF_GRPMASK           (0xFFFFFFFFU)
#define RTCDR_RTCDF_GRPPOS            (0U)


/******************************************
*** Peripheral EPORT0
*******************************************/

/*** EPPAR0 - EPORT Pin Assignment Register.; 0x00130000 ***/
#define EPPAR0                        (*((volatile uint16 *)(&__IPSBAR[0x00130000UL])))
#define EPPAR0_EPPA10_BITMASK         (0x4U)
#define EPPAR0_EPPA11_BITMASK         (0x8U)
#define EPPAR0_EPPA20_BITMASK         (0x10U)
#define EPPAR0_EPPA21_BITMASK         (0x20U)
#define EPPAR0_EPPA30_BITMASK         (0x40U)
#define EPPAR0_EPPA31_BITMASK         (0x80U)
#define EPPAR0_EPPA40_BITMASK         (0x100U)
#define EPPAR0_EPPA41_BITMASK         (0x200U)
#define EPPAR0_EPPA50_BITMASK         (0x400U)
#define EPPAR0_EPPA51_BITMASK         (0x800U)
#define EPPAR0_EPPA60_BITMASK         (0x1000U)
#define EPPAR0_EPPA61_BITMASK         (0x2000U)
#define EPPAR0_EPPA70_BITMASK         (0x4000U)
#define EPPAR0_EPPA71_BITMASK         (0x8000U)
#define EPPAR0_EPPA1_GRPMASK          (0xCU)
#define EPPAR0_EPPA1_GRPPOS           (0x2U)
#define EPPAR0_EPPA2_GRPMASK          (0x30U)
#define EPPAR0_EPPA2_GRPPOS           (0x4U)
#define EPPAR0_EPPA3_GRPMASK          (0xC0U)
#define EPPAR0_EPPA3_GRPPOS           (0x6U)
#define EPPAR0_EPPA4_GRPMASK          (0x300U)
#define EPPAR0_EPPA4_GRPPOS           (0x8U)
#define EPPAR0_EPPA5_GRPMASK          (0xC00U)
#define EPPAR0_EPPA5_GRPPOS           (0xAU)
#define EPPAR0_EPPA6_GRPMASK          (0x3000U)
#define EPPAR0_EPPA6_GRPPOS           (0xCU)
#define EPPAR0_EPPA7_GRPMASK          (0xC000U)
#define EPPAR0_EPPA7_GRPPOS           (0xEU)

/*** EPDDR0 - EPORT Data Direction Register.; 0x00130002 ***/
#define EPDDR0                        (*((volatile uint8 *)(&__IPSBAR[0x00130002UL])))
#define EPDDR0_EPDD1_BITMASK          (0x2U)
#define EPDDR0_EPDD2_BITMASK          (0x4U)
#define EPDDR0_EPDD3_BITMASK          (0x8U)
#define EPDDR0_EPDD4_BITMASK          (0x10U)
#define EPDDR0_EPDD5_BITMASK          (0x20U)
#define EPDDR0_EPDD6_BITMASK          (0x40U)
#define EPDDR0_EPDD7_BITMASK          (0x80U)

/*** EPIER0 - Edge Port Interrupt Enable Register.; 0x00130003 ***/
#define EPIER0                        (*((volatile uint8 *)(&__IPSBAR[0x00130003UL])))
#define EPIER0_EPIE1_BITMASK          (0x2U)
#define EPIER0_EPIE2_BITMASK          (0x4U)
#define EPIER0_EPIE3_BITMASK          (0x8U)
#define EPIER0_EPIE4_BITMASK          (0x10U)
#define EPIER0_EPIE5_BITMASK          (0x20U)
#define EPIER0_EPIE6_BITMASK          (0x40U)
#define EPIER0_EPIE7_BITMASK          (0x80U)

/*** EPDR0 - EPORT Port Data Register.; 0x00130004 ***/
#define EPDR0                         (*((volatile uint8 *)(&__IPSBAR[0x00130004UL])))
#define EPDR0_EPD1_BITMASK            (0x2U)
#define EPDR0_EPD2_BITMASK            (0x4U)
#define EPDR0_EPD3_BITMASK            (0x8U)
#define EPDR0_EPD4_BITMASK            (0x10U)
#define EPDR0_EPD5_BITMASK            (0x20U)
#define EPDR0_EPD6_BITMASK            (0x40U)
#define EPDR0_EPD7_BITMASK            (0x80U)

/*** EPPDR0 - EPORT Port Pin Data Register.; 0x00130005 ***/
#define EPPDR0                        (*((volatile uint8 *)(&__IPSBAR[0x00130005UL])))
#define EPPDR0_EPPD1_BITMASK          (0x2U)
#define EPPDR0_EPPD2_BITMASK          (0x4U)
#define EPPDR0_EPPD3_BITMASK          (0x8U)
#define EPPDR0_EPPD4_BITMASK          (0x10U)
#define EPPDR0_EPPD5_BITMASK          (0x20U)
#define EPPDR0_EPPD6_BITMASK          (0x40U)
#define EPPDR0_EPPD7_BITMASK          (0x80U)

/*** EPFR0 - Edge Port Flag Register.; 0x00130006 ***/
#define EPFR0                         (*((volatile uint8 *)(&__IPSBAR[0x00130006UL])))
#define EPFR0_EPF1_BITMASK            (0x2U)
#define EPFR0_EPF2_BITMASK            (0x4U)
#define EPFR0_EPF3_BITMASK            (0x8U)
#define EPFR0_EPF4_BITMASK            (0x10U)
#define EPFR0_EPF5_BITMASK            (0x20U)
#define EPFR0_EPF6_BITMASK            (0x40U)
#define EPFR0_EPF7_BITMASK            (0x80U)


/******************************************
*** Peripheral EPORT1
*******************************************/

/*** EPPAR1 - EPORT Pin Assignment Register.; 0x00140000 ***/
#define EPPAR1                        (*((volatile uint16 *)(&__IPSBAR[0x00140000UL])))
#define EPPAR1_EPPA80_BITMASK         (0x1U)
#define EPPAR1_EPPA81_BITMASK         (0x2U)
#define EPPAR1_EPPA90_BITMASK         (0x4U)
#define EPPAR1_EPPA91_BITMASK         (0x8U)
#define EPPAR1_EPPA100_BITMASK        (0x10U)
#define EPPAR1_EPPA101_BITMASK        (0x20U)
#define EPPAR1_EPPA110_BITMASK        (0x40U)
#define EPPAR1_EPPA111_BITMASK        (0x80U)
#define EPPAR1_EPPA120_BITMASK        (0x100U)
#define EPPAR1_EPPA121_BITMASK        (0x200U)
#define EPPAR1_EPPA130_BITMASK        (0x400U)
#define EPPAR1_EPPA131_BITMASK        (0x800U)
#define EPPAR1_EPPA140_BITMASK        (0x1000U)
#define EPPAR1_EPPA141_BITMASK        (0x2000U)
#define EPPAR1_EPPA150_BITMASK        (0x4000U)
#define EPPAR1_EPPA151_BITMASK        (0x8000U)
#define EPPAR1_EPPA8_GRPMASK          (0x3U)
#define EPPAR1_EPPA8_GRPPOS           (0U)
#define EPPAR1_EPPA9_GRPMASK          (0xCU)
#define EPPAR1_EPPA9_GRPPOS           (0x2U)
#define EPPAR1_EPPA10_GRPMASK         (0x30U)
#define EPPAR1_EPPA10_GRPPOS          (0x4U)
#define EPPAR1_EPPA11_GRPMASK         (0xC0U)
#define EPPAR1_EPPA11_GRPPOS          (0x6U)
#define EPPAR1_EPPA12_GRPMASK         (0x300U)
#define EPPAR1_EPPA12_GRPPOS          (0x8U)
#define EPPAR1_EPPA13_GRPMASK         (0xC00U)
#define EPPAR1_EPPA13_GRPPOS          (0xAU)
#define EPPAR1_EPPA14_GRPMASK         (0x3000U)
#define EPPAR1_EPPA14_GRPPOS          (0xCU)
#define EPPAR1_EPPA15_GRPMASK         (0xC000U)
#define EPPAR1_EPPA15_GRPPOS          (0xEU)

/*** EPDDR1 - EPORT Data Direction Register.; 0x00140002 ***/
#define EPDDR1                        (*((volatile uint8 *)(&__IPSBAR[0x00140002UL])))
#define EPDDR1_EPDD8_BITMASK          (0x1U)
#define EPDDR1_EPDD9_BITMASK          (0x2U)
#define EPDDR1_EPDD10_BITMASK         (0x4U)
#define EPDDR1_EPDD11_BITMASK         (0x8U)
#define EPDDR1_EPDD12_BITMASK         (0x10U)
#define EPDDR1_EPDD13_BITMASK         (0x20U)
#define EPDDR1_EPDD14_BITMASK         (0x40U)
#define EPDDR1_EPDD15_BITMASK         (0x80U)

/*** EPIER1 - Edge Port Interrupt Enable Register.; 0x00140003 ***/
#define EPIER1                        (*((volatile uint8 *)(&__IPSBAR[0x00140003UL])))
#define EPIER1_EPIE8_BITMASK          (0x1U)
#define EPIER1_EPIE9_BITMASK          (0x2U)
#define EPIER1_EPIE10_BITMASK         (0x4U)
#define EPIER1_EPIE11_BITMASK         (0x8U)
#define EPIER1_EPIE12_BITMASK         (0x10U)
#define EPIER1_EPIE13_BITMASK         (0x20U)
#define EPIER1_EPIE14_BITMASK         (0x40U)
#define EPIER1_EPIE15_BITMASK         (0x80U)

/*** EPDR1 - EPORT Port Data Register.; 0x00140004 ***/
#define EPDR1                         (*((volatile uint8 *)(&__IPSBAR[0x00140004UL])))
#define EPDR1_EPD8_BITMASK            (0x1U)
#define EPDR1_EPD9_BITMASK            (0x2U)
#define EPDR1_EPD10_BITMASK           (0x4U)
#define EPDR1_EPD11_BITMASK           (0x8U)
#define EPDR1_EPD12_BITMASK           (0x10U)
#define EPDR1_EPD13_BITMASK           (0x20U)
#define EPDR1_EPD14_BITMASK           (0x40U)
#define EPDR1_EPD15_BITMASK           (0x80U)

/*** EPPDR1 - EPORT Port Pin Data Register.; 0x00140005 ***/
#define EPPDR1                        (*((volatile uint8 *)(&__IPSBAR[0x00140005UL])))
#define EPPDR1_EPPD8_BITMASK          (0x1U)
#define EPPDR1_EPPD9_BITMASK          (0x2U)
#define EPPDR1_EPPD10_BITMASK         (0x4U)
#define EPPDR1_EPPD11_BITMASK         (0x8U)
#define EPPDR1_EPPD12_BITMASK         (0x10U)
#define EPPDR1_EPPD13_BITMASK         (0x20U)
#define EPPDR1_EPPD14_BITMASK         (0x40U)
#define EPPDR1_EPPD15_BITMASK         (0x80U)

/*** EPFR1 - Edge Port Flag Register.; 0x00140006 ***/
#define EPFR1                         (*((volatile uint8 *)(&__IPSBAR[0x00140006UL])))
#define EPFR1_EPF8_BITMASK            (0x1U)
#define EPFR1_EPF9_BITMASK            (0x2U)
#define EPFR1_EPF10_BITMASK           (0x4U)
#define EPFR1_EPF11_BITMASK           (0x8U)
#define EPFR1_EPF12_BITMASK           (0x10U)
#define EPFR1_EPF13_BITMASK           (0x20U)
#define EPFR1_EPF14_BITMASK           (0x40U)
#define EPFR1_EPF15_BITMASK           (0x80U)


/******************************************
*** Peripheral PIT0
*******************************************/

/*** PCSR0 - PIT0 Control and Status Register.; 0x00150000 ***/
#define PCSR0                         (*((volatile uint16 *)(&__IPSBAR[0x00150000UL])))
#define PCSR0_EN_BITMASK              (0x1U)
#define PCSR0_RLD_BITMASK             (0x2U)
#define PCSR0_PIF_BITMASK             (0x4U)
#define PCSR0_PIE_BITMASK             (0x8U)
#define PCSR0_OVW_BITMASK             (0x10U)
#define PCSR0_DBG_BITMASK             (0x20U)
#define PCSR0_DOZE_BITMASK            (0x40U)
#define PCSR0_PRE0_BITMASK            (0x100U)
#define PCSR0_PRE1_BITMASK            (0x200U)
#define PCSR0_PRE2_BITMASK            (0x400U)
#define PCSR0_PRE3_BITMASK            (0x800U)
#define PCSR0_PRE_GRPMASK             (0xF00U)
#define PCSR0_PRE_GRPPOS              (0x8U)

/*** PMR0 - PIT0 Modulus Register.; 0x00150002 ***/
#define PMR0                          (*((volatile uint16 *)(&__IPSBAR[0x00150002UL])))
#define PMR0_PM0_BITMASK              (0x1U)
#define PMR0_PM1_BITMASK              (0x2U)
#define PMR0_PM2_BITMASK              (0x4U)
#define PMR0_PM3_BITMASK              (0x8U)
#define PMR0_PM4_BITMASK              (0x10U)
#define PMR0_PM5_BITMASK              (0x20U)
#define PMR0_PM6_BITMASK              (0x40U)
#define PMR0_PM7_BITMASK              (0x80U)
#define PMR0_PM8_BITMASK              (0x100U)
#define PMR0_PM9_BITMASK              (0x200U)
#define PMR0_PM10_BITMASK             (0x400U)
#define PMR0_PM11_BITMASK             (0x800U)
#define PMR0_PM12_BITMASK             (0x1000U)
#define PMR0_PM13_BITMASK             (0x2000U)
#define PMR0_PM14_BITMASK             (0x4000U)
#define PMR0_PM15_BITMASK             (0x8000U)
#define PMR0_PM_GRPMASK               (0xFFFFU)
#define PMR0_PM_GRPPOS                (0U)

/*** PCNTR0 - PIT0 Count Register.; 0x00150004 ***/
#define PCNTR0                        (*((volatile uint16 *)(&__IPSBAR[0x00150004UL])))
#define PCNTR0_PC0_BITMASK            (0x1U)
#define PCNTR0_PC1_BITMASK            (0x2U)
#define PCNTR0_PC2_BITMASK            (0x4U)
#define PCNTR0_PC3_BITMASK            (0x8U)
#define PCNTR0_PC4_BITMASK            (0x10U)
#define PCNTR0_PC5_BITMASK            (0x20U)
#define PCNTR0_PC6_BITMASK            (0x40U)
#define PCNTR0_PC7_BITMASK            (0x80U)
#define PCNTR0_PC8_BITMASK            (0x100U)
#define PCNTR0_PC9_BITMASK            (0x200U)
#define PCNTR0_PC10_BITMASK           (0x400U)
#define PCNTR0_PC11_BITMASK           (0x800U)
#define PCNTR0_PC12_BITMASK           (0x1000U)
#define PCNTR0_PC13_BITMASK           (0x2000U)
#define PCNTR0_PC14_BITMASK           (0x4000U)
#define PCNTR0_PC15_BITMASK           (0x8000U)
#define PCNTR0_PC_GRPMASK             (0xFFFFU)
#define PCNTR0_PC_GRPPOS              (0U)


/******************************************
*** Peripheral PIT1
*******************************************/

/*** PCSR1 - PIT1 Control and Status Register.; 0x00160000 ***/
#define PCSR1                         (*((volatile uint16 *)(&__IPSBAR[0x00160000UL])))
#define PCSR1_EN_BITMASK              (0x1U)
#define PCSR1_RLD_BITMASK             (0x2U)
#define PCSR1_PIF_BITMASK             (0x4U)
#define PCSR1_PIE_BITMASK             (0x8U)
#define PCSR1_OVW_BITMASK             (0x10U)
#define PCSR1_DBG_BITMASK             (0x20U)
#define PCSR1_DOZE_BITMASK            (0x40U)
#define PCSR1_PRE0_BITMASK            (0x100U)
#define PCSR1_PRE1_BITMASK            (0x200U)
#define PCSR1_PRE2_BITMASK            (0x400U)
#define PCSR1_PRE3_BITMASK            (0x800U)
#define PCSR1_PRE_GRPMASK             (0xF00U)
#define PCSR1_PRE_GRPPOS              (0x8U)

/*** PMR1 - PIT1 Modulus Register.; 0x00160002 ***/
#define PMR1                          (*((volatile uint16 *)(&__IPSBAR[0x00160002UL])))
#define PMR1_PM0_BITMASK              (0x1U)
#define PMR1_PM1_BITMASK              (0x2U)
#define PMR1_PM2_BITMASK              (0x4U)
#define PMR1_PM3_BITMASK              (0x8U)
#define PMR1_PM4_BITMASK              (0x10U)
#define PMR1_PM5_BITMASK              (0x20U)
#define PMR1_PM6_BITMASK              (0x40U)
#define PMR1_PM7_BITMASK              (0x80U)
#define PMR1_PM8_BITMASK              (0x100U)
#define PMR1_PM9_BITMASK              (0x200U)
#define PMR1_PM10_BITMASK             (0x400U)
#define PMR1_PM11_BITMASK             (0x800U)
#define PMR1_PM12_BITMASK             (0x1000U)
#define PMR1_PM13_BITMASK             (0x2000U)
#define PMR1_PM14_BITMASK             (0x4000U)
#define PMR1_PM15_BITMASK             (0x8000U)
#define PMR1_PM_GRPMASK               (0xFFFFU)
#define PMR1_PM_GRPPOS                (0U)

/*** PCNTR1 - PIT1 Count Register.; 0x00160004 ***/
#define PCNTR1                        (*((volatile uint16 *)(&__IPSBAR[0x00160004UL])))
#define PCNTR1_PC0_BITMASK            (0x1U)
#define PCNTR1_PC1_BITMASK            (0x2U)
#define PCNTR1_PC2_BITMASK            (0x4U)
#define PCNTR1_PC3_BITMASK            (0x8U)
#define PCNTR1_PC4_BITMASK            (0x10U)
#define PCNTR1_PC5_BITMASK            (0x20U)
#define PCNTR1_PC6_BITMASK            (0x40U)
#define PCNTR1_PC7_BITMASK            (0x80U)
#define PCNTR1_PC8_BITMASK            (0x100U)
#define PCNTR1_PC9_BITMASK            (0x200U)
#define PCNTR1_PC10_BITMASK           (0x400U)
#define PCNTR1_PC11_BITMASK           (0x800U)
#define PCNTR1_PC12_BITMASK           (0x1000U)
#define PCNTR1_PC13_BITMASK           (0x2000U)
#define PCNTR1_PC14_BITMASK           (0x4000U)
#define PCNTR1_PC15_BITMASK           (0x8000U)
#define PCNTR1_PC_GRPMASK             (0xFFFFU)
#define PCNTR1_PC_GRPPOS              (0U)


/******************************************
*** Peripheral ADC
*******************************************/

/*** CTRL1 - Control 1 Register.; 0x00190000 ***/
#define CTRL1                         (*((volatile uint16 *)(&__IPSBAR[0x00190000UL])))
#define CTRL1_SMODE0_BITMASK          (0x1U)
#define CTRL1_SMODE1_BITMASK          (0x2U)
#define CTRL1_SMODE2_BITMASK          (0x4U)
#define CTRL1_CHNCFG0_BITMASK         (0x10U)
#define CTRL1_CHNCFG1_BITMASK         (0x20U)
#define CTRL1_CHNCFG2_BITMASK         (0x40U)
#define CTRL1_CHNCFG3_BITMASK         (0x80U)
#define CTRL1_HLMTIE_BITMASK          (0x100U)
#define CTRL1_LLMTIE_BITMASK          (0x200U)
#define CTRL1_ZCIE_BITMASK            (0x400U)
#define CTRL1_EOSIE0_BITMASK          (0x800U)
#define CTRL1_SYNC0_BITMASK           (0x1000U)
#define CTRL1_START0_BITMASK          (0x2000U)
#define CTRL1_STOP0_BITMASK           (0x4000U)
#define CTRL1_SMODE_GRPMASK           (0x7U)
#define CTRL1_SMODE_GRPPOS            (0U)
#define CTRL1_CHNCFG_GRPMASK          (0xF0U)
#define CTRL1_CHNCFG_GRPPOS           (0x4U)

/*** CTRL2 - Control 2 Register.; 0x00190002 ***/
#define CTRL2                         (*((volatile uint16 *)(&__IPSBAR[0x00190002UL])))
#define CTRL2_DIV0_BITMASK            (0x1U)
#define CTRL2_DIV1_BITMASK            (0x2U)
#define CTRL2_DIV2_BITMASK            (0x4U)
#define CTRL2_DIV3_BITMASK            (0x8U)
#define CTRL2_DIV4_BITMASK            (0x10U)
#define CTRL2_SIMULT_BITMASK          (0x20U)
#define CTRL2_EOSIE1_BITMASK          (0x800U)
#define CTRL2_SYNC1_BITMASK           (0x1000U)
#define CTRL2_START1_BITMASK          (0x2000U)
#define CTRL2_STOP1_BITMASK           (0x4000U)
#define CTRL2_DIV_GRPMASK             (0x1FU)
#define CTRL2_DIV_GRPPOS              (0U)

/*** ADZCC - Zero Crossing Control Register.; 0x00190004 ***/
#define ADZCC                         (*((volatile uint16 *)(&__IPSBAR[0x00190004UL])))
#define ADZCC_ZCE00_BITMASK           (0x1U)
#define ADZCC_ZCE01_BITMASK           (0x2U)
#define ADZCC_ZCE10_BITMASK           (0x4U)
#define ADZCC_ZCE11_BITMASK           (0x8U)
#define ADZCC_ZCE20_BITMASK           (0x10U)
#define ADZCC_ZCE21_BITMASK           (0x20U)
#define ADZCC_ZCE30_BITMASK           (0x40U)
#define ADZCC_ZCE31_BITMASK           (0x80U)
#define ADZCC_ZCE40_BITMASK           (0x100U)
#define ADZCC_ZCE41_BITMASK           (0x200U)
#define ADZCC_ZCE50_BITMASK           (0x400U)
#define ADZCC_ZCE51_BITMASK           (0x800U)
#define ADZCC_ZCE60_BITMASK           (0x1000U)
#define ADZCC_ZCE61_BITMASK           (0x2000U)
#define ADZCC_ZCE70_BITMASK           (0x4000U)
#define ADZCC_ZCE71_BITMASK           (0x8000U)
#define ADZCC_ZCE0_GRPMASK            (0x3U)
#define ADZCC_ZCE0_GRPPOS             (0U)
#define ADZCC_ZCE1_GRPMASK            (0xCU)
#define ADZCC_ZCE1_GRPPOS             (0x2U)
#define ADZCC_ZCE2_GRPMASK            (0x30U)
#define ADZCC_ZCE2_GRPPOS             (0x4U)
#define ADZCC_ZCE3_GRPMASK            (0xC0U)
#define ADZCC_ZCE3_GRPPOS             (0x6U)
#define ADZCC_ZCE4_GRPMASK            (0x300U)
#define ADZCC_ZCE4_GRPPOS             (0x8U)
#define ADZCC_ZCE5_GRPMASK            (0xC00U)
#define ADZCC_ZCE5_GRPPOS             (0xAU)
#define ADZCC_ZCE6_GRPMASK            (0x3000U)
#define ADZCC_ZCE6_GRPPOS             (0xCU)
#define ADZCC_ZCE7_GRPMASK            (0xC000U)
#define ADZCC_ZCE7_GRPPOS             (0xEU)

/*** ADLST1 - Channel List 1 Register.; 0x00190006 ***/
#define ADLST1                        (*((volatile uint16 *)(&__IPSBAR[0x00190006UL])))
#define ADLST1_SAMPLE00_BITMASK       (0x1U)
#define ADLST1_SAMPLE01_BITMASK       (0x2U)
#define ADLST1_SAMPLE02_BITMASK       (0x4U)
#define ADLST1_SAMPLE10_BITMASK       (0x10U)
#define ADLST1_SAMPLE11_BITMASK       (0x20U)
#define ADLST1_SAMPLE12_BITMASK       (0x40U)
#define ADLST1_SAMPLE20_BITMASK       (0x100U)
#define ADLST1_SAMPLE21_BITMASK       (0x200U)
#define ADLST1_SAMPLE22_BITMASK       (0x400U)
#define ADLST1_SAMPLE30_BITMASK       (0x1000U)
#define ADLST1_SAMPLE31_BITMASK       (0x2000U)
#define ADLST1_SAMPLE32_BITMASK       (0x4000U)
#define ADLST1_SAMPLE0_GRPMASK        (0x7U)
#define ADLST1_SAMPLE0_GRPPOS         (0U)
#define ADLST1_SAMPLE1_GRPMASK        (0x70U)
#define ADLST1_SAMPLE1_GRPPOS         (0x4U)
#define ADLST1_SAMPLE2_GRPMASK        (0x700U)
#define ADLST1_SAMPLE2_GRPPOS         (0x8U)
#define ADLST1_SAMPLE3_GRPMASK        (0x7000U)
#define ADLST1_SAMPLE3_GRPPOS         (0xCU)

/*** ADLST2 - Channel List 2 Register.; 0x00190008 ***/
#define ADLST2                        (*((volatile uint16 *)(&__IPSBAR[0x00190008UL])))
#define ADLST2_SAMPLE40_BITMASK       (0x1U)
#define ADLST2_SAMPLE41_BITMASK       (0x2U)
#define ADLST2_SAMPLE42_BITMASK       (0x4U)
#define ADLST2_SAMPLE50_BITMASK       (0x10U)
#define ADLST2_SAMPLE51_BITMASK       (0x20U)
#define ADLST2_SAMPLE52_BITMASK       (0x40U)
#define ADLST2_SAMPLE60_BITMASK       (0x100U)
#define ADLST2_SAMPLE61_BITMASK       (0x200U)
#define ADLST2_SAMPLE62_BITMASK       (0x400U)
#define ADLST2_SAMPLE70_BITMASK       (0x1000U)
#define ADLST2_SAMPLE71_BITMASK       (0x2000U)
#define ADLST2_SAMPLE72_BITMASK       (0x4000U)
#define ADLST2_SAMPLE4_GRPMASK        (0x7U)
#define ADLST2_SAMPLE4_GRPPOS         (0U)
#define ADLST2_SAMPLE5_GRPMASK        (0x70U)
#define ADLST2_SAMPLE5_GRPPOS         (0x4U)
#define ADLST2_SAMPLE6_GRPMASK        (0x700U)
#define ADLST2_SAMPLE6_GRPPOS         (0x8U)
#define ADLST2_SAMPLE7_GRPMASK        (0x7000U)
#define ADLST2_SAMPLE7_GRPPOS         (0xCU)

/*** ADSDIS - Sample Disable Register.; 0x0019000A ***/
#define ADSDIS                        (*((volatile uint16 *)(&__IPSBAR[0x0019000AUL])))
#define ADSDIS_DS0_BITMASK            (0x1U)
#define ADSDIS_DS1_BITMASK            (0x2U)
#define ADSDIS_DS2_BITMASK            (0x4U)
#define ADSDIS_DS3_BITMASK            (0x8U)
#define ADSDIS_DS4_BITMASK            (0x10U)
#define ADSDIS_DS5_BITMASK            (0x20U)
#define ADSDIS_DS6_BITMASK            (0x40U)
#define ADSDIS_DS7_BITMASK            (0x80U)

/*** ADSTAT - Status Register.; 0x0019000C ***/
#define ADSTAT                        (*((volatile uint16 *)(&__IPSBAR[0x0019000CUL])))
#define ADSTAT_RDY0_BITMASK           (0x1U)
#define ADSTAT_RDY1_BITMASK           (0x2U)
#define ADSTAT_RDY2_BITMASK           (0x4U)
#define ADSTAT_RDY3_BITMASK           (0x8U)
#define ADSTAT_RDY4_BITMASK           (0x10U)
#define ADSTAT_RDY5_BITMASK           (0x20U)
#define ADSTAT_RDY6_BITMASK           (0x40U)
#define ADSTAT_RDY7_BITMASK           (0x80U)
#define ADSTAT_HLMTI_BITMASK          (0x100U)
#define ADSTAT_LLMTI_BITMASK          (0x200U)
#define ADSTAT_ZCI_BITMASK            (0x400U)
#define ADSTAT_EOSI0_BITMASK          (0x800U)
#define ADSTAT_EOSI1_BITMASK          (0x1000U)
#define ADSTAT_CIP1_BITMASK           (0x4000U)
#define ADSTAT_CIP0_BITMASK           (0x8000U)

/*** ADLSTAT - Limit Status Register.; 0x0019000E ***/
#define ADLSTAT                       (*((volatile uint16 *)(&__IPSBAR[0x0019000EUL])))
#define ADLSTAT_LLS0_BITMASK          (0x1U)
#define ADLSTAT_LLS1_BITMASK          (0x2U)
#define ADLSTAT_LLS2_BITMASK          (0x4U)
#define ADLSTAT_LLS3_BITMASK          (0x8U)
#define ADLSTAT_LLS4_BITMASK          (0x10U)
#define ADLSTAT_LLS5_BITMASK          (0x20U)
#define ADLSTAT_LLS6_BITMASK          (0x40U)
#define ADLSTAT_LLS7_BITMASK          (0x80U)
#define ADLSTAT_HLS0_BITMASK          (0x100U)
#define ADLSTAT_HLS1_BITMASK          (0x200U)
#define ADLSTAT_HLS2_BITMASK          (0x400U)
#define ADLSTAT_HLS3_BITMASK          (0x800U)
#define ADLSTAT_HLS4_BITMASK          (0x1000U)
#define ADLSTAT_HLS5_BITMASK          (0x2000U)
#define ADLSTAT_HLS6_BITMASK          (0x4000U)
#define ADLSTAT_HLS7_BITMASK          (0x8000U)

/*** ADZCSTAT - Zero Crossing Status Register.; 0x00190010 ***/
#define ADZCSTAT                      (*((volatile uint16 *)(&__IPSBAR[0x00190010UL])))
#define ADZCSTAT_ZCS0_BITMASK         (0x1U)
#define ADZCSTAT_ZCS1_BITMASK         (0x2U)
#define ADZCSTAT_ZCS2_BITMASK         (0x4U)
#define ADZCSTAT_ZCS3_BITMASK         (0x8U)
#define ADZCSTAT_ZCS4_BITMASK         (0x10U)
#define ADZCSTAT_ZCS5_BITMASK         (0x20U)
#define ADZCSTAT_ZCS6_BITMASK         (0x40U)
#define ADZCSTAT_ZCS7_BITMASK         (0x80U)

/*** ADRSLT0 - Result Register 0.; 0x00190012 ***/
#define ADRSLT0                       (*((volatile uint16 *)(&__IPSBAR[0x00190012UL])))
#define ADRSLT0_RSLT0_BITMASK         (0x8U)
#define ADRSLT0_RSLT1_BITMASK         (0x10U)
#define ADRSLT0_RSLT2_BITMASK         (0x20U)
#define ADRSLT0_RSLT3_BITMASK         (0x40U)
#define ADRSLT0_RSLT4_BITMASK         (0x80U)
#define ADRSLT0_RSLT5_BITMASK         (0x100U)
#define ADRSLT0_RSLT6_BITMASK         (0x200U)
#define ADRSLT0_RSLT7_BITMASK         (0x400U)
#define ADRSLT0_RSLT8_BITMASK         (0x800U)
#define ADRSLT0_RSLT9_BITMASK         (0x1000U)
#define ADRSLT0_RSLT10_BITMASK        (0x2000U)
#define ADRSLT0_RSLT11_BITMASK        (0x4000U)
#define ADRSLT0_SEXT_BITMASK          (0x8000U)
#define ADRSLT0_RSLT_GRPMASK          (0x7FF8U)
#define ADRSLT0_RSLT_GRPPOS           (0x3U)

/*** ADRSLT1 - Result Register 1.; 0x00190014 ***/
#define ADRSLT1                       (*((volatile uint16 *)(&__IPSBAR[0x00190014UL])))
#define ADRSLT1_RSLT0_BITMASK         (0x8U)
#define ADRSLT1_RSLT1_BITMASK         (0x10U)
#define ADRSLT1_RSLT2_BITMASK         (0x20U)
#define ADRSLT1_RSLT3_BITMASK         (0x40U)
#define ADRSLT1_RSLT4_BITMASK         (0x80U)
#define ADRSLT1_RSLT5_BITMASK         (0x100U)
#define ADRSLT1_RSLT6_BITMASK         (0x200U)
#define ADRSLT1_RSLT7_BITMASK         (0x400U)
#define ADRSLT1_RSLT8_BITMASK         (0x800U)
#define ADRSLT1_RSLT9_BITMASK         (0x1000U)
#define ADRSLT1_RSLT10_BITMASK        (0x2000U)
#define ADRSLT1_RSLT11_BITMASK        (0x4000U)
#define ADRSLT1_SEXT_BITMASK          (0x8000U)
#define ADRSLT1_RSLT_GRPMASK          (0x7FF8U)
#define ADRSLT1_RSLT_GRPPOS           (0x3U)

/*** ADRSLT2 - Result Register 2.; 0x00190016 ***/
#define ADRSLT2                       (*((volatile uint16 *)(&__IPSBAR[0x00190016UL])))
#define ADRSLT2_RSLT0_BITMASK         (0x8U)
#define ADRSLT2_RSLT1_BITMASK         (0x10U)
#define ADRSLT2_RSLT2_BITMASK         (0x20U)
#define ADRSLT2_RSLT3_BITMASK         (0x40U)
#define ADRSLT2_RSLT4_BITMASK         (0x80U)
#define ADRSLT2_RSLT5_BITMASK         (0x100U)
#define ADRSLT2_RSLT6_BITMASK         (0x200U)
#define ADRSLT2_RSLT7_BITMASK         (0x400U)
#define ADRSLT2_RSLT8_BITMASK         (0x800U)
#define ADRSLT2_RSLT9_BITMASK         (0x1000U)
#define ADRSLT2_RSLT10_BITMASK        (0x2000U)
#define ADRSLT2_RSLT11_BITMASK        (0x4000U)
#define ADRSLT2_SEXT_BITMASK          (0x8000U)
#define ADRSLT2_RSLT_GRPMASK          (0x7FF8U)
#define ADRSLT2_RSLT_GRPPOS           (0x3U)

/*** ADRSLT3 - Result Register 3.; 0x00190018 ***/
#define ADRSLT3                       (*((volatile uint16 *)(&__IPSBAR[0x00190018UL])))
#define ADRSLT3_RSLT0_BITMASK         (0x8U)
#define ADRSLT3_RSLT1_BITMASK         (0x10U)
#define ADRSLT3_RSLT2_BITMASK         (0x20U)
#define ADRSLT3_RSLT3_BITMASK         (0x40U)
#define ADRSLT3_RSLT4_BITMASK         (0x80U)
#define ADRSLT3_RSLT5_BITMASK         (0x100U)
#define ADRSLT3_RSLT6_BITMASK         (0x200U)
#define ADRSLT3_RSLT7_BITMASK         (0x400U)
#define ADRSLT3_RSLT8_BITMASK         (0x800U)
#define ADRSLT3_RSLT9_BITMASK         (0x1000U)
#define ADRSLT3_RSLT10_BITMASK        (0x2000U)
#define ADRSLT3_RSLT11_BITMASK        (0x4000U)
#define ADRSLT3_SEXT_BITMASK          (0x8000U)
#define ADRSLT3_RSLT_GRPMASK          (0x7FF8U)
#define ADRSLT3_RSLT_GRPPOS           (0x3U)

/*** ADRSLT4 - Result Register 4.; 0x0019001A ***/
#define ADRSLT4                       (*((volatile uint16 *)(&__IPSBAR[0x0019001AUL])))
#define ADRSLT4_RSLT0_BITMASK         (0x8U)
#define ADRSLT4_RSLT1_BITMASK         (0x10U)
#define ADRSLT4_RSLT2_BITMASK         (0x20U)
#define ADRSLT4_RSLT3_BITMASK         (0x40U)
#define ADRSLT4_RSLT4_BITMASK         (0x80U)
#define ADRSLT4_RSLT5_BITMASK         (0x100U)
#define ADRSLT4_RSLT6_BITMASK         (0x200U)
#define ADRSLT4_RSLT7_BITMASK         (0x400U)
#define ADRSLT4_RSLT8_BITMASK         (0x800U)
#define ADRSLT4_RSLT9_BITMASK         (0x1000U)
#define ADRSLT4_RSLT10_BITMASK        (0x2000U)
#define ADRSLT4_RSLT11_BITMASK        (0x4000U)
#define ADRSLT4_SEXT_BITMASK          (0x8000U)
#define ADRSLT4_RSLT_GRPMASK          (0x7FF8U)
#define ADRSLT4_RSLT_GRPPOS           (0x3U)

/*** ADRSLT5 - Result Register 5.; 0x0019001C ***/
#define ADRSLT5                       (*((volatile uint16 *)(&__IPSBAR[0x0019001CUL])))
#define ADRSLT5_RSLT0_BITMASK         (0x8U)
#define ADRSLT5_RSLT1_BITMASK         (0x10U)
#define ADRSLT5_RSLT2_BITMASK         (0x20U)
#define ADRSLT5_RSLT3_BITMASK         (0x40U)
#define ADRSLT5_RSLT4_BITMASK         (0x80U)
#define ADRSLT5_RSLT5_BITMASK         (0x100U)
#define ADRSLT5_RSLT6_BITMASK         (0x200U)
#define ADRSLT5_RSLT7_BITMASK         (0x400U)
#define ADRSLT5_RSLT8_BITMASK         (0x800U)
#define ADRSLT5_RSLT9_BITMASK         (0x1000U)
#define ADRSLT5_RSLT10_BITMASK        (0x2000U)
#define ADRSLT5_RSLT11_BITMASK        (0x4000U)
#define ADRSLT5_SEXT_BITMASK          (0x8000U)
#define ADRSLT5_RSLT_GRPMASK          (0x7FF8U)
#define ADRSLT5_RSLT_GRPPOS           (0x3U)

/*** ADRSLT6 - Result Register 6.; 0x0019001E ***/
#define ADRSLT6                       (*((volatile uint16 *)(&__IPSBAR[0x0019001EUL])))
#define ADRSLT6_RSLT0_BITMASK         (0x8U)
#define ADRSLT6_RSLT1_BITMASK         (0x10U)
#define ADRSLT6_RSLT2_BITMASK         (0x20U)
#define ADRSLT6_RSLT3_BITMASK         (0x40U)
#define ADRSLT6_RSLT4_BITMASK         (0x80U)
#define ADRSLT6_RSLT5_BITMASK         (0x100U)
#define ADRSLT6_RSLT6_BITMASK         (0x200U)
#define ADRSLT6_RSLT7_BITMASK         (0x400U)
#define ADRSLT6_RSLT8_BITMASK         (0x800U)
#define ADRSLT6_RSLT9_BITMASK         (0x1000U)
#define ADRSLT6_RSLT10_BITMASK        (0x2000U)
#define ADRSLT6_RSLT11_BITMASK        (0x4000U)
#define ADRSLT6_SEXT_BITMASK          (0x8000U)
#define ADRSLT6_RSLT_GRPMASK          (0x7FF8U)
#define ADRSLT6_RSLT_GRPPOS           (0x3U)

/*** ADRSLT7 - Result Register 7.; 0x00190020 ***/
#define ADRSLT7                       (*((volatile uint16 *)(&__IPSBAR[0x00190020UL])))
#define ADRSLT7_RSLT0_BITMASK         (0x8U)
#define ADRSLT7_RSLT1_BITMASK         (0x10U)
#define ADRSLT7_RSLT2_BITMASK         (0x20U)
#define ADRSLT7_RSLT3_BITMASK         (0x40U)
#define ADRSLT7_RSLT4_BITMASK         (0x80U)
#define ADRSLT7_RSLT5_BITMASK         (0x100U)
#define ADRSLT7_RSLT6_BITMASK         (0x200U)
#define ADRSLT7_RSLT7_BITMASK         (0x400U)
#define ADRSLT7_RSLT8_BITMASK         (0x800U)
#define ADRSLT7_RSLT9_BITMASK         (0x1000U)
#define ADRSLT7_RSLT10_BITMASK        (0x2000U)
#define ADRSLT7_RSLT11_BITMASK        (0x4000U)
#define ADRSLT7_SEXT_BITMASK          (0x8000U)
#define ADRSLT7_RSLT_GRPMASK          (0x7FF8U)
#define ADRSLT7_RSLT_GRPPOS           (0x3U)

/*** ADLLMT0 - Low Limit Register 0.; 0x00190022 ***/
#define ADLLMT0                       (*((volatile uint16 *)(&__IPSBAR[0x00190022UL])))
#define ADLLMT0_LLMT0_BITMASK         (0x8U)
#define ADLLMT0_LLMT1_BITMASK         (0x10U)
#define ADLLMT0_LLMT2_BITMASK         (0x20U)
#define ADLLMT0_LLMT3_BITMASK         (0x40U)
#define ADLLMT0_LLMT4_BITMASK         (0x80U)
#define ADLLMT0_LLMT5_BITMASK         (0x100U)
#define ADLLMT0_LLMT6_BITMASK         (0x200U)
#define ADLLMT0_LLMT7_BITMASK         (0x400U)
#define ADLLMT0_LLMT8_BITMASK         (0x800U)
#define ADLLMT0_LLMT9_BITMASK         (0x1000U)
#define ADLLMT0_LLMT10_BITMASK        (0x2000U)
#define ADLLMT0_LLMT11_BITMASK        (0x4000U)
#define ADLLMT0_LLMT_GRPMASK          (0x7FF8U)
#define ADLLMT0_LLMT_GRPPOS           (0x3U)

/*** ADLLMT1 - Low Limit Register 1.; 0x00190024 ***/
#define ADLLMT1                       (*((volatile uint16 *)(&__IPSBAR[0x00190024UL])))
#define ADLLMT1_LLMT0_BITMASK         (0x8U)
#define ADLLMT1_LLMT1_BITMASK         (0x10U)
#define ADLLMT1_LLMT2_BITMASK         (0x20U)
#define ADLLMT1_LLMT3_BITMASK         (0x40U)
#define ADLLMT1_LLMT4_BITMASK         (0x80U)
#define ADLLMT1_LLMT5_BITMASK         (0x100U)
#define ADLLMT1_LLMT6_BITMASK         (0x200U)
#define ADLLMT1_LLMT7_BITMASK         (0x400U)
#define ADLLMT1_LLMT8_BITMASK         (0x800U)
#define ADLLMT1_LLMT9_BITMASK         (0x1000U)
#define ADLLMT1_LLMT10_BITMASK        (0x2000U)
#define ADLLMT1_LLMT11_BITMASK        (0x4000U)
#define ADLLMT1_LLMT_GRPMASK          (0x7FF8U)
#define ADLLMT1_LLMT_GRPPOS           (0x3U)

/*** ADLLMT2 - Low Limit Register 2.; 0x00190026 ***/
#define ADLLMT2                       (*((volatile uint16 *)(&__IPSBAR[0x00190026UL])))
#define ADLLMT2_LLMT0_BITMASK         (0x8U)
#define ADLLMT2_LLMT1_BITMASK         (0x10U)
#define ADLLMT2_LLMT2_BITMASK         (0x20U)
#define ADLLMT2_LLMT3_BITMASK         (0x40U)
#define ADLLMT2_LLMT4_BITMASK         (0x80U)
#define ADLLMT2_LLMT5_BITMASK         (0x100U)
#define ADLLMT2_LLMT6_BITMASK         (0x200U)
#define ADLLMT2_LLMT7_BITMASK         (0x400U)
#define ADLLMT2_LLMT8_BITMASK         (0x800U)
#define ADLLMT2_LLMT9_BITMASK         (0x1000U)
#define ADLLMT2_LLMT10_BITMASK        (0x2000U)
#define ADLLMT2_LLMT11_BITMASK        (0x4000U)
#define ADLLMT2_LLMT_GRPMASK          (0x7FF8U)
#define ADLLMT2_LLMT_GRPPOS           (0x3U)

/*** ADLLMT3 - Low Limit Register 3.; 0x00190028 ***/
#define ADLLMT3                       (*((volatile uint16 *)(&__IPSBAR[0x00190028UL])))
#define ADLLMT3_LLMT0_BITMASK         (0x8U)
#define ADLLMT3_LLMT1_BITMASK         (0x10U)
#define ADLLMT3_LLMT2_BITMASK         (0x20U)
#define ADLLMT3_LLMT3_BITMASK         (0x40U)
#define ADLLMT3_LLMT4_BITMASK         (0x80U)
#define ADLLMT3_LLMT5_BITMASK         (0x100U)
#define ADLLMT3_LLMT6_BITMASK         (0x200U)
#define ADLLMT3_LLMT7_BITMASK         (0x400U)
#define ADLLMT3_LLMT8_BITMASK         (0x800U)
#define ADLLMT3_LLMT9_BITMASK         (0x1000U)
#define ADLLMT3_LLMT10_BITMASK        (0x2000U)
#define ADLLMT3_LLMT11_BITMASK        (0x4000U)
#define ADLLMT3_LLMT_GRPMASK          (0x7FF8U)
#define ADLLMT3_LLMT_GRPPOS           (0x3U)

/*** ADLLMT4 - Low Limit Register 4.; 0x0019002A ***/
#define ADLLMT4                       (*((volatile uint16 *)(&__IPSBAR[0x0019002AUL])))
#define ADLLMT4_LLMT0_BITMASK         (0x8U)
#define ADLLMT4_LLMT1_BITMASK         (0x10U)
#define ADLLMT4_LLMT2_BITMASK         (0x20U)
#define ADLLMT4_LLMT3_BITMASK         (0x40U)
#define ADLLMT4_LLMT4_BITMASK         (0x80U)
#define ADLLMT4_LLMT5_BITMASK         (0x100U)
#define ADLLMT4_LLMT6_BITMASK         (0x200U)
#define ADLLMT4_LLMT7_BITMASK         (0x400U)
#define ADLLMT4_LLMT8_BITMASK         (0x800U)
#define ADLLMT4_LLMT9_BITMASK         (0x1000U)
#define ADLLMT4_LLMT10_BITMASK        (0x2000U)
#define ADLLMT4_LLMT11_BITMASK        (0x4000U)
#define ADLLMT4_LLMT_GRPMASK          (0x7FF8U)
#define ADLLMT4_LLMT_GRPPOS           (0x3U)

/*** ADLLMT5 - Low Limit Register 5.; 0x0019002C ***/
#define ADLLMT5                       (*((volatile uint16 *)(&__IPSBAR[0x0019002CUL])))
#define ADLLMT5_LLMT0_BITMASK         (0x8U)
#define ADLLMT5_LLMT1_BITMASK         (0x10U)
#define ADLLMT5_LLMT2_BITMASK         (0x20U)
#define ADLLMT5_LLMT3_BITMASK         (0x40U)
#define ADLLMT5_LLMT4_BITMASK         (0x80U)
#define ADLLMT5_LLMT5_BITMASK         (0x100U)
#define ADLLMT5_LLMT6_BITMASK         (0x200U)
#define ADLLMT5_LLMT7_BITMASK         (0x400U)
#define ADLLMT5_LLMT8_BITMASK         (0x800U)
#define ADLLMT5_LLMT9_BITMASK         (0x1000U)
#define ADLLMT5_LLMT10_BITMASK        (0x2000U)
#define ADLLMT5_LLMT11_BITMASK        (0x4000U)
#define ADLLMT5_LLMT_GRPMASK          (0x7FF8U)
#define ADLLMT5_LLMT_GRPPOS           (0x3U)

/*** ADLLMT6 - Low Limit Register 6.; 0x0019002E ***/
#define ADLLMT6                       (*((volatile uint16 *)(&__IPSBAR[0x0019002EUL])))
#define ADLLMT6_LLMT0_BITMASK         (0x8U)
#define ADLLMT6_LLMT1_BITMASK         (0x10U)
#define ADLLMT6_LLMT2_BITMASK         (0x20U)
#define ADLLMT6_LLMT3_BITMASK         (0x40U)
#define ADLLMT6_LLMT4_BITMASK         (0x80U)
#define ADLLMT6_LLMT5_BITMASK         (0x100U)
#define ADLLMT6_LLMT6_BITMASK         (0x200U)
#define ADLLMT6_LLMT7_BITMASK         (0x400U)
#define ADLLMT6_LLMT8_BITMASK         (0x800U)
#define ADLLMT6_LLMT9_BITMASK         (0x1000U)
#define ADLLMT6_LLMT10_BITMASK        (0x2000U)
#define ADLLMT6_LLMT11_BITMASK        (0x4000U)
#define ADLLMT6_LLMT_GRPMASK          (0x7FF8U)
#define ADLLMT6_LLMT_GRPPOS           (0x3U)

/*** ADLLMT7 - Low Limit Register 7.; 0x00190030 ***/
#define ADLLMT7                       (*((volatile uint16 *)(&__IPSBAR[0x00190030UL])))
#define ADLLMT7_LLMT0_BITMASK         (0x8U)
#define ADLLMT7_LLMT1_BITMASK         (0x10U)
#define ADLLMT7_LLMT2_BITMASK         (0x20U)
#define ADLLMT7_LLMT3_BITMASK         (0x40U)
#define ADLLMT7_LLMT4_BITMASK         (0x80U)
#define ADLLMT7_LLMT5_BITMASK         (0x100U)
#define ADLLMT7_LLMT6_BITMASK         (0x200U)
#define ADLLMT7_LLMT7_BITMASK         (0x400U)
#define ADLLMT7_LLMT8_BITMASK         (0x800U)
#define ADLLMT7_LLMT9_BITMASK         (0x1000U)
#define ADLLMT7_LLMT10_BITMASK        (0x2000U)
#define ADLLMT7_LLMT11_BITMASK        (0x4000U)
#define ADLLMT7_LLMT_GRPMASK          (0x7FF8U)
#define ADLLMT7_LLMT_GRPPOS           (0x3U)

/*** ADHLMT0 - High Limit Register 0.; 0x00190032 ***/
#define ADHLMT0                       (*((volatile uint16 *)(&__IPSBAR[0x00190032UL])))
#define ADHLMT0_HLMT0_BITMASK         (0x8U)
#define ADHLMT0_HLMT1_BITMASK         (0x10U)
#define ADHLMT0_HLMT2_BITMASK         (0x20U)
#define ADHLMT0_HLMT3_BITMASK         (0x40U)
#define ADHLMT0_HLMT4_BITMASK         (0x80U)
#define ADHLMT0_HLMT5_BITMASK         (0x100U)
#define ADHLMT0_HLMT6_BITMASK         (0x200U)
#define ADHLMT0_HLMT7_BITMASK         (0x400U)
#define ADHLMT0_HLMT8_BITMASK         (0x800U)
#define ADHLMT0_HLMT9_BITMASK         (0x1000U)
#define ADHLMT0_HLMT10_BITMASK        (0x2000U)
#define ADHLMT0_HLMT11_BITMASK        (0x4000U)
#define ADHLMT0_HLMT_GRPMASK          (0x7FF8U)
#define ADHLMT0_HLMT_GRPPOS           (0x3U)

/*** ADHLMT1 - High Limit Register 1.; 0x00190034 ***/
#define ADHLMT1                       (*((volatile uint16 *)(&__IPSBAR[0x00190034UL])))
#define ADHLMT1_HLMT0_BITMASK         (0x8U)
#define ADHLMT1_HLMT1_BITMASK         (0x10U)
#define ADHLMT1_HLMT2_BITMASK         (0x20U)
#define ADHLMT1_HLMT3_BITMASK         (0x40U)
#define ADHLMT1_HLMT4_BITMASK         (0x80U)
#define ADHLMT1_HLMT5_BITMASK         (0x100U)
#define ADHLMT1_HLMT6_BITMASK         (0x200U)
#define ADHLMT1_HLMT7_BITMASK         (0x400U)
#define ADHLMT1_HLMT8_BITMASK         (0x800U)
#define ADHLMT1_HLMT9_BITMASK         (0x1000U)
#define ADHLMT1_HLMT10_BITMASK        (0x2000U)
#define ADHLMT1_HLMT11_BITMASK        (0x4000U)
#define ADHLMT1_HLMT_GRPMASK          (0x7FF8U)
#define ADHLMT1_HLMT_GRPPOS           (0x3U)

/*** ADHLMT2 - High Limit Register 2.; 0x00190036 ***/
#define ADHLMT2                       (*((volatile uint16 *)(&__IPSBAR[0x00190036UL])))
#define ADHLMT2_HLMT0_BITMASK         (0x8U)
#define ADHLMT2_HLMT1_BITMASK         (0x10U)
#define ADHLMT2_HLMT2_BITMASK         (0x20U)
#define ADHLMT2_HLMT3_BITMASK         (0x40U)
#define ADHLMT2_HLMT4_BITMASK         (0x80U)
#define ADHLMT2_HLMT5_BITMASK         (0x100U)
#define ADHLMT2_HLMT6_BITMASK         (0x200U)
#define ADHLMT2_HLMT7_BITMASK         (0x400U)
#define ADHLMT2_HLMT8_BITMASK         (0x800U)
#define ADHLMT2_HLMT9_BITMASK         (0x1000U)
#define ADHLMT2_HLMT10_BITMASK        (0x2000U)
#define ADHLMT2_HLMT11_BITMASK        (0x4000U)
#define ADHLMT2_HLMT_GRPMASK          (0x7FF8U)
#define ADHLMT2_HLMT_GRPPOS           (0x3U)

/*** ADHLMT3 - High Limit Register 3.; 0x00190038 ***/
#define ADHLMT3                       (*((volatile uint16 *)(&__IPSBAR[0x00190038UL])))
#define ADHLMT3_HLMT0_BITMASK         (0x8U)
#define ADHLMT3_HLMT1_BITMASK         (0x10U)
#define ADHLMT3_HLMT2_BITMASK         (0x20U)
#define ADHLMT3_HLMT3_BITMASK         (0x40U)
#define ADHLMT3_HLMT4_BITMASK         (0x80U)
#define ADHLMT3_HLMT5_BITMASK         (0x100U)
#define ADHLMT3_HLMT6_BITMASK         (0x200U)
#define ADHLMT3_HLMT7_BITMASK         (0x400U)
#define ADHLMT3_HLMT8_BITMASK         (0x800U)
#define ADHLMT3_HLMT9_BITMASK         (0x1000U)
#define ADHLMT3_HLMT10_BITMASK        (0x2000U)
#define ADHLMT3_HLMT11_BITMASK        (0x4000U)
#define ADHLMT3_HLMT_GRPMASK          (0x7FF8U)
#define ADHLMT3_HLMT_GRPPOS           (0x3U)

/*** ADHLMT4 - High Limit Register 4.; 0x0019003A ***/
#define ADHLMT4                       (*((volatile uint16 *)(&__IPSBAR[0x0019003AUL])))
#define ADHLMT4_HLMT0_BITMASK         (0x8U)
#define ADHLMT4_HLMT1_BITMASK         (0x10U)
#define ADHLMT4_HLMT2_BITMASK         (0x20U)
#define ADHLMT4_HLMT3_BITMASK         (0x40U)
#define ADHLMT4_HLMT4_BITMASK         (0x80U)
#define ADHLMT4_HLMT5_BITMASK         (0x100U)
#define ADHLMT4_HLMT6_BITMASK         (0x200U)
#define ADHLMT4_HLMT7_BITMASK         (0x400U)
#define ADHLMT4_HLMT8_BITMASK         (0x800U)
#define ADHLMT4_HLMT9_BITMASK         (0x1000U)
#define ADHLMT4_HLMT10_BITMASK        (0x2000U)
#define ADHLMT4_HLMT11_BITMASK        (0x4000U)
#define ADHLMT4_HLMT_GRPMASK          (0x7FF8U)
#define ADHLMT4_HLMT_GRPPOS           (0x3U)

/*** ADHLMT5 - High Limit Register 5.; 0x0019003C ***/
#define ADHLMT5                       (*((volatile uint16 *)(&__IPSBAR[0x0019003CUL])))
#define ADHLMT5_HLMT0_BITMASK         (0x8U)
#define ADHLMT5_HLMT1_BITMASK         (0x10U)
#define ADHLMT5_HLMT2_BITMASK         (0x20U)
#define ADHLMT5_HLMT3_BITMASK         (0x40U)
#define ADHLMT5_HLMT4_BITMASK         (0x80U)
#define ADHLMT5_HLMT5_BITMASK         (0x100U)
#define ADHLMT5_HLMT6_BITMASK         (0x200U)
#define ADHLMT5_HLMT7_BITMASK         (0x400U)
#define ADHLMT5_HLMT8_BITMASK         (0x800U)
#define ADHLMT5_HLMT9_BITMASK         (0x1000U)
#define ADHLMT5_HLMT10_BITMASK        (0x2000U)
#define ADHLMT5_HLMT11_BITMASK        (0x4000U)
#define ADHLMT5_HLMT_GRPMASK          (0x7FF8U)
#define ADHLMT5_HLMT_GRPPOS           (0x3U)

/*** ADHLMT6 - High Limit Register 6.; 0x0019003E ***/
#define ADHLMT6                       (*((volatile uint16 *)(&__IPSBAR[0x0019003EUL])))
#define ADHLMT6_HLMT0_BITMASK         (0x8U)
#define ADHLMT6_HLMT1_BITMASK         (0x10U)
#define ADHLMT6_HLMT2_BITMASK         (0x20U)
#define ADHLMT6_HLMT3_BITMASK         (0x40U)
#define ADHLMT6_HLMT4_BITMASK         (0x80U)
#define ADHLMT6_HLMT5_BITMASK         (0x100U)
#define ADHLMT6_HLMT6_BITMASK         (0x200U)
#define ADHLMT6_HLMT7_BITMASK         (0x400U)
#define ADHLMT6_HLMT8_BITMASK         (0x800U)
#define ADHLMT6_HLMT9_BITMASK         (0x1000U)
#define ADHLMT6_HLMT10_BITMASK        (0x2000U)
#define ADHLMT6_HLMT11_BITMASK        (0x4000U)
#define ADHLMT6_HLMT_GRPMASK          (0x7FF8U)
#define ADHLMT6_HLMT_GRPPOS           (0x3U)

/*** ADHLMT7 - High Limit Register 7.; 0x00190040 ***/
#define ADHLMT7                       (*((volatile uint16 *)(&__IPSBAR[0x00190040UL])))
#define ADHLMT7_HLMT0_BITMASK         (0x8U)
#define ADHLMT7_HLMT1_BITMASK         (0x10U)
#define ADHLMT7_HLMT2_BITMASK         (0x20U)
#define ADHLMT7_HLMT3_BITMASK         (0x40U)
#define ADHLMT7_HLMT4_BITMASK         (0x80U)
#define ADHLMT7_HLMT5_BITMASK         (0x100U)
#define ADHLMT7_HLMT6_BITMASK         (0x200U)
#define ADHLMT7_HLMT7_BITMASK         (0x400U)
#define ADHLMT7_HLMT8_BITMASK         (0x800U)
#define ADHLMT7_HLMT9_BITMASK         (0x1000U)
#define ADHLMT7_HLMT10_BITMASK        (0x2000U)
#define ADHLMT7_HLMT11_BITMASK        (0x4000U)
#define ADHLMT7_HLMT_GRPMASK          (0x7FF8U)
#define ADHLMT7_HLMT_GRPPOS           (0x3U)

/*** ADOFS0 - Offset Register 0.; 0x00190042 ***/
#define ADOFS0                        (*((volatile uint16 *)(&__IPSBAR[0x00190042UL])))
#define ADOFS0_OFFSET0_BITMASK        (0x8U)
#define ADOFS0_OFFSET1_BITMASK        (0x10U)
#define ADOFS0_OFFSET2_BITMASK        (0x20U)
#define ADOFS0_OFFSET3_BITMASK        (0x40U)
#define ADOFS0_OFFSET4_BITMASK        (0x80U)
#define ADOFS0_OFFSET5_BITMASK        (0x100U)
#define ADOFS0_OFFSET6_BITMASK        (0x200U)
#define ADOFS0_OFFSET7_BITMASK        (0x400U)
#define ADOFS0_OFFSET8_BITMASK        (0x800U)
#define ADOFS0_OFFSET9_BITMASK        (0x1000U)
#define ADOFS0_OFFSET10_BITMASK       (0x2000U)
#define ADOFS0_OFFSET11_BITMASK       (0x4000U)
#define ADOFS0_OFFSET_GRPMASK         (0x7FF8U)
#define ADOFS0_OFFSET_GRPPOS          (0x3U)

/*** ADOFS1 - Offset Register 1.; 0x00190044 ***/
#define ADOFS1                        (*((volatile uint16 *)(&__IPSBAR[0x00190044UL])))
#define ADOFS1_OFFSET0_BITMASK        (0x8U)
#define ADOFS1_OFFSET1_BITMASK        (0x10U)
#define ADOFS1_OFFSET2_BITMASK        (0x20U)
#define ADOFS1_OFFSET3_BITMASK        (0x40U)
#define ADOFS1_OFFSET4_BITMASK        (0x80U)
#define ADOFS1_OFFSET5_BITMASK        (0x100U)
#define ADOFS1_OFFSET6_BITMASK        (0x200U)
#define ADOFS1_OFFSET7_BITMASK        (0x400U)
#define ADOFS1_OFFSET8_BITMASK        (0x800U)
#define ADOFS1_OFFSET9_BITMASK        (0x1000U)
#define ADOFS1_OFFSET10_BITMASK       (0x2000U)
#define ADOFS1_OFFSET11_BITMASK       (0x4000U)
#define ADOFS1_OFFSET_GRPMASK         (0x7FF8U)
#define ADOFS1_OFFSET_GRPPOS          (0x3U)

/*** ADOFS2 - Offset Register 2.; 0x00190046 ***/
#define ADOFS2                        (*((volatile uint16 *)(&__IPSBAR[0x00190046UL])))
#define ADOFS2_OFFSET0_BITMASK        (0x8U)
#define ADOFS2_OFFSET1_BITMASK        (0x10U)
#define ADOFS2_OFFSET2_BITMASK        (0x20U)
#define ADOFS2_OFFSET3_BITMASK        (0x40U)
#define ADOFS2_OFFSET4_BITMASK        (0x80U)
#define ADOFS2_OFFSET5_BITMASK        (0x100U)
#define ADOFS2_OFFSET6_BITMASK        (0x200U)
#define ADOFS2_OFFSET7_BITMASK        (0x400U)
#define ADOFS2_OFFSET8_BITMASK        (0x800U)
#define ADOFS2_OFFSET9_BITMASK        (0x1000U)
#define ADOFS2_OFFSET10_BITMASK       (0x2000U)
#define ADOFS2_OFFSET11_BITMASK       (0x4000U)
#define ADOFS2_OFFSET_GRPMASK         (0x7FF8U)
#define ADOFS2_OFFSET_GRPPOS          (0x3U)

/*** ADOFS3 - Offset Register 3.; 0x00190048 ***/
#define ADOFS3                        (*((volatile uint16 *)(&__IPSBAR[0x00190048UL])))
#define ADOFS3_OFFSET0_BITMASK        (0x8U)
#define ADOFS3_OFFSET1_BITMASK        (0x10U)
#define ADOFS3_OFFSET2_BITMASK        (0x20U)
#define ADOFS3_OFFSET3_BITMASK        (0x40U)
#define ADOFS3_OFFSET4_BITMASK        (0x80U)
#define ADOFS3_OFFSET5_BITMASK        (0x100U)
#define ADOFS3_OFFSET6_BITMASK        (0x200U)
#define ADOFS3_OFFSET7_BITMASK        (0x400U)
#define ADOFS3_OFFSET8_BITMASK        (0x800U)
#define ADOFS3_OFFSET9_BITMASK        (0x1000U)
#define ADOFS3_OFFSET10_BITMASK       (0x2000U)
#define ADOFS3_OFFSET11_BITMASK       (0x4000U)
#define ADOFS3_OFFSET_GRPMASK         (0x7FF8U)
#define ADOFS3_OFFSET_GRPPOS          (0x3U)

/*** ADOFS4 - Offset Register 4.; 0x0019004A ***/
#define ADOFS4                        (*((volatile uint16 *)(&__IPSBAR[0x0019004AUL])))
#define ADOFS4_OFFSET0_BITMASK        (0x8U)
#define ADOFS4_OFFSET1_BITMASK        (0x10U)
#define ADOFS4_OFFSET2_BITMASK        (0x20U)
#define ADOFS4_OFFSET3_BITMASK        (0x40U)
#define ADOFS4_OFFSET4_BITMASK        (0x80U)
#define ADOFS4_OFFSET5_BITMASK        (0x100U)
#define ADOFS4_OFFSET6_BITMASK        (0x200U)
#define ADOFS4_OFFSET7_BITMASK        (0x400U)
#define ADOFS4_OFFSET8_BITMASK        (0x800U)
#define ADOFS4_OFFSET9_BITMASK        (0x1000U)
#define ADOFS4_OFFSET10_BITMASK       (0x2000U)
#define ADOFS4_OFFSET11_BITMASK       (0x4000U)
#define ADOFS4_OFFSET_GRPMASK         (0x7FF8U)
#define ADOFS4_OFFSET_GRPPOS          (0x3U)

/*** ADOFS5 - Offset Register 5.; 0x0019004C ***/
#define ADOFS5                        (*((volatile uint16 *)(&__IPSBAR[0x0019004CUL])))
#define ADOFS5_OFFSET0_BITMASK        (0x8U)
#define ADOFS5_OFFSET1_BITMASK        (0x10U)
#define ADOFS5_OFFSET2_BITMASK        (0x20U)
#define ADOFS5_OFFSET3_BITMASK        (0x40U)
#define ADOFS5_OFFSET4_BITMASK        (0x80U)
#define ADOFS5_OFFSET5_BITMASK        (0x100U)
#define ADOFS5_OFFSET6_BITMASK        (0x200U)
#define ADOFS5_OFFSET7_BITMASK        (0x400U)
#define ADOFS5_OFFSET8_BITMASK        (0x800U)
#define ADOFS5_OFFSET9_BITMASK        (0x1000U)
#define ADOFS5_OFFSET10_BITMASK       (0x2000U)
#define ADOFS5_OFFSET11_BITMASK       (0x4000U)
#define ADOFS5_OFFSET_GRPMASK         (0x7FF8U)
#define ADOFS5_OFFSET_GRPPOS          (0x3U)

/*** ADOFS6 - Offset Register 6.; 0x0019004E ***/
#define ADOFS6                        (*((volatile uint16 *)(&__IPSBAR[0x0019004EUL])))
#define ADOFS6_OFFSET0_BITMASK        (0x8U)
#define ADOFS6_OFFSET1_BITMASK        (0x10U)
#define ADOFS6_OFFSET2_BITMASK        (0x20U)
#define ADOFS6_OFFSET3_BITMASK        (0x40U)
#define ADOFS6_OFFSET4_BITMASK        (0x80U)
#define ADOFS6_OFFSET5_BITMASK        (0x100U)
#define ADOFS6_OFFSET6_BITMASK        (0x200U)
#define ADOFS6_OFFSET7_BITMASK        (0x400U)
#define ADOFS6_OFFSET8_BITMASK        (0x800U)
#define ADOFS6_OFFSET9_BITMASK        (0x1000U)
#define ADOFS6_OFFSET10_BITMASK       (0x2000U)
#define ADOFS6_OFFSET11_BITMASK       (0x4000U)
#define ADOFS6_OFFSET_GRPMASK         (0x7FF8U)
#define ADOFS6_OFFSET_GRPPOS          (0x3U)

/*** ADOFS7 - Offset Register 7.; 0x00190050 ***/
#define ADOFS7                        (*((volatile uint16 *)(&__IPSBAR[0x00190050UL])))
#define ADOFS7_OFFSET0_BITMASK        (0x8U)
#define ADOFS7_OFFSET1_BITMASK        (0x10U)
#define ADOFS7_OFFSET2_BITMASK        (0x20U)
#define ADOFS7_OFFSET3_BITMASK        (0x40U)
#define ADOFS7_OFFSET4_BITMASK        (0x80U)
#define ADOFS7_OFFSET5_BITMASK        (0x100U)
#define ADOFS7_OFFSET6_BITMASK        (0x200U)
#define ADOFS7_OFFSET7_BITMASK        (0x400U)
#define ADOFS7_OFFSET8_BITMASK        (0x800U)
#define ADOFS7_OFFSET9_BITMASK        (0x1000U)
#define ADOFS7_OFFSET10_BITMASK       (0x2000U)
#define ADOFS7_OFFSET11_BITMASK       (0x4000U)
#define ADOFS7_OFFSET_GRPMASK         (0x7FF8U)
#define ADOFS7_OFFSET_GRPPOS          (0x3U)

/*** POWER - Power Control Register.; 0x00190052 ***/
#define POWER                         (*((volatile uint16 *)(&__IPSBAR[0x00190052UL])))
#define POWER_PD0_BITMASK             (0x1U)
#define POWER_PD1_BITMASK             (0x2U)
#define POWER_PD2_BITMASK             (0x4U)
#define POWER_APD_BITMASK             (0x8U)
#define POWER_PUDELAY0_BITMASK        (0x10U)
#define POWER_PUDELAY1_BITMASK        (0x20U)
#define POWER_PUDELAY2_BITMASK        (0x40U)
#define POWER_PUDELAY3_BITMASK        (0x80U)
#define POWER_PUDELAY4_BITMASK        (0x100U)
#define POWER_PUDELAY5_BITMASK        (0x200U)
#define POWER_PSTS0_BITMASK           (0x400U)
#define POWER_PSTS1_BITMASK           (0x800U)
#define POWER_PSTS2_BITMASK           (0x1000U)
#define POWER_ASB_BITMASK             (0x8000U)
#define POWER_PUDELAY_GRPMASK         (0x3F0U)
#define POWER_PUDELAY_GRPPOS          (0x4U)

/*** CAL - Voltage Reference Register.; 0x00190054 ***/
#define CAL                           (*((volatile uint16 *)(&__IPSBAR[0x00190054UL])))
#define CAL_SEL_VREFL_BITMASK         (0x4000U)
#define CAL_SEL_VREFH_BITMASK         (0x8000U)


/******************************************
*** Peripheral GPTA
*******************************************/

/*** GPTIOS - GPT Input Capture/Output Compare Select Register.; 0x001A0000 ***/
#define GPTIOS                        (*((volatile uint8 *)(&__IPSBAR[0x001A0000UL])))
#define GPTIOS_IOS0_BITMASK           (0x1U)
#define GPTIOS_IOS1_BITMASK           (0x2U)
#define GPTIOS_IOS2_BITMASK           (0x4U)
#define GPTIOS_IOS3_BITMASK           (0x8U)

/*** GPTCFORC - GPT Compare Force Register.; 0x001A0001 ***/
#define GPTCFORC                      (*((volatile uint8 *)(&__IPSBAR[0x001A0001UL])))
#define GPTCFORC_FOC0_BITMASK         (0x1U)
#define GPTCFORC_FOC1_BITMASK         (0x2U)
#define GPTCFORC_FOC2_BITMASK         (0x4U)
#define GPTCFORC_FOC3_BITMASK         (0x8U)

/*** GPTOC3M - GPT Output Compare 3 Mask Register.; 0x001A0002 ***/
#define GPTOC3M                       (*((volatile uint8 *)(&__IPSBAR[0x001A0002UL])))
#define GPTOC3M_OC3M0_BITMASK         (0x1U)
#define GPTOC3M_OC3M1_BITMASK         (0x2U)
#define GPTOC3M_OC3M2_BITMASK         (0x4U)
#define GPTOC3M_OC3M3_BITMASK         (0x8U)

/*** GPTOC3D - GPT Output Compare 3 Data Register.; 0x001A0003 ***/
#define GPTOC3D                       (*((volatile uint8 *)(&__IPSBAR[0x001A0003UL])))
#define GPTOC3D_OC3D0_BITMASK         (0x1U)
#define GPTOC3D_OC3D1_BITMASK         (0x2U)
#define GPTOC3D_OC3D2_BITMASK         (0x4U)
#define GPTOC3D_OC3D3_BITMASK         (0x8U)

/*** GPTCNT - GPT Counter Register.; 0x001A0004 ***/
#define GPTCNT                        (*((volatile uint16 *)(&__IPSBAR[0x001A0004UL])))
#define GPTCNT_CNTR0_BITMASK          (0x1U)
#define GPTCNT_CNTR1_BITMASK          (0x2U)
#define GPTCNT_CNTR2_BITMASK          (0x4U)
#define GPTCNT_CNTR3_BITMASK          (0x8U)
#define GPTCNT_CNTR4_BITMASK          (0x10U)
#define GPTCNT_CNTR5_BITMASK          (0x20U)
#define GPTCNT_CNTR6_BITMASK          (0x40U)
#define GPTCNT_CNTR7_BITMASK          (0x80U)
#define GPTCNT_CNTR8_BITMASK          (0x100U)
#define GPTCNT_CNTR9_BITMASK          (0x200U)
#define GPTCNT_CNTR10_BITMASK         (0x400U)
#define GPTCNT_CNTR11_BITMASK         (0x800U)
#define GPTCNT_CNTR12_BITMASK         (0x1000U)
#define GPTCNT_CNTR13_BITMASK         (0x2000U)
#define GPTCNT_CNTR14_BITMASK         (0x4000U)
#define GPTCNT_CNTR15_BITMASK         (0x8000U)
#define GPTCNT_CNTR_GRPMASK           (0xFFFFU)
#define GPTCNT_CNTR_GRPPOS            (0U)

/*** GPTSCR1 - GPT System Control Register 1.; 0x001A0006 ***/
#define GPTSCR1                       (*((volatile uint8 *)(&__IPSBAR[0x001A0006UL])))
#define GPTSCR1_TFFCA_BITMASK         (0x10U)
#define GPTSCR1_GPTEN_BITMASK         (0x80U)

/*** GPTTOV - GPT Toggle-On-Overflow Register.; 0x001A0008 ***/
#define GPTTOV                        (*((volatile uint8 *)(&__IPSBAR[0x001A0008UL])))
#define GPTTOV_TOV0_BITMASK           (0x1U)
#define GPTTOV_TOV1_BITMASK           (0x2U)
#define GPTTOV_TOV2_BITMASK           (0x4U)
#define GPTTOV_TOV3_BITMASK           (0x8U)

/*** GPTCTL1 - GPT Control Register 1.; 0x001A0009 ***/
#define GPTCTL1                       (*((volatile uint8 *)(&__IPSBAR[0x001A0009UL])))
#define GPTCTL1_OL0_BITMASK           (0x1U)
#define GPTCTL1_OM0_BITMASK           (0x2U)
#define GPTCTL1_OL1_BITMASK           (0x4U)
#define GPTCTL1_OM1_BITMASK           (0x8U)
#define GPTCTL1_OL2_BITMASK           (0x10U)
#define GPTCTL1_OM2_BITMASK           (0x20U)
#define GPTCTL1_OL3_BITMASK           (0x40U)
#define GPTCTL1_OM3_BITMASK           (0x80U)

/*** GPTCTL2 - GPT Control Register 2.; 0x001A000B ***/
#define GPTCTL2                       (*((volatile uint8 *)(&__IPSBAR[0x001A000BUL])))
#define GPTCTL2_EDG0A_BITMASK         (0x1U)
#define GPTCTL2_EDG0B_BITMASK         (0x2U)
#define GPTCTL2_EDG1A_BITMASK         (0x4U)
#define GPTCTL2_EDG1B_BITMASK         (0x8U)
#define GPTCTL2_EDG2A_BITMASK         (0x10U)
#define GPTCTL2_EDG2B_BITMASK         (0x20U)
#define GPTCTL2_EDG3A_BITMASK         (0x40U)
#define GPTCTL2_EDG3B_BITMASK         (0x80U)

/*** GPTIE - GPT Interrupt Enable Register.; 0x001A000C ***/
#define GPTIE                         (*((volatile uint8 *)(&__IPSBAR[0x001A000CUL])))
#define GPTIE_CI0_BITMASK             (0x1U)
#define GPTIE_CI1_BITMASK             (0x2U)
#define GPTIE_CI2_BITMASK             (0x4U)
#define GPTIE_CI3_BITMASK             (0x8U)

/*** GPTSCR2 - GPT System Control Register 2.; 0x001A000D ***/
#define GPTSCR2                       (*((volatile uint8 *)(&__IPSBAR[0x001A000DUL])))
#define GPTSCR2_PR0_BITMASK           (0x1U)
#define GPTSCR2_PR1_BITMASK           (0x2U)
#define GPTSCR2_PR2_BITMASK           (0x4U)
#define GPTSCR2_TCRE_BITMASK          (0x8U)
#define GPTSCR2_RDPT_BITMASK          (0x10U)
#define GPTSCR2_PUPT_BITMASK          (0x20U)
#define GPTSCR2_TOI_BITMASK           (0x80U)
#define GPTSCR2_PR_GRPMASK            (0x7U)
#define GPTSCR2_PR_GRPPOS             (0U)

/*** GPTFLG1 - GPT Flag Register 1.; 0x001A000E ***/
#define GPTFLG1                       (*((volatile uint8 *)(&__IPSBAR[0x001A000EUL])))
#define GPTFLG1_CF0_BITMASK           (0x1U)
#define GPTFLG1_CF1_BITMASK           (0x2U)
#define GPTFLG1_CF2_BITMASK           (0x4U)
#define GPTFLG1_CF3_BITMASK           (0x8U)

/*** GPTFLG2 - GPT Flag Register 2.; 0x001A000F ***/
#define GPTFLG2                       (*((volatile uint8 *)(&__IPSBAR[0x001A000FUL])))
#define GPTFLG2_TOF_BITMASK           (0x80U)

/*** GPTC0 - GPT Channel 0 Register.; 0x001A0010 ***/
#define GPTC0                         (*((volatile uint16 *)(&__IPSBAR[0x001A0010UL])))
#define GPTC0_CCNT0_BITMASK           (0x1U)
#define GPTC0_CCNT1_BITMASK           (0x2U)
#define GPTC0_CCNT2_BITMASK           (0x4U)
#define GPTC0_CCNT3_BITMASK           (0x8U)
#define GPTC0_CCNT4_BITMASK           (0x10U)
#define GPTC0_CCNT5_BITMASK           (0x20U)
#define GPTC0_CCNT6_BITMASK           (0x40U)
#define GPTC0_CCNT7_BITMASK           (0x80U)
#define GPTC0_CCNT8_BITMASK           (0x100U)
#define GPTC0_CCNT9_BITMASK           (0x200U)
#define GPTC0_CCNT10_BITMASK          (0x400U)
#define GPTC0_CCNT11_BITMASK          (0x800U)
#define GPTC0_CCNT12_BITMASK          (0x1000U)
#define GPTC0_CCNT13_BITMASK          (0x2000U)
#define GPTC0_CCNT14_BITMASK          (0x4000U)
#define GPTC0_CCNT15_BITMASK          (0x8000U)
#define GPTC0_CCNT_GRPMASK            (0xFFFFU)
#define GPTC0_CCNT_GRPPOS             (0U)

/*** GPTC1 - GPT Channel 1 Register.; 0x001A0012 ***/
#define GPTC1                         (*((volatile uint16 *)(&__IPSBAR[0x001A0012UL])))
#define GPTC1_CCNT0_BITMASK           (0x1U)
#define GPTC1_CCNT1_BITMASK           (0x2U)
#define GPTC1_CCNT2_BITMASK           (0x4U)
#define GPTC1_CCNT3_BITMASK           (0x8U)
#define GPTC1_CCNT4_BITMASK           (0x10U)
#define GPTC1_CCNT5_BITMASK           (0x20U)
#define GPTC1_CCNT6_BITMASK           (0x40U)
#define GPTC1_CCNT7_BITMASK           (0x80U)
#define GPTC1_CCNT8_BITMASK           (0x100U)
#define GPTC1_CCNT9_BITMASK           (0x200U)
#define GPTC1_CCNT10_BITMASK          (0x400U)
#define GPTC1_CCNT11_BITMASK          (0x800U)
#define GPTC1_CCNT12_BITMASK          (0x1000U)
#define GPTC1_CCNT13_BITMASK          (0x2000U)
#define GPTC1_CCNT14_BITMASK          (0x4000U)
#define GPTC1_CCNT15_BITMASK          (0x8000U)
#define GPTC1_CCNT_GRPMASK            (0xFFFFU)
#define GPTC1_CCNT_GRPPOS             (0U)

/*** GPTC2 - GPT Channel 2 Register.; 0x001A0014 ***/
#define GPTC2                         (*((volatile uint16 *)(&__IPSBAR[0x001A0014UL])))
#define GPTC2_CCNT0_BITMASK           (0x1U)
#define GPTC2_CCNT1_BITMASK           (0x2U)
#define GPTC2_CCNT2_BITMASK           (0x4U)
#define GPTC2_CCNT3_BITMASK           (0x8U)
#define GPTC2_CCNT4_BITMASK           (0x10U)
#define GPTC2_CCNT5_BITMASK           (0x20U)
#define GPTC2_CCNT6_BITMASK           (0x40U)
#define GPTC2_CCNT7_BITMASK           (0x80U)
#define GPTC2_CCNT8_BITMASK           (0x100U)
#define GPTC2_CCNT9_BITMASK           (0x200U)
#define GPTC2_CCNT10_BITMASK          (0x400U)
#define GPTC2_CCNT11_BITMASK          (0x800U)
#define GPTC2_CCNT12_BITMASK          (0x1000U)
#define GPTC2_CCNT13_BITMASK          (0x2000U)
#define GPTC2_CCNT14_BITMASK          (0x4000U)
#define GPTC2_CCNT15_BITMASK          (0x8000U)
#define GPTC2_CCNT_GRPMASK            (0xFFFFU)
#define GPTC2_CCNT_GRPPOS             (0U)

/*** GPTC3 - GPT Channel 3 Register.; 0x001A0016 ***/
#define GPTC3                         (*((volatile uint16 *)(&__IPSBAR[0x001A0016UL])))
#define GPTC3_CCNT0_BITMASK           (0x1U)
#define GPTC3_CCNT1_BITMASK           (0x2U)
#define GPTC3_CCNT2_BITMASK           (0x4U)
#define GPTC3_CCNT3_BITMASK           (0x8U)
#define GPTC3_CCNT4_BITMASK           (0x10U)
#define GPTC3_CCNT5_BITMASK           (0x20U)
#define GPTC3_CCNT6_BITMASK           (0x40U)
#define GPTC3_CCNT7_BITMASK           (0x80U)
#define GPTC3_CCNT8_BITMASK           (0x100U)
#define GPTC3_CCNT9_BITMASK           (0x200U)
#define GPTC3_CCNT10_BITMASK          (0x400U)
#define GPTC3_CCNT11_BITMASK          (0x800U)
#define GPTC3_CCNT12_BITMASK          (0x1000U)
#define GPTC3_CCNT13_BITMASK          (0x2000U)
#define GPTC3_CCNT14_BITMASK          (0x4000U)
#define GPTC3_CCNT15_BITMASK          (0x8000U)
#define GPTC3_CCNT_GRPMASK            (0xFFFFU)
#define GPTC3_CCNT_GRPPOS             (0U)

/*** GPTPACTL - Pulse Accumulator Control Register.; 0x001A0018 ***/
#define GPTPACTL                      (*((volatile uint8 *)(&__IPSBAR[0x001A0018UL])))
#define GPTPACTL_PAI_BITMASK          (0x1U)
#define GPTPACTL_PAOVI_BITMASK        (0x2U)
#define GPTPACTL_CLK0_BITMASK         (0x4U)
#define GPTPACTL_CLK1_BITMASK         (0x8U)
#define GPTPACTL_PEDGE_BITMASK        (0x10U)
#define GPTPACTL_PAMOD_BITMASK        (0x20U)
#define GPTPACTL_PAE_BITMASK          (0x40U)
#define GPTPACTL_CLK_GRPMASK          (0xCU)
#define GPTPACTL_CLK_GRPPOS           (0x2U)

/*** GPTPAFLG - Pulse Accumulator Flag Register.; 0x001A0019 ***/
#define GPTPAFLG                      (*((volatile uint8 *)(&__IPSBAR[0x001A0019UL])))
#define GPTPAFLG_PAIF_BITMASK         (0x1U)
#define GPTPAFLG_PAOVF_BITMASK        (0x2U)

/*** GPTPACNT - Pulse Accumulator Counter Register.; 0x001A001A ***/
#define GPTPACNT                      (*((volatile uint16 *)(&__IPSBAR[0x001A001AUL])))
#define GPTPACNT_PACNT0_BITMASK       (0x1U)
#define GPTPACNT_PACNT1_BITMASK       (0x2U)
#define GPTPACNT_PACNT2_BITMASK       (0x4U)
#define GPTPACNT_PACNT3_BITMASK       (0x8U)
#define GPTPACNT_PACNT4_BITMASK       (0x10U)
#define GPTPACNT_PACNT5_BITMASK       (0x20U)
#define GPTPACNT_PACNT6_BITMASK       (0x40U)
#define GPTPACNT_PACNT7_BITMASK       (0x80U)
#define GPTPACNT_PACNT8_BITMASK       (0x100U)
#define GPTPACNT_PACNT9_BITMASK       (0x200U)
#define GPTPACNT_PACNT10_BITMASK      (0x400U)
#define GPTPACNT_PACNT11_BITMASK      (0x800U)
#define GPTPACNT_PACNT12_BITMASK      (0x1000U)
#define GPTPACNT_PACNT13_BITMASK      (0x2000U)
#define GPTPACNT_PACNT14_BITMASK      (0x4000U)
#define GPTPACNT_PACNT15_BITMASK      (0x8000U)
#define GPTPACNT_PACNT_GRPMASK        (0xFFFFU)
#define GPTPACNT_PACNT_GRPPOS         (0U)

/*** GPTPORT - GPT Port Data Register.; 0x001A001D ***/
#define GPTPORT                       (*((volatile uint8 *)(&__IPSBAR[0x001A001DUL])))
#define GPTPORT_PORTT0_BITMASK        (0x1U)
#define GPTPORT_PORTT1_BITMASK        (0x2U)
#define GPTPORT_PORTT2_BITMASK        (0x4U)
#define GPTPORT_PORTT3_BITMASK        (0x8U)

/*** GPTDDR - GPT Port Data Direction Register.; 0x001A001E ***/
#define GPTDDR                        (*((volatile uint8 *)(&__IPSBAR[0x001A001EUL])))
#define GPTDDR_DDRT0_BITMASK          (0x1U)
#define GPTDDR_DDRT1_BITMASK          (0x2U)
#define GPTDDR_DDRT2_BITMASK          (0x4U)
#define GPTDDR_DDRT3_BITMASK          (0x8U)


/******************************************
*** Peripheral PWM
*******************************************/

/*** PWME - PWM Enable Register.; 0x001B0000 ***/
#define PWME                          (*((volatile uint8 *)(&__IPSBAR[0x001B0000UL])))
#define PWME_PWME0_BITMASK            (0x1U)
#define PWME_PWME1_BITMASK            (0x2U)
#define PWME_PWME2_BITMASK            (0x4U)
#define PWME_PWME3_BITMASK            (0x8U)
#define PWME_PWME4_BITMASK            (0x10U)
#define PWME_PWME5_BITMASK            (0x20U)
#define PWME_PWME6_BITMASK            (0x40U)
#define PWME_PWME7_BITMASK            (0x80U)

/*** PWMPOL - PWM Polarity Register.; 0x001B0001 ***/
#define PWMPOL                        (*((volatile uint8 *)(&__IPSBAR[0x001B0001UL])))
#define PWMPOL_PPOL0_BITMASK          (0x1U)
#define PWMPOL_PPOL1_BITMASK          (0x2U)
#define PWMPOL_PPOL2_BITMASK          (0x4U)
#define PWMPOL_PPOL3_BITMASK          (0x8U)
#define PWMPOL_PPOL4_BITMASK          (0x10U)
#define PWMPOL_PPOL5_BITMASK          (0x20U)
#define PWMPOL_PPOL6_BITMASK          (0x40U)
#define PWMPOL_PPOL7_BITMASK          (0x80U)

/*** PWMCLK - PWM Clock Select Register.; 0x001B0002 ***/
#define PWMCLK                        (*((volatile uint8 *)(&__IPSBAR[0x001B0002UL])))
#define PWMCLK_PCLK0_BITMASK          (0x1U)
#define PWMCLK_PCLK1_BITMASK          (0x2U)
#define PWMCLK_PCLK2_BITMASK          (0x4U)
#define PWMCLK_PCLK3_BITMASK          (0x8U)
#define PWMCLK_PCLK4_BITMASK          (0x10U)
#define PWMCLK_PCLK5_BITMASK          (0x20U)
#define PWMCLK_PCLK6_BITMASK          (0x40U)
#define PWMCLK_PCLK7_BITMASK          (0x80U)

/*** PWMPRCLK - PWM Prescale Clock Select Register.; 0x001B0003 ***/
#define PWMPRCLK                      (*((volatile uint8 *)(&__IPSBAR[0x001B0003UL])))
#define PWMPRCLK_PCKA0_BITMASK        (0x1U)
#define PWMPRCLK_PCKA1_BITMASK        (0x2U)
#define PWMPRCLK_PCKA2_BITMASK        (0x4U)
#define PWMPRCLK_PCKB0_BITMASK        (0x10U)
#define PWMPRCLK_PCKB1_BITMASK        (0x20U)
#define PWMPRCLK_PCKB2_BITMASK        (0x40U)
#define PWMPRCLK_PCKA_GRPMASK         (0x7U)
#define PWMPRCLK_PCKA_GRPPOS          (0U)
#define PWMPRCLK_PCKB_GRPMASK         (0x70U)
#define PWMPRCLK_PCKB_GRPPOS          (0x4U)

/*** PWMCAE - PWM Center Align Enable Register.; 0x001B0004 ***/
#define PWMCAE                        (*((volatile uint8 *)(&__IPSBAR[0x001B0004UL])))
#define PWMCAE_CAE0_BITMASK           (0x1U)
#define PWMCAE_CAE1_BITMASK           (0x2U)
#define PWMCAE_CAE2_BITMASK           (0x4U)
#define PWMCAE_CAE3_BITMASK           (0x8U)
#define PWMCAE_CAE4_BITMASK           (0x10U)
#define PWMCAE_CAE5_BITMASK           (0x20U)
#define PWMCAE_CAE6_BITMASK           (0x40U)
#define PWMCAE_CAE7_BITMASK           (0x80U)

/*** PWMCTL - PWM Control Register.; 0x001B0005 ***/
#define PWMCTL                        (*((volatile uint8 *)(&__IPSBAR[0x001B0005UL])))
#define PWMCTL_PFRZ_BITMASK           (0x4U)
#define PWMCTL_PSWAI_BITMASK          (0x8U)
#define PWMCTL_CON01_BITMASK          (0x10U)
#define PWMCTL_CON23_BITMASK          (0x20U)
#define PWMCTL_CON45_BITMASK          (0x40U)
#define PWMCTL_CON67_BITMASK          (0x80U)

/*** PWMSCLA - PWM Scale A Register.; 0x001B0008 ***/
#define PWMSCLA                       (*((volatile uint8 *)(&__IPSBAR[0x001B0008UL])))
#define PWMSCLA_SCALEA0_BITMASK       (0x1U)
#define PWMSCLA_SCALEA1_BITMASK       (0x2U)
#define PWMSCLA_SCALEA2_BITMASK       (0x4U)
#define PWMSCLA_SCALEA3_BITMASK       (0x8U)
#define PWMSCLA_SCALEA4_BITMASK       (0x10U)
#define PWMSCLA_SCALEA5_BITMASK       (0x20U)
#define PWMSCLA_SCALEA6_BITMASK       (0x40U)
#define PWMSCLA_SCALEA7_BITMASK       (0x80U)
#define PWMSCLA_SCALEA_GRPMASK        (0xFFU)
#define PWMSCLA_SCALEA_GRPPOS         (0U)

/*** PWMSCLB - PWM Scale B Register.; 0x001B0009 ***/
#define PWMSCLB                       (*((volatile uint8 *)(&__IPSBAR[0x001B0009UL])))
#define PWMSCLB_SCALEB0_BITMASK       (0x1U)
#define PWMSCLB_SCALEB1_BITMASK       (0x2U)
#define PWMSCLB_SCALEB2_BITMASK       (0x4U)
#define PWMSCLB_SCALEB3_BITMASK       (0x8U)
#define PWMSCLB_SCALEB4_BITMASK       (0x10U)
#define PWMSCLB_SCALEB5_BITMASK       (0x20U)
#define PWMSCLB_SCALEB6_BITMASK       (0x40U)
#define PWMSCLB_SCALEB7_BITMASK       (0x80U)
#define PWMSCLB_SCALEB_GRPMASK        (0xFFU)
#define PWMSCLB_SCALEB_GRPPOS         (0U)

/*** PWMCNT01 - PWM Channel Counter 01 Register; 0x001B000C ***/
#define PWMCNT01                      (*((volatile uint16 *)(&__IPSBAR[0x001B000CUL])))
#define PWMCNT01_BIT0_BITMASK         (0x1U)
#define PWMCNT01_BIT1_BITMASK         (0x2U)
#define PWMCNT01_BIT2_BITMASK         (0x4U)
#define PWMCNT01_BIT3_BITMASK         (0x8U)
#define PWMCNT01_BIT4_BITMASK         (0x10U)
#define PWMCNT01_BIT5_BITMASK         (0x20U)
#define PWMCNT01_BIT6_BITMASK         (0x40U)
#define PWMCNT01_BIT7_BITMASK         (0x80U)
#define PWMCNT01_BIT8_BITMASK         (0x100U)
#define PWMCNT01_BIT9_BITMASK         (0x200U)
#define PWMCNT01_BIT10_BITMASK        (0x400U)
#define PWMCNT01_BIT11_BITMASK        (0x800U)
#define PWMCNT01_BIT12_BITMASK        (0x1000U)
#define PWMCNT01_BIT13_BITMASK        (0x2000U)
#define PWMCNT01_BIT14_BITMASK        (0x4000U)
#define PWMCNT01_BIT15_BITMASK        (0x8000U)

/*** PWMCNT0 - PWM Channel 0 Counter Register.; 0x001B000C ***/
#define PWMCNT0                       (*((volatile uint8 *)(&__IPSBAR[0x001B000CUL])))
#define PWMCNT0_COUNT0_BITMASK        (0x1U)
#define PWMCNT0_COUNT1_BITMASK        (0x2U)
#define PWMCNT0_COUNT2_BITMASK        (0x4U)
#define PWMCNT0_COUNT3_BITMASK        (0x8U)
#define PWMCNT0_COUNT4_BITMASK        (0x10U)
#define PWMCNT0_COUNT5_BITMASK        (0x20U)
#define PWMCNT0_COUNT6_BITMASK        (0x40U)
#define PWMCNT0_COUNT7_BITMASK        (0x80U)
#define PWMCNT0_COUNT_GRPMASK         (0xFFU)
#define PWMCNT0_COUNT_GRPPOS          (0U)

/*** PWMCNT1 - PWM Channel 1 Counter Register.; 0x001B000D ***/
#define PWMCNT1                       (*((volatile uint8 *)(&__IPSBAR[0x001B000DUL])))
#define PWMCNT1_COUNT0_BITMASK        (0x1U)
#define PWMCNT1_COUNT1_BITMASK        (0x2U)
#define PWMCNT1_COUNT2_BITMASK        (0x4U)
#define PWMCNT1_COUNT3_BITMASK        (0x8U)
#define PWMCNT1_COUNT4_BITMASK        (0x10U)
#define PWMCNT1_COUNT5_BITMASK        (0x20U)
#define PWMCNT1_COUNT6_BITMASK        (0x40U)
#define PWMCNT1_COUNT7_BITMASK        (0x80U)
#define PWMCNT1_COUNT_GRPMASK         (0xFFU)
#define PWMCNT1_COUNT_GRPPOS          (0U)

/*** PWMCNT23 - PWM Channel Counter 23 Register; 0x001B000E ***/
#define PWMCNT23                      (*((volatile uint16 *)(&__IPSBAR[0x001B000EUL])))
#define PWMCNT23_BIT0_BITMASK         (0x1U)
#define PWMCNT23_BIT1_BITMASK         (0x2U)
#define PWMCNT23_BIT2_BITMASK         (0x4U)
#define PWMCNT23_BIT3_BITMASK         (0x8U)
#define PWMCNT23_BIT4_BITMASK         (0x10U)
#define PWMCNT23_BIT5_BITMASK         (0x20U)
#define PWMCNT23_BIT6_BITMASK         (0x40U)
#define PWMCNT23_BIT7_BITMASK         (0x80U)
#define PWMCNT23_BIT8_BITMASK         (0x100U)
#define PWMCNT23_BIT9_BITMASK         (0x200U)
#define PWMCNT23_BIT10_BITMASK        (0x400U)
#define PWMCNT23_BIT11_BITMASK        (0x800U)
#define PWMCNT23_BIT12_BITMASK        (0x1000U)
#define PWMCNT23_BIT13_BITMASK        (0x2000U)
#define PWMCNT23_BIT14_BITMASK        (0x4000U)
#define PWMCNT23_BIT15_BITMASK        (0x8000U)

/*** PWMCNT2 - PWM Channel 2 Counter Register.; 0x001B000E ***/
#define PWMCNT2                       (*((volatile uint8 *)(&__IPSBAR[0x001B000EUL])))
#define PWMCNT2_COUNT0_BITMASK        (0x1U)
#define PWMCNT2_COUNT1_BITMASK        (0x2U)
#define PWMCNT2_COUNT2_BITMASK        (0x4U)
#define PWMCNT2_COUNT3_BITMASK        (0x8U)
#define PWMCNT2_COUNT4_BITMASK        (0x10U)
#define PWMCNT2_COUNT5_BITMASK        (0x20U)
#define PWMCNT2_COUNT6_BITMASK        (0x40U)
#define PWMCNT2_COUNT7_BITMASK        (0x80U)
#define PWMCNT2_COUNT_GRPMASK         (0xFFU)
#define PWMCNT2_COUNT_GRPPOS          (0U)

/*** PWMCNT3 - PWM Channel 3 Counter Register.; 0x001B000F ***/
#define PWMCNT3                       (*((volatile uint8 *)(&__IPSBAR[0x001B000FUL])))
#define PWMCNT3_COUNT0_BITMASK        (0x1U)
#define PWMCNT3_COUNT1_BITMASK        (0x2U)
#define PWMCNT3_COUNT2_BITMASK        (0x4U)
#define PWMCNT3_COUNT3_BITMASK        (0x8U)
#define PWMCNT3_COUNT4_BITMASK        (0x10U)
#define PWMCNT3_COUNT5_BITMASK        (0x20U)
#define PWMCNT3_COUNT6_BITMASK        (0x40U)
#define PWMCNT3_COUNT7_BITMASK        (0x80U)
#define PWMCNT3_COUNT_GRPMASK         (0xFFU)
#define PWMCNT3_COUNT_GRPPOS          (0U)

/*** PWMCNT4 - PWM Channel 4 Counter Register.; 0x001B0010 ***/
#define PWMCNT4                       (*((volatile uint8 *)(&__IPSBAR[0x001B0010UL])))
#define PWMCNT4_COUNT0_BITMASK        (0x1U)
#define PWMCNT4_COUNT1_BITMASK        (0x2U)
#define PWMCNT4_COUNT2_BITMASK        (0x4U)
#define PWMCNT4_COUNT3_BITMASK        (0x8U)
#define PWMCNT4_COUNT4_BITMASK        (0x10U)
#define PWMCNT4_COUNT5_BITMASK        (0x20U)
#define PWMCNT4_COUNT6_BITMASK        (0x40U)
#define PWMCNT4_COUNT7_BITMASK        (0x80U)
#define PWMCNT4_COUNT_GRPMASK         (0xFFU)
#define PWMCNT4_COUNT_GRPPOS          (0U)

/*** PWMCNT45 - PWM Channel Counter 45 Register; 0x001B0010 ***/
#define PWMCNT45                      (*((volatile uint16 *)(&__IPSBAR[0x001B0010UL])))
#define PWMCNT45_BIT0_BITMASK         (0x1U)
#define PWMCNT45_BIT1_BITMASK         (0x2U)
#define PWMCNT45_BIT2_BITMASK         (0x4U)
#define PWMCNT45_BIT3_BITMASK         (0x8U)
#define PWMCNT45_BIT4_BITMASK         (0x10U)
#define PWMCNT45_BIT5_BITMASK         (0x20U)
#define PWMCNT45_BIT6_BITMASK         (0x40U)
#define PWMCNT45_BIT7_BITMASK         (0x80U)
#define PWMCNT45_BIT8_BITMASK         (0x100U)
#define PWMCNT45_BIT9_BITMASK         (0x200U)
#define PWMCNT45_BIT10_BITMASK        (0x400U)
#define PWMCNT45_BIT11_BITMASK        (0x800U)
#define PWMCNT45_BIT12_BITMASK        (0x1000U)
#define PWMCNT45_BIT13_BITMASK        (0x2000U)
#define PWMCNT45_BIT14_BITMASK        (0x4000U)
#define PWMCNT45_BIT15_BITMASK        (0x8000U)

/*** PWMCNT5 - PWM Channel 5 Counter Register.; 0x001B0011 ***/
#define PWMCNT5                       (*((volatile uint8 *)(&__IPSBAR[0x001B0011UL])))
#define PWMCNT5_COUNT0_BITMASK        (0x1U)
#define PWMCNT5_COUNT1_BITMASK        (0x2U)
#define PWMCNT5_COUNT2_BITMASK        (0x4U)
#define PWMCNT5_COUNT3_BITMASK        (0x8U)
#define PWMCNT5_COUNT4_BITMASK        (0x10U)
#define PWMCNT5_COUNT5_BITMASK        (0x20U)
#define PWMCNT5_COUNT6_BITMASK        (0x40U)
#define PWMCNT5_COUNT7_BITMASK        (0x80U)
#define PWMCNT5_COUNT_GRPMASK         (0xFFU)
#define PWMCNT5_COUNT_GRPPOS          (0U)

/*** PWMCNT6 - PWM Channel 6 Counter Register.; 0x001B0012 ***/
#define PWMCNT6                       (*((volatile uint8 *)(&__IPSBAR[0x001B0012UL])))
#define PWMCNT6_COUNT0_BITMASK        (0x1U)
#define PWMCNT6_COUNT1_BITMASK        (0x2U)
#define PWMCNT6_COUNT2_BITMASK        (0x4U)
#define PWMCNT6_COUNT3_BITMASK        (0x8U)
#define PWMCNT6_COUNT4_BITMASK        (0x10U)
#define PWMCNT6_COUNT5_BITMASK        (0x20U)
#define PWMCNT6_COUNT6_BITMASK        (0x40U)
#define PWMCNT6_COUNT7_BITMASK        (0x80U)
#define PWMCNT6_COUNT_GRPMASK         (0xFFU)
#define PWMCNT6_COUNT_GRPPOS          (0U)

/*** PWMCNT67 - PWM Channel Counter 67 Register; 0x001B0012 ***/
#define PWMCNT67                      (*((volatile uint16 *)(&__IPSBAR[0x001B0012UL])))
#define PWMCNT67_BIT0_BITMASK         (0x1U)
#define PWMCNT67_BIT1_BITMASK         (0x2U)
#define PWMCNT67_BIT2_BITMASK         (0x4U)
#define PWMCNT67_BIT3_BITMASK         (0x8U)
#define PWMCNT67_BIT4_BITMASK         (0x10U)
#define PWMCNT67_BIT5_BITMASK         (0x20U)
#define PWMCNT67_BIT6_BITMASK         (0x40U)
#define PWMCNT67_BIT7_BITMASK         (0x80U)
#define PWMCNT67_BIT8_BITMASK         (0x100U)
#define PWMCNT67_BIT9_BITMASK         (0x200U)
#define PWMCNT67_BIT10_BITMASK        (0x400U)
#define PWMCNT67_BIT11_BITMASK        (0x800U)
#define PWMCNT67_BIT12_BITMASK        (0x1000U)
#define PWMCNT67_BIT13_BITMASK        (0x2000U)
#define PWMCNT67_BIT14_BITMASK        (0x4000U)
#define PWMCNT67_BIT15_BITMASK        (0x8000U)

/*** PWMCNT7 - PWM Channel 7 Counter Register.; 0x001B0013 ***/
#define PWMCNT7                       (*((volatile uint8 *)(&__IPSBAR[0x001B0013UL])))
#define PWMCNT7_COUNT0_BITMASK        (0x1U)
#define PWMCNT7_COUNT1_BITMASK        (0x2U)
#define PWMCNT7_COUNT2_BITMASK        (0x4U)
#define PWMCNT7_COUNT3_BITMASK        (0x8U)
#define PWMCNT7_COUNT4_BITMASK        (0x10U)
#define PWMCNT7_COUNT5_BITMASK        (0x20U)
#define PWMCNT7_COUNT6_BITMASK        (0x40U)
#define PWMCNT7_COUNT7_BITMASK        (0x80U)
#define PWMCNT7_COUNT_GRPMASK         (0xFFU)
#define PWMCNT7_COUNT_GRPPOS          (0U)

/*** PWMPER01 - PWM Channel Period 01 Register; 0x001B0014 ***/
#define PWMPER01                      (*((volatile uint16 *)(&__IPSBAR[0x001B0014UL])))
#define PWMPER01_BIT0_BITMASK         (0x1U)
#define PWMPER01_BIT1_BITMASK         (0x2U)
#define PWMPER01_BIT2_BITMASK         (0x4U)
#define PWMPER01_BIT3_BITMASK         (0x8U)
#define PWMPER01_BIT4_BITMASK         (0x10U)
#define PWMPER01_BIT5_BITMASK         (0x20U)
#define PWMPER01_BIT6_BITMASK         (0x40U)
#define PWMPER01_BIT7_BITMASK         (0x80U)
#define PWMPER01_BIT8_BITMASK         (0x100U)
#define PWMPER01_BIT9_BITMASK         (0x200U)
#define PWMPER01_BIT10_BITMASK        (0x400U)
#define PWMPER01_BIT11_BITMASK        (0x800U)
#define PWMPER01_BIT12_BITMASK        (0x1000U)
#define PWMPER01_BIT13_BITMASK        (0x2000U)
#define PWMPER01_BIT14_BITMASK        (0x4000U)
#define PWMPER01_BIT15_BITMASK        (0x8000U)

/*** PWMPER0 - PWM Channel 0 Period Register.; 0x001B0014 ***/
#define PWMPER0                       (*((volatile uint8 *)(&__IPSBAR[0x001B0014UL])))
#define PWMPER0_PERIOD0_BITMASK       (0x1U)
#define PWMPER0_PERIOD1_BITMASK       (0x2U)
#define PWMPER0_PERIOD2_BITMASK       (0x4U)
#define PWMPER0_PERIOD3_BITMASK       (0x8U)
#define PWMPER0_PERIOD4_BITMASK       (0x10U)
#define PWMPER0_PERIOD5_BITMASK       (0x20U)
#define PWMPER0_PERIOD6_BITMASK       (0x40U)
#define PWMPER0_PERIOD7_BITMASK       (0x80U)
#define PWMPER0_PERIOD_GRPMASK        (0xFFU)
#define PWMPER0_PERIOD_GRPPOS         (0U)

/*** PWMPER1 - PWM Channel 1 Period Register.; 0x001B0015 ***/
#define PWMPER1                       (*((volatile uint8 *)(&__IPSBAR[0x001B0015UL])))
#define PWMPER1_PERIOD0_BITMASK       (0x1U)
#define PWMPER1_PERIOD1_BITMASK       (0x2U)
#define PWMPER1_PERIOD2_BITMASK       (0x4U)
#define PWMPER1_PERIOD3_BITMASK       (0x8U)
#define PWMPER1_PERIOD4_BITMASK       (0x10U)
#define PWMPER1_PERIOD5_BITMASK       (0x20U)
#define PWMPER1_PERIOD6_BITMASK       (0x40U)
#define PWMPER1_PERIOD7_BITMASK       (0x80U)
#define PWMPER1_PERIOD_GRPMASK        (0xFFU)
#define PWMPER1_PERIOD_GRPPOS         (0U)

/*** PWMPER23 - PWM Channel Period 23 Register; 0x001B0016 ***/
#define PWMPER23                      (*((volatile uint16 *)(&__IPSBAR[0x001B0016UL])))
#define PWMPER23_BIT0_BITMASK         (0x1U)
#define PWMPER23_BIT1_BITMASK         (0x2U)
#define PWMPER23_BIT2_BITMASK         (0x4U)
#define PWMPER23_BIT3_BITMASK         (0x8U)
#define PWMPER23_BIT4_BITMASK         (0x10U)
#define PWMPER23_BIT5_BITMASK         (0x20U)
#define PWMPER23_BIT6_BITMASK         (0x40U)
#define PWMPER23_BIT7_BITMASK         (0x80U)
#define PWMPER23_BIT8_BITMASK         (0x100U)
#define PWMPER23_BIT9_BITMASK         (0x200U)
#define PWMPER23_BIT10_BITMASK        (0x400U)
#define PWMPER23_BIT11_BITMASK        (0x800U)
#define PWMPER23_BIT12_BITMASK        (0x1000U)
#define PWMPER23_BIT13_BITMASK        (0x2000U)
#define PWMPER23_BIT14_BITMASK        (0x4000U)
#define PWMPER23_BIT15_BITMASK        (0x8000U)

/*** PWMPER2 - PWM Channel 2 Period Register.; 0x001B0016 ***/
#define PWMPER2                       (*((volatile uint8 *)(&__IPSBAR[0x001B0016UL])))
#define PWMPER2_PERIOD0_BITMASK       (0x1U)
#define PWMPER2_PERIOD1_BITMASK       (0x2U)
#define PWMPER2_PERIOD2_BITMASK       (0x4U)
#define PWMPER2_PERIOD3_BITMASK       (0x8U)
#define PWMPER2_PERIOD4_BITMASK       (0x10U)
#define PWMPER2_PERIOD5_BITMASK       (0x20U)
#define PWMPER2_PERIOD6_BITMASK       (0x40U)
#define PWMPER2_PERIOD7_BITMASK       (0x80U)
#define PWMPER2_PERIOD_GRPMASK        (0xFFU)
#define PWMPER2_PERIOD_GRPPOS         (0U)

/*** PWMPER3 - PWM Channel 3 Period Register.; 0x001B0017 ***/
#define PWMPER3                       (*((volatile uint8 *)(&__IPSBAR[0x001B0017UL])))
#define PWMPER3_PERIOD0_BITMASK       (0x1U)
#define PWMPER3_PERIOD1_BITMASK       (0x2U)
#define PWMPER3_PERIOD2_BITMASK       (0x4U)
#define PWMPER3_PERIOD3_BITMASK       (0x8U)
#define PWMPER3_PERIOD4_BITMASK       (0x10U)
#define PWMPER3_PERIOD5_BITMASK       (0x20U)
#define PWMPER3_PERIOD6_BITMASK       (0x40U)
#define PWMPER3_PERIOD7_BITMASK       (0x80U)
#define PWMPER3_PERIOD_GRPMASK        (0xFFU)
#define PWMPER3_PERIOD_GRPPOS         (0U)

/*** PWMPER45 - PWM Channel Period 45 Register; 0x001B0018 ***/
#define PWMPER45                      (*((volatile uint16 *)(&__IPSBAR[0x001B0018UL])))
#define PWMPER45_BIT0_BITMASK         (0x1U)
#define PWMPER45_BIT1_BITMASK         (0x2U)
#define PWMPER45_BIT2_BITMASK         (0x4U)
#define PWMPER45_BIT3_BITMASK         (0x8U)
#define PWMPER45_BIT4_BITMASK         (0x10U)
#define PWMPER45_BIT5_BITMASK         (0x20U)
#define PWMPER45_BIT6_BITMASK         (0x40U)
#define PWMPER45_BIT7_BITMASK         (0x80U)
#define PWMPER45_BIT8_BITMASK         (0x100U)
#define PWMPER45_BIT9_BITMASK         (0x200U)
#define PWMPER45_BIT10_BITMASK        (0x400U)
#define PWMPER45_BIT11_BITMASK        (0x800U)
#define PWMPER45_BIT12_BITMASK        (0x1000U)
#define PWMPER45_BIT13_BITMASK        (0x2000U)
#define PWMPER45_BIT14_BITMASK        (0x4000U)
#define PWMPER45_BIT15_BITMASK        (0x8000U)

/*** PWMPER4 - PWM Channel 4 Period Register.; 0x001B0018 ***/
#define PWMPER4                       (*((volatile uint8 *)(&__IPSBAR[0x001B0018UL])))
#define PWMPER4_PERIOD0_BITMASK       (0x1U)
#define PWMPER4_PERIOD1_BITMASK       (0x2U)
#define PWMPER4_PERIOD2_BITMASK       (0x4U)
#define PWMPER4_PERIOD3_BITMASK       (0x8U)
#define PWMPER4_PERIOD4_BITMASK       (0x10U)
#define PWMPER4_PERIOD5_BITMASK       (0x20U)
#define PWMPER4_PERIOD6_BITMASK       (0x40U)
#define PWMPER4_PERIOD7_BITMASK       (0x80U)
#define PWMPER4_PERIOD_GRPMASK        (0xFFU)
#define PWMPER4_PERIOD_GRPPOS         (0U)

/*** PWMPER5 - PWM Channel 5 Period Register.; 0x001B0019 ***/
#define PWMPER5                       (*((volatile uint8 *)(&__IPSBAR[0x001B0019UL])))
#define PWMPER5_PERIOD0_BITMASK       (0x1U)
#define PWMPER5_PERIOD1_BITMASK       (0x2U)
#define PWMPER5_PERIOD2_BITMASK       (0x4U)
#define PWMPER5_PERIOD3_BITMASK       (0x8U)
#define PWMPER5_PERIOD4_BITMASK       (0x10U)
#define PWMPER5_PERIOD5_BITMASK       (0x20U)
#define PWMPER5_PERIOD6_BITMASK       (0x40U)
#define PWMPER5_PERIOD7_BITMASK       (0x80U)
#define PWMPER5_PERIOD_GRPMASK        (0xFFU)
#define PWMPER5_PERIOD_GRPPOS         (0U)

/*** PWMPER67 - PWM Channel Period 67 Register; 0x001B001A ***/
#define PWMPER67                      (*((volatile uint16 *)(&__IPSBAR[0x001B001AUL])))
#define PWMPER67_BIT0_BITMASK         (0x1U)
#define PWMPER67_BIT1_BITMASK         (0x2U)
#define PWMPER67_BIT2_BITMASK         (0x4U)
#define PWMPER67_BIT3_BITMASK         (0x8U)
#define PWMPER67_BIT4_BITMASK         (0x10U)
#define PWMPER67_BIT5_BITMASK         (0x20U)
#define PWMPER67_BIT6_BITMASK         (0x40U)
#define PWMPER67_BIT7_BITMASK         (0x80U)
#define PWMPER67_BIT8_BITMASK         (0x100U)
#define PWMPER67_BIT9_BITMASK         (0x200U)
#define PWMPER67_BIT10_BITMASK        (0x400U)
#define PWMPER67_BIT11_BITMASK        (0x800U)
#define PWMPER67_BIT12_BITMASK        (0x1000U)
#define PWMPER67_BIT13_BITMASK        (0x2000U)
#define PWMPER67_BIT14_BITMASK        (0x4000U)
#define PWMPER67_BIT15_BITMASK        (0x8000U)

/*** PWMPER6 - PWM Channel 6 Period Register.; 0x001B001A ***/
#define PWMPER6                       (*((volatile uint8 *)(&__IPSBAR[0x001B001AUL])))
#define PWMPER6_PERIOD0_BITMASK       (0x1U)
#define PWMPER6_PERIOD1_BITMASK       (0x2U)
#define PWMPER6_PERIOD2_BITMASK       (0x4U)
#define PWMPER6_PERIOD3_BITMASK       (0x8U)
#define PWMPER6_PERIOD4_BITMASK       (0x10U)
#define PWMPER6_PERIOD5_BITMASK       (0x20U)
#define PWMPER6_PERIOD6_BITMASK       (0x40U)
#define PWMPER6_PERIOD7_BITMASK       (0x80U)
#define PWMPER6_PERIOD_GRPMASK        (0xFFU)
#define PWMPER6_PERIOD_GRPPOS         (0U)

/*** PWMPER7 - PWM Channel 7 Period Register.; 0x001B001B ***/
#define PWMPER7                       (*((volatile uint8 *)(&__IPSBAR[0x001B001BUL])))
#define PWMPER7_PERIOD0_BITMASK       (0x1U)
#define PWMPER7_PERIOD1_BITMASK       (0x2U)
#define PWMPER7_PERIOD2_BITMASK       (0x4U)
#define PWMPER7_PERIOD3_BITMASK       (0x8U)
#define PWMPER7_PERIOD4_BITMASK       (0x10U)
#define PWMPER7_PERIOD5_BITMASK       (0x20U)
#define PWMPER7_PERIOD6_BITMASK       (0x40U)
#define PWMPER7_PERIOD7_BITMASK       (0x80U)
#define PWMPER7_PERIOD_GRPMASK        (0xFFU)
#define PWMPER7_PERIOD_GRPPOS         (0U)

/*** PWMDTY0 - PWM Channel 0 Duty Register.; 0x001B001C ***/
#define PWMDTY0                       (*((volatile uint8 *)(&__IPSBAR[0x001B001CUL])))
#define PWMDTY0_DUTY0_BITMASK         (0x1U)
#define PWMDTY0_DUTY1_BITMASK         (0x2U)
#define PWMDTY0_DUTY2_BITMASK         (0x4U)
#define PWMDTY0_DUTY3_BITMASK         (0x8U)
#define PWMDTY0_DUTY4_BITMASK         (0x10U)
#define PWMDTY0_DUTY5_BITMASK         (0x20U)
#define PWMDTY0_DUTY6_BITMASK         (0x40U)
#define PWMDTY0_DUTY7_BITMASK         (0x80U)
#define PWMDTY0_DUTY_GRPMASK          (0xFFU)
#define PWMDTY0_DUTY_GRPPOS           (0U)

/*** PWMDTY01 - PWM Channel Duty 01 Register; 0x001B001C ***/
#define PWMDTY01                      (*((volatile uint16 *)(&__IPSBAR[0x001B001CUL])))
#define PWMDTY01_BIT0_BITMASK         (0x1U)
#define PWMDTY01_BIT1_BITMASK         (0x2U)
#define PWMDTY01_BIT2_BITMASK         (0x4U)
#define PWMDTY01_BIT3_BITMASK         (0x8U)
#define PWMDTY01_BIT4_BITMASK         (0x10U)
#define PWMDTY01_BIT5_BITMASK         (0x20U)
#define PWMDTY01_BIT6_BITMASK         (0x40U)
#define PWMDTY01_BIT7_BITMASK         (0x80U)
#define PWMDTY01_BIT8_BITMASK         (0x100U)
#define PWMDTY01_BIT9_BITMASK         (0x200U)
#define PWMDTY01_BIT10_BITMASK        (0x400U)
#define PWMDTY01_BIT11_BITMASK        (0x800U)
#define PWMDTY01_BIT12_BITMASK        (0x1000U)
#define PWMDTY01_BIT13_BITMASK        (0x2000U)
#define PWMDTY01_BIT14_BITMASK        (0x4000U)
#define PWMDTY01_BIT15_BITMASK        (0x8000U)

/*** PWMDTY1 - PWM Channel 1 Duty Register.; 0x001B001D ***/
#define PWMDTY1                       (*((volatile uint8 *)(&__IPSBAR[0x001B001DUL])))
#define PWMDTY1_DUTY0_BITMASK         (0x1U)
#define PWMDTY1_DUTY1_BITMASK         (0x2U)
#define PWMDTY1_DUTY2_BITMASK         (0x4U)
#define PWMDTY1_DUTY3_BITMASK         (0x8U)
#define PWMDTY1_DUTY4_BITMASK         (0x10U)
#define PWMDTY1_DUTY5_BITMASK         (0x20U)
#define PWMDTY1_DUTY6_BITMASK         (0x40U)
#define PWMDTY1_DUTY7_BITMASK         (0x80U)
#define PWMDTY1_DUTY_GRPMASK          (0xFFU)
#define PWMDTY1_DUTY_GRPPOS           (0U)

/*** PWMDTY2 - PWM Channel 2 Duty Register.; 0x001B001E ***/
#define PWMDTY2                       (*((volatile uint8 *)(&__IPSBAR[0x001B001EUL])))
#define PWMDTY2_DUTY0_BITMASK         (0x1U)
#define PWMDTY2_DUTY1_BITMASK         (0x2U)
#define PWMDTY2_DUTY2_BITMASK         (0x4U)
#define PWMDTY2_DUTY3_BITMASK         (0x8U)
#define PWMDTY2_DUTY4_BITMASK         (0x10U)
#define PWMDTY2_DUTY5_BITMASK         (0x20U)
#define PWMDTY2_DUTY6_BITMASK         (0x40U)
#define PWMDTY2_DUTY7_BITMASK         (0x80U)
#define PWMDTY2_DUTY_GRPMASK          (0xFFU)
#define PWMDTY2_DUTY_GRPPOS           (0U)

/*** PWMDTY23 - PWM Channel Duty 23 Register; 0x001B001E ***/
#define PWMDTY23                      (*((volatile uint16 *)(&__IPSBAR[0x001B001EUL])))
#define PWMDTY23_BIT0_BITMASK         (0x1U)
#define PWMDTY23_BIT1_BITMASK         (0x2U)
#define PWMDTY23_BIT2_BITMASK         (0x4U)
#define PWMDTY23_BIT3_BITMASK         (0x8U)
#define PWMDTY23_BIT4_BITMASK         (0x10U)
#define PWMDTY23_BIT5_BITMASK         (0x20U)
#define PWMDTY23_BIT6_BITMASK         (0x40U)
#define PWMDTY23_BIT7_BITMASK         (0x80U)
#define PWMDTY23_BIT8_BITMASK         (0x100U)
#define PWMDTY23_BIT9_BITMASK         (0x200U)
#define PWMDTY23_BIT10_BITMASK        (0x400U)
#define PWMDTY23_BIT11_BITMASK        (0x800U)
#define PWMDTY23_BIT12_BITMASK        (0x1000U)
#define PWMDTY23_BIT13_BITMASK        (0x2000U)
#define PWMDTY23_BIT14_BITMASK        (0x4000U)
#define PWMDTY23_BIT15_BITMASK        (0x8000U)

/*** PWMDTY3 - PWM Channel 3 Duty Register.; 0x001B001F ***/
#define PWMDTY3                       (*((volatile uint8 *)(&__IPSBAR[0x001B001FUL])))
#define PWMDTY3_DUTY0_BITMASK         (0x1U)
#define PWMDTY3_DUTY1_BITMASK         (0x2U)
#define PWMDTY3_DUTY2_BITMASK         (0x4U)
#define PWMDTY3_DUTY3_BITMASK         (0x8U)
#define PWMDTY3_DUTY4_BITMASK         (0x10U)
#define PWMDTY3_DUTY5_BITMASK         (0x20U)
#define PWMDTY3_DUTY6_BITMASK         (0x40U)
#define PWMDTY3_DUTY7_BITMASK         (0x80U)
#define PWMDTY3_DUTY_GRPMASK          (0xFFU)
#define PWMDTY3_DUTY_GRPPOS           (0U)

/*** PWMDTY4 - PWM Channel 4 Duty Register.; 0x001B0020 ***/
#define PWMDTY4                       (*((volatile uint8 *)(&__IPSBAR[0x001B0020UL])))
#define PWMDTY4_DUTY0_BITMASK         (0x1U)
#define PWMDTY4_DUTY1_BITMASK         (0x2U)
#define PWMDTY4_DUTY2_BITMASK         (0x4U)
#define PWMDTY4_DUTY3_BITMASK         (0x8U)
#define PWMDTY4_DUTY4_BITMASK         (0x10U)
#define PWMDTY4_DUTY5_BITMASK         (0x20U)
#define PWMDTY4_DUTY6_BITMASK         (0x40U)
#define PWMDTY4_DUTY7_BITMASK         (0x80U)
#define PWMDTY4_DUTY_GRPMASK          (0xFFU)
#define PWMDTY4_DUTY_GRPPOS           (0U)

/*** PWMDTY45 - PWM Channel Duty 45 Register; 0x001B0020 ***/
#define PWMDTY45                      (*((volatile uint16 *)(&__IPSBAR[0x001B0020UL])))
#define PWMDTY45_BIT0_BITMASK         (0x1U)
#define PWMDTY45_BIT1_BITMASK         (0x2U)
#define PWMDTY45_BIT2_BITMASK         (0x4U)
#define PWMDTY45_BIT3_BITMASK         (0x8U)
#define PWMDTY45_BIT4_BITMASK         (0x10U)
#define PWMDTY45_BIT5_BITMASK         (0x20U)
#define PWMDTY45_BIT6_BITMASK         (0x40U)
#define PWMDTY45_BIT7_BITMASK         (0x80U)
#define PWMDTY45_BIT8_BITMASK         (0x100U)
#define PWMDTY45_BIT9_BITMASK         (0x200U)
#define PWMDTY45_BIT10_BITMASK        (0x400U)
#define PWMDTY45_BIT11_BITMASK        (0x800U)
#define PWMDTY45_BIT12_BITMASK        (0x1000U)
#define PWMDTY45_BIT13_BITMASK        (0x2000U)
#define PWMDTY45_BIT14_BITMASK        (0x4000U)
#define PWMDTY45_BIT15_BITMASK        (0x8000U)

/*** PWMDTY5 - PWM Channel 5 Duty Register.; 0x001B0021 ***/
#define PWMDTY5                       (*((volatile uint8 *)(&__IPSBAR[0x001B0021UL])))
#define PWMDTY5_DUTY0_BITMASK         (0x1U)
#define PWMDTY5_DUTY1_BITMASK         (0x2U)
#define PWMDTY5_DUTY2_BITMASK         (0x4U)
#define PWMDTY5_DUTY3_BITMASK         (0x8U)
#define PWMDTY5_DUTY4_BITMASK         (0x10U)
#define PWMDTY5_DUTY5_BITMASK         (0x20U)
#define PWMDTY5_DUTY6_BITMASK         (0x40U)
#define PWMDTY5_DUTY7_BITMASK         (0x80U)
#define PWMDTY5_DUTY_GRPMASK          (0xFFU)
#define PWMDTY5_DUTY_GRPPOS           (0U)

/*** PWMDTY6 - PWM Channel 6 Duty Register.; 0x001B0022 ***/
#define PWMDTY6                       (*((volatile uint8 *)(&__IPSBAR[0x001B0022UL])))
#define PWMDTY6_DUTY0_BITMASK         (0x1U)
#define PWMDTY6_DUTY1_BITMASK         (0x2U)
#define PWMDTY6_DUTY2_BITMASK         (0x4U)
#define PWMDTY6_DUTY3_BITMASK         (0x8U)
#define PWMDTY6_DUTY4_BITMASK         (0x10U)
#define PWMDTY6_DUTY5_BITMASK         (0x20U)
#define PWMDTY6_DUTY6_BITMASK         (0x40U)
#define PWMDTY6_DUTY7_BITMASK         (0x80U)
#define PWMDTY6_DUTY_GRPMASK          (0xFFU)
#define PWMDTY6_DUTY_GRPPOS           (0U)

/*** PWMDTY67 - PWM Channel Duty 67 Register; 0x001B0022 ***/
#define PWMDTY67                      (*((volatile uint16 *)(&__IPSBAR[0x001B0022UL])))
#define PWMDTY67_BIT0_BITMASK         (0x1U)
#define PWMDTY67_BIT1_BITMASK         (0x2U)
#define PWMDTY67_BIT2_BITMASK         (0x4U)
#define PWMDTY67_BIT3_BITMASK         (0x8U)
#define PWMDTY67_BIT4_BITMASK         (0x10U)
#define PWMDTY67_BIT5_BITMASK         (0x20U)
#define PWMDTY67_BIT6_BITMASK         (0x40U)
#define PWMDTY67_BIT7_BITMASK         (0x80U)
#define PWMDTY67_BIT8_BITMASK         (0x100U)
#define PWMDTY67_BIT9_BITMASK         (0x200U)
#define PWMDTY67_BIT10_BITMASK        (0x400U)
#define PWMDTY67_BIT11_BITMASK        (0x800U)
#define PWMDTY67_BIT12_BITMASK        (0x1000U)
#define PWMDTY67_BIT13_BITMASK        (0x2000U)
#define PWMDTY67_BIT14_BITMASK        (0x4000U)
#define PWMDTY67_BIT15_BITMASK        (0x8000U)

/*** PWMDTY7 - PWM Channel 7 Duty Register.; 0x001B0023 ***/
#define PWMDTY7                       (*((volatile uint8 *)(&__IPSBAR[0x001B0023UL])))
#define PWMDTY7_DUTY0_BITMASK         (0x1U)
#define PWMDTY7_DUTY1_BITMASK         (0x2U)
#define PWMDTY7_DUTY2_BITMASK         (0x4U)
#define PWMDTY7_DUTY3_BITMASK         (0x8U)
#define PWMDTY7_DUTY4_BITMASK         (0x10U)
#define PWMDTY7_DUTY5_BITMASK         (0x20U)
#define PWMDTY7_DUTY6_BITMASK         (0x40U)
#define PWMDTY7_DUTY7_BITMASK         (0x80U)
#define PWMDTY7_DUTY_GRPMASK          (0xFFU)
#define PWMDTY7_DUTY_GRPPOS           (0U)

/*** PWMSDN - PWM Shutdown Register.; 0x001B0024 ***/
#define PWMSDN                        (*((volatile uint8 *)(&__IPSBAR[0x001B0024UL])))
#define PWMSDN_SDNEN_BITMASK          (0x1U)
#define PWMSDN_PWM7IL_BITMASK         (0x2U)
#define PWMSDN_PWM7IN_BITMASK         (0x4U)
#define PWMSDN_LVL_BITMASK            (0x10U)
#define PWMSDN_RESTART_BITMASK        (0x20U)
#define PWMSDN_IE_BITMASK             (0x40U)
#define PWMSDN_IF_BITMASK             (0x80U)


/******************************************
*** Peripheral CFM
*******************************************/

/*** CFMMCR - CFM Module Configuration Register.; 0x001D0000 ***/
#define CFMMCR                        (*((volatile uint16 *)(&__IPSBAR[0x001D0000UL])))
#define CFMMCR_KEYACC_BITMASK         (0x20U)
#define CFMMCR_CCIE_BITMASK           (0x40U)
#define CFMMCR_CBEIE_BITMASK          (0x80U)
#define CFMMCR_AEIE_BITMASK           (0x100U)
#define CFMMCR_PVIE_BITMASK           (0x200U)
#define CFMMCR_LOCK_BITMASK           (0x400U)

/*** CFMCLKD - CFM Clock Divider Register.; 0x001D0002 ***/
#define CFMCLKD                       (*((volatile uint8 *)(&__IPSBAR[0x001D0002UL])))
#define CFMCLKD_DIV0_BITMASK          (0x1U)
#define CFMCLKD_DIV1_BITMASK          (0x2U)
#define CFMCLKD_DIV2_BITMASK          (0x4U)
#define CFMCLKD_DIV3_BITMASK          (0x8U)
#define CFMCLKD_DIV4_BITMASK          (0x10U)
#define CFMCLKD_DIV5_BITMASK          (0x20U)
#define CFMCLKD_PRDIV8_BITMASK        (0x40U)
#define CFMCLKD_DIVLD_BITMASK         (0x80U)
#define CFMCLKD_DIV_GRPMASK           (0x3FU)
#define CFMCLKD_DIV_GRPPOS            (0U)

/*** CFMSEC - CFM Security Register.; 0x001D0008 ***/
#define CFMSEC                        (*((volatile uint32 *)(&__IPSBAR[0x001D0008UL])))
#define CFMSEC_SEC0_BITMASK           (0x1U)
#define CFMSEC_SEC1_BITMASK           (0x2U)
#define CFMSEC_SEC2_BITMASK           (0x4U)
#define CFMSEC_SEC3_BITMASK           (0x8U)
#define CFMSEC_SEC4_BITMASK           (0x10U)
#define CFMSEC_SEC5_BITMASK           (0x20U)
#define CFMSEC_SEC6_BITMASK           (0x40U)
#define CFMSEC_SEC7_BITMASK           (0x80U)
#define CFMSEC_SEC8_BITMASK           (0x100U)
#define CFMSEC_SEC9_BITMASK           (0x200U)
#define CFMSEC_SEC10_BITMASK          (0x400U)
#define CFMSEC_SEC11_BITMASK          (0x800U)
#define CFMSEC_SEC12_BITMASK          (0x1000U)
#define CFMSEC_SEC13_BITMASK          (0x2000U)
#define CFMSEC_SEC14_BITMASK          (0x4000U)
#define CFMSEC_SEC15_BITMASK          (0x8000U)
#define CFMSEC_SECSTAT_BITMASK        (0x40000000U)
#define CFMSEC_KEYEN_BITMASK          (0x80000000U)
#define CFMSEC_SEC_GRPMASK            (0xFFFFU)
#define CFMSEC_SEC_GRPPOS             (0U)

/*** CFMPROT - CFM Protection Register.; 0x001D0010 ***/
#define CFMPROT                       (*((volatile uint32 *)(&__IPSBAR[0x001D0010UL])))
#define CFMPROT_PROTECT0_BITMASK      (0x1U)
#define CFMPROT_PROTECT1_BITMASK      (0x2U)
#define CFMPROT_PROTECT2_BITMASK      (0x4U)
#define CFMPROT_PROTECT3_BITMASK      (0x8U)
#define CFMPROT_PROTECT4_BITMASK      (0x10U)
#define CFMPROT_PROTECT5_BITMASK      (0x20U)
#define CFMPROT_PROTECT6_BITMASK      (0x40U)
#define CFMPROT_PROTECT7_BITMASK      (0x80U)
#define CFMPROT_PROTECT8_BITMASK      (0x100U)
#define CFMPROT_PROTECT9_BITMASK      (0x200U)
#define CFMPROT_PROTECT10_BITMASK     (0x400U)
#define CFMPROT_PROTECT11_BITMASK     (0x800U)
#define CFMPROT_PROTECT12_BITMASK     (0x1000U)
#define CFMPROT_PROTECT13_BITMASK     (0x2000U)
#define CFMPROT_PROTECT14_BITMASK     (0x4000U)
#define CFMPROT_PROTECT15_BITMASK     (0x8000U)
#define CFMPROT_PROTECT16_BITMASK     (0x10000U)
#define CFMPROT_PROTECT17_BITMASK     (0x20000U)
#define CFMPROT_PROTECT18_BITMASK     (0x40000U)
#define CFMPROT_PROTECT19_BITMASK     (0x80000U)
#define CFMPROT_PROTECT20_BITMASK     (0x100000U)
#define CFMPROT_PROTECT21_BITMASK     (0x200000U)
#define CFMPROT_PROTECT22_BITMASK     (0x400000U)
#define CFMPROT_PROTECT23_BITMASK     (0x800000U)
#define CFMPROT_PROTECT24_BITMASK     (0x1000000U)
#define CFMPROT_PROTECT25_BITMASK     (0x2000000U)
#define CFMPROT_PROTECT26_BITMASK     (0x4000000U)
#define CFMPROT_PROTECT27_BITMASK     (0x8000000U)
#define CFMPROT_PROTECT28_BITMASK     (0x10000000U)
#define CFMPROT_PROTECT29_BITMASK     (0x20000000U)
#define CFMPROT_PROTECT30_BITMASK     (0x40000000U)
#define CFMPROT_PROTECT31_BITMASK     (0x80000000U)
#define CFMPROT_PROTECT_GRPMASK       (0xFFFFFFFFU)
#define CFMPROT_PROTECT_GRPPOS        (0U)

/*** CFMSACC - CFM Supervisor Access Register.; 0x001D0014 ***/
#define CFMSACC                       (*((volatile uint32 *)(&__IPSBAR[0x001D0014UL])))
#define CFMSACC_SUPV0_BITMASK         (0x1U)
#define CFMSACC_SUPV1_BITMASK         (0x2U)
#define CFMSACC_SUPV2_BITMASK         (0x4U)
#define CFMSACC_SUPV3_BITMASK         (0x8U)
#define CFMSACC_SUPV4_BITMASK         (0x10U)
#define CFMSACC_SUPV5_BITMASK         (0x20U)
#define CFMSACC_SUPV6_BITMASK         (0x40U)
#define CFMSACC_SUPV7_BITMASK         (0x80U)
#define CFMSACC_SUPV8_BITMASK         (0x100U)
#define CFMSACC_SUPV9_BITMASK         (0x200U)
#define CFMSACC_SUPV10_BITMASK        (0x400U)
#define CFMSACC_SUPV11_BITMASK        (0x800U)
#define CFMSACC_SUPV12_BITMASK        (0x1000U)
#define CFMSACC_SUPV13_BITMASK        (0x2000U)
#define CFMSACC_SUPV14_BITMASK        (0x4000U)
#define CFMSACC_SUPV15_BITMASK        (0x8000U)
#define CFMSACC_SUPV16_BITMASK        (0x10000U)
#define CFMSACC_SUPV17_BITMASK        (0x20000U)
#define CFMSACC_SUPV18_BITMASK        (0x40000U)
#define CFMSACC_SUPV19_BITMASK        (0x80000U)
#define CFMSACC_SUPV20_BITMASK        (0x100000U)
#define CFMSACC_SUPV21_BITMASK        (0x200000U)
#define CFMSACC_SUPV22_BITMASK        (0x400000U)
#define CFMSACC_SUPV23_BITMASK        (0x800000U)
#define CFMSACC_SUPV24_BITMASK        (0x1000000U)
#define CFMSACC_SUPV25_BITMASK        (0x2000000U)
#define CFMSACC_SUPV26_BITMASK        (0x4000000U)
#define CFMSACC_SUPV27_BITMASK        (0x8000000U)
#define CFMSACC_SUPV28_BITMASK        (0x10000000U)
#define CFMSACC_SUPV29_BITMASK        (0x20000000U)
#define CFMSACC_SUPV30_BITMASK        (0x40000000U)
#define CFMSACC_SUPV31_BITMASK        (0x80000000U)
#define CFMSACC_SUPV_GRPMASK          (0xFFFFFFFFU)
#define CFMSACC_SUPV_GRPPOS           (0U)

/*** CFMDACC - CFM Data Access Register.; 0x001D0018 ***/
#define CFMDACC                       (*((volatile uint32 *)(&__IPSBAR[0x001D0018UL])))
#define CFMDACC_DACC0_BITMASK         (0x1U)
#define CFMDACC_DACC1_BITMASK         (0x2U)
#define CFMDACC_DACC2_BITMASK         (0x4U)
#define CFMDACC_DACC3_BITMASK         (0x8U)
#define CFMDACC_DACC4_BITMASK         (0x10U)
#define CFMDACC_DACC5_BITMASK         (0x20U)
#define CFMDACC_DACC6_BITMASK         (0x40U)
#define CFMDACC_DACC7_BITMASK         (0x80U)
#define CFMDACC_DACC8_BITMASK         (0x100U)
#define CFMDACC_DACC9_BITMASK         (0x200U)
#define CFMDACC_DACC10_BITMASK        (0x400U)
#define CFMDACC_DACC11_BITMASK        (0x800U)
#define CFMDACC_DACC12_BITMASK        (0x1000U)
#define CFMDACC_DACC13_BITMASK        (0x2000U)
#define CFMDACC_DACC14_BITMASK        (0x4000U)
#define CFMDACC_DACC15_BITMASK        (0x8000U)
#define CFMDACC_DACC16_BITMASK        (0x10000U)
#define CFMDACC_DACC17_BITMASK        (0x20000U)
#define CFMDACC_DACC18_BITMASK        (0x40000U)
#define CFMDACC_DACC19_BITMASK        (0x80000U)
#define CFMDACC_DACC20_BITMASK        (0x100000U)
#define CFMDACC_DACC21_BITMASK        (0x200000U)
#define CFMDACC_DACC22_BITMASK        (0x400000U)
#define CFMDACC_DACC23_BITMASK        (0x800000U)
#define CFMDACC_DACC24_BITMASK        (0x1000000U)
#define CFMDACC_DACC25_BITMASK        (0x2000000U)
#define CFMDACC_DACC26_BITMASK        (0x4000000U)
#define CFMDACC_DACC27_BITMASK        (0x8000000U)
#define CFMDACC_DACC28_BITMASK        (0x10000000U)
#define CFMDACC_DACC29_BITMASK        (0x20000000U)
#define CFMDACC_DACC30_BITMASK        (0x40000000U)
#define CFMDACC_DACC31_BITMASK        (0x80000000U)
#define CFMDACC_DACC_GRPMASK          (0xFFFFFFFFU)
#define CFMDACC_DACC_GRPPOS           (0U)

/*** CFMUSTAT - CFM User Status Register.; 0x001D0020 ***/
#define CFMUSTAT                      (*((volatile uint8 *)(&__IPSBAR[0x001D0020UL])))
#define CFMUSTAT_BLANK_BITMASK        (0x4U)
#define CFMUSTAT_ACCERR_BITMASK       (0x10U)
#define CFMUSTAT_PVIOL_BITMASK        (0x20U)
#define CFMUSTAT_CCIF_BITMASK         (0x40U)
#define CFMUSTAT_CBEIF_BITMASK        (0x80U)

/*** CFMCMD - CFM Command Register.; 0x001D0024 ***/
#define CFMCMD                        (*((volatile uint8 *)(&__IPSBAR[0x001D0024UL])))
#define CFMCMD_CMD0_BITMASK           (0x1U)
#define CFMCMD_CMD1_BITMASK           (0x2U)
#define CFMCMD_CMD2_BITMASK           (0x4U)
#define CFMCMD_CMD3_BITMASK           (0x8U)
#define CFMCMD_CMD4_BITMASK           (0x10U)
#define CFMCMD_CMD5_BITMASK           (0x20U)
#define CFMCMD_CMD6_BITMASK           (0x40U)
#define CFMCMD_CMD_GRPMASK            (0x7FU)
#define CFMCMD_CMD_GRPPOS             (0U)

/*** CFMCLKSEL - CFM Clock Select Register.; 0x001D004A ***/
#define CFMCLKSEL                     (*((volatile uint16 *)(&__IPSBAR[0x001D004AUL])))
#define CFMCLKSEL_CLKSEL0_BITMASK     (0x1U)
#define CFMCLKSEL_CLKSEL1_BITMASK     (0x2U)
#define CFMCLKSEL_CLKSEL_GRPMASK      (0x3U)
#define CFMCLKSEL_CLKSEL_GRPPOS       (0U)


/******************************************
*** Peripheral EPHY
*******************************************/

/*** EPHYCTL0 - Ethernet Physical Transceiver Control Register 0.; 0x001E0000 ***/
#define EPHYCTL0                      (*((volatile uint8 *)(&__IPSBAR[0x001E0000UL])))
#define EPHYCTL0_EPHYIEN_BITMASK      (0x1U)
#define EPHYCTL0_EPHYWAI_BITMASK      (0x4U)
#define EPHYCTL0_LEDEN_BITMASK        (0x8U)
#define EPHYCTL0_DIS10_BITMASK        (0x10U)
#define EPHYCTL0_DIS100_BITMASK       (0x20U)
#define EPHYCTL0_ANDIS_BITMASK        (0x40U)
#define EPHYCTL0_EPHYEN_BITMASK       (0x80U)

/*** EPHYCTL1 - Ethernet Physical Transceiver Control Register 1.; 0x001E0001 ***/
#define EPHYCTL1                      (*((volatile uint8 *)(&__IPSBAR[0x001E0001UL])))
#define EPHYCTL1_PHYADD0_BITMASK      (0x1U)
#define EPHYCTL1_PHYADD1_BITMASK      (0x2U)
#define EPHYCTL1_PHYADD2_BITMASK      (0x4U)
#define EPHYCTL1_PHYADD3_BITMASK      (0x8U)
#define EPHYCTL1_PHYADD4_BITMASK      (0x10U)
#define EPHYCTL1_PHYADD_GRPMASK       (0x1FU)
#define EPHYCTL1_PHYADD_GRPPOS        (0U)

/*** EPHYSR -  Ethernet Physical Transceiver Status Register.; 0x001E0002 ***/
#define EPHYSR                        (*((volatile uint8 *)(&__IPSBAR[0x001E0002UL])))
#define EPHYSR_EPHYIF_BITMASK         (0x1U)
#define EPHYSR_10DIS_BITMASK          (0x10U)
#define EPHYSR_100DIS_BITMASK         (0x20U)


#endif /* __MCF52233_H */
