INTERRUPT STATUS REGISTER (ISR)

 7       6       5       4      3       2      1       0
RST     RDC     CNT     OVW    TXE     RXE    PTX     PRX

Bit Symbol Description

D0 PRX PACKET RECEIVED: Indicates packet received with no errors.
D1 PTX PACKET TRANSMITTED: Indicates packet transmitted with no errors.
D2 RXE RECEIVE ERROR: Indicates that a packet was received with one or
                      more of the following errors: CRC  Error Frame
                                                    Alignment Error
                                                    FIFO Overrun
                                                    Missed Packet
D3 TXE TRANSMIT ERROR: Set when packet transmitted with one or more of the
                       following errors:Excessive Collisions
                                        FIFO Underrun
D4 OVW OVERWRITE WARNING: Set when receive buffer ring storage resources have
                          been exhausted. (Local DMA has reached Boundary
                          Pointer).
D5 CNT COUNTER OVERFLOW: Set when MSB of one or more of the Network Tally
                         Counters has been set.
D6 RDC REMOTE DMA COMPLETE: Set when Remote DMA operation has been completed.
D7 RST RESET STATUS: Set when NIC enters reset state and cleared when a Start
                     Command is issued to the CR. This bit is also set when a
                     Receive Buffer Ring overflow occurs and is cleared when
                     one or more packets have been removed from the ring.
 
 
 

           TRANSMIT STATUS REGISTER

 7       6      5        4        3        2      1       0
OWC     CDH     FU      CRS      ABT      COL     0      PTX

Bit Symbol Description

D0 PTX  PACKET TRANSMITTED: Indicates transmission without error.
                            (No excessivecollisions or FIFO underrun) .
D1      reserved 
D2 COL  TRANSMIT COLLIDED: Indicates that the transmission collided at least
                           once with another station on the network. The
                           number of collisions is recorded in the Number
                           of Collisions Registers (NCR).
D3 ABT  TRANSMIT ABORTED: Indicates the NIC aborted transmission because
                          of excessive collisions. (Total number of
                          transmissions including original transmission
                          attempt equals 16).
D4 CRS  CARRIER SENSE LOST: This bit is set when carrier is lost during transmission
                            of the packet. Carrier Sense is monitored from
                            the end of Preamble/Synch until TXEN is dropped.
                            Transmission is not aborted on loss of carrier.
D5 FU  FIFO UNDERRUN: If the NIC cannot gain access of the bus before the
                       FIFO empties, this bit is set. Transmission of the
                       packet will be aborted.
D6 CDH  CD HEARTBEAT: Failure of the transceiver to transmit a collision
                      signal after transmission of a packet will set this bit.
                      The Collision Detect (CD) heartbeat signal must commence
                      during the first 6.4 ms of the Interframe Gap following
                      a transmission. In certain collisions, the CD Heartbeat
                      bit will be set even though the transceiver is not
                      performing the CD heartbeat test.
D7 OWC  OUT OF WINDOW COLLISION: Indicates that a collision occurred after a
                                 slot time (51.2 ms). Transmissions
                                 rescheduled  as in normal collisions.
 
 

           RECEIVE STATUS REGISTER

 7       6       5       4      3       2       1       0
DFR     DIS     PHY     MPA     FO     FAE     CRC     PRX

Bit Symbol Description

D0 PRX PACKET RECEIVED INTACT: Indicates packet received without error.
D1 CRC CRC ERROR:  Indicates packet received with CRC error.
D2 FAE FRAME ALIGNMENT ERROR: Indicates that the incoming packet did not end
                              on a byte boundary and the CRC did not match at
                              last byte boundary. Increments Tally Counter .
D3 FO FIFO OVERRUN: This bit is set when the FIFO is not serviced causing
                    overflow during reception. Reception of the packet will
                    be aborted.
D4 MPA MISSED PACKET: Set when packet intended for node cannot be accepted
                      by NIC because of a lack of receive buffers or if the
                      controller is in monitor mode and did not buffer the
                      packet to memory.
D5 PHY PHYSICAL/MULTICAST ADDRESS: Indicates whether received packet had a
                                   physical or multicast address type.
                       0: Physical Address Match
                       1: Multicast/Broadcast Address Match
D6 DIS RECEIVER DISABLED: Set when receiver disabled by entering Monitor mode.
                          Reset when receiver is re-enabled when exiting
                          Monitor mode.
D7 DFR DEFERRING: Set when CRS or COL inputs are active. If the transceiver
                  has asserted the CD line as a result of the jabber, this
                  bit will stay set indicating the jabber condition.
                  Note: Following coding applies to CRC and FAE bits
                  FAE CRC Type of Error
                   0   0  No Error (Good CRC and k6 Dribble Bits)
                   0   1  CRC Error
                   1   0  Illegal, will not occur
                   1   1  Frame Alignment Error and CRC Error